Release 14.2 - xst P.

28xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
--> Reading design: BCD_Addition.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
*
Synthesis Options Summary
*
=========================================================================
---- Source Parameters
Input File Name
: "BCD_Addition.prj"
Input Format
: mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name
Output Format
Target Device

: "BCD_Addition"
: NGC
: xc3s500e-4-fg320

---- Source Options

Top Module Name
Automatic FSM Extraction
FSM Encoding Algorithm
Safe Implementation
FSM Style
RAM Extraction
RAM Style
ROM Extraction
Mux Style
Decoder Extraction
Priority Encoder Extraction
Shift Register Extraction
Logical Shifter Extraction

:
:
:
:
:
:
:
:
:
:
:
:
:

BCD_Addition
YES
Auto
No
LUT
Yes
Auto
Yes
Auto
YES
Yes
YES
YES

XOR Collapsing
ROM Style
Mux Extraction
Resource Sharing
Asynchronous To Synchronous
Multiplier Style
Automatic Register Balancing

:
:
:
:
:
:
:

YES
Auto
Yes
YES
NO
Auto
No

---- Target Options

Add IO Buffers
Global Maximum Fanout
Add Generic Clock Buffer(BUFG)
Register Duplication
Slice Packing
Optimize Instantiated Primitives
Use Clock Enable
Use Synchronous Set
Use Synchronous Reset
Pack IO Registers into IOBs
Equivalent register Removal

:
:
:
:
:
:
:
:
:
:
:

YES
100000
24
YES
YES
NO
Yes
Yes
Yes
Auto
YES

---- General Options

Optimization Goal
Optimization Effort
Keep Hierarchy
Netlist Hierarchy
RTL Output
Global Optimization
Read Cores
Write Timing Constraints
Cross Clock Analysis
Hierarchy Separator
Bus Delimiter
Case Specifier
Slice Utilization Ratio
BRAM Utilization Ratio
Verilog 2001
Auto BRAM Packing
Slice Utilization Ratio Delta

:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:

Speed
1
No
As_Optimized
Yes
AllClockNets
YES
NO
NO
/
<>
Maintain
100
100
YES
NO
5

=========================================================================
=========================================================================
*
HDL Compilation
*
=========================================================================
WARNING:HDLCompilers:176 - Include directory \Users\p2vld15017\Desktop\ does not
exist
Compiling verilog file "C:/Users/p2vld15017/Desktop/BCD_Addition.v" in library w
ork
Module <BCD_Addition> compiled
No errors in compilation
Analysis of file <"BCD_Addition.prj"> succeeded.
=========================================================================
*
Design Hierarchy Analysis
*
=========================================================================
Analyzing hierarchy for module <BCD_Addition> in library <work>.

=========================================================================
*
HDL Analysis
*
=========================================================================
Analyzing top module <BCD_Addition>.
Module <BCD_Addition> is correct for synthesis.
=========================================================================
*
HDL Synthesis
*
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <BCD_Addition>.
Related source file is "C:/Users/p2vld15017/Desktop/BCD_Addition.v".
Found 4-bit adder carry out for signal <sr$addsub0000>.
Found 5-bit comparator greater for signal <sum$cmp_gt0000> created at line 1
4.
Summary:
inferred 2 Adder/Subtractor(s).
inferred 1 Comparator(s).
Unit <BCD_Addition> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
4-bit adder carry out
5-bit adder
# Comparators
5-bit comparator greater

:
:
:
:
:

2
1
1
1
1

=========================================================================
=========================================================================
*
Advanced HDL Synthesis
*
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
4-bit adder carry out
5-bit adder
# Comparators
5-bit comparator greater

:
:
:
:
:

2
1
1
1
1

=========================================================================
=========================================================================
*
Low Level Synthesis
*
=========================================================================
Optimizing unit <BCD_Addition> ...

Mapping all equations...

Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block BCD_Addition, actual ratio is
0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
*
Partition Report
*
=========================================================================
Partition Implementation Status
------------------------------No Partitions were found in this design.
------------------------------=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name
: BCD_Addition.ngr
Top Level Output File Name
: BCD_Addition
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: No
Design Statistics
# IOs

: 13

Cell Usage :
# BELS
: 12
#
LUT2
: 2
#
LUT3
: 2
#
LUT4
: 7
#
MUXF5
: 1
# IO Buffers
: 13
#
IBUF
: 8
#
OBUF
: 5
=========================================================================
Device utilization summary:
--------------------------Selected Device : 3s500efg320-4
Number
Number
Number
Number

of
of
of
of

Slices:
4 input LUTs:
IOs:
bonded IOBs:

--------------------------Partition Resource Summary:

6 out of
11 out of
13
13 out of

4656
9312

0%
0%

232

5%

--------------------------No Partitions were found in this design.

--------------------------=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -4
Minimum
Minimum
Maximum
Maximum

period: No path found

input arrival time before clock: No path found
output required time after clock: No path found
combinational path delay: 10.062ns

Timing Detail:
-------------All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 94 / 5
------------------------------------------------------------------------Delay:
10.062ns (Levels of Logic = 6)
Source:
i1<1> (PAD)
Destination:
sum<1> (PAD)
Data Path: i1<1> to sum<1>
Gate
Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
2 1.218 0.622 i1_1_IBUF (i1_1_IBUF)
LUT4:I0->O
4 0.704 0.622 Madd_sr_addsub0000_cy<1>11 (Madd_s
r_addsub0000_cy<1>)
LUT4:I2->O
3 0.704 0.566 Madd__AUX_1_cy<2>11 (Madd__AUX_1_c
y<2>)
LUT4:I2->O
2 0.704 0.526 sum_or00001 (sum_or0000)
LUT2:I1->O
1 0.704 0.420 sum<1>1 (sum_1_OBUF)
OBUF:I->O
3.272
sum_1_OBUF (sum<1>)
---------------------------------------Total
10.062ns (7.306ns logic, 2.756ns route)
(72.6% logic, 27.4% route)
=========================================================================

Total REAL time to Xst completion: 6.00 secs

Total CPU time to Xst completion: 5.77 secs
-->
Total memory usage is 252088 kilobytes
Number of errors :
Number of warnings :
Number of infos
:

0 (
1 (
0 (

0 filtered)
0 filtered)
0 filtered)

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Release 14.2 - xst P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
--> Reading design: BCD_Addition.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
*
Synthesis Options Summary
*
=========================================================================

---- Source Parameters

Input File Name
Input Format
Ignore Synthesis Constraint File

: "BCD_Addition.prj"
: mixed
: NO

---- Target Parameters

Output File Name
Output Format
Target Device

: "BCD_Addition"
: NGC
: xc3s500e-4-fg320

---- Source Options

Top Module Name
Automatic FSM Extraction
FSM Encoding Algorithm
Safe Implementation
FSM Style
RAM Extraction
RAM Style
ROM Extraction
Mux Style
Decoder Extraction
Priority Encoder Extraction
Shift Register Extraction
Logical Shifter Extraction
XOR Collapsing
ROM Style
Mux Extraction
Resource Sharing
Asynchronous To Synchronous
Multiplier Style
Automatic Register Balancing

:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:

BCD_Addition
YES
Auto
No
LUT
Yes
Auto
Yes
Auto
YES
Yes
YES
YES
YES
Auto
Yes
YES
NO
Auto
No

---- Target Options

Add IO Buffers
Global Maximum Fanout
Add Generic Clock Buffer(BUFG)
Register Duplication
Slice Packing
Optimize Instantiated Primitives
Use Clock Enable
Use Synchronous Set
Use Synchronous Reset
Pack IO Registers into IOBs
Equivalent register Removal

:
:
:
:
:
:
:
:
:
:
:

YES
100000
24
YES
YES
NO
Yes
Yes
Yes
Auto
YES

---- General Options

Optimization Goal
Optimization Effort
Keep Hierarchy
Netlist Hierarchy
RTL Output
Global Optimization
Read Cores
Write Timing Constraints
Cross Clock Analysis
Hierarchy Separator
Bus Delimiter
Case Specifier
Slice Utilization Ratio
BRAM Utilization Ratio

:
:
:
:
:
:
:
:
:
:
:
:
:
:

Speed
1
No
As_Optimized
Yes
AllClockNets
YES
NO
NO
/
<>
Maintain
100
100

Verilog 2001
Auto BRAM Packing
Slice Utilization Ratio Delta

: YES
: NO
: 5

=========================================================================
=========================================================================
*
HDL Compilation
*
=========================================================================
WARNING:HDLCompilers:176 - Include directory \Users\p2vld15017\Desktop\ does not
exist
Compiling verilog file "C:/Users/p2vld15017/Desktop/BCD_Addition.v" in library w
ork
Module <BCD_Addition> compiled
No errors in compilation
Analysis of file <"BCD_Addition.prj"> succeeded.
=========================================================================
*
Design Hierarchy Analysis
*
=========================================================================
Analyzing hierarchy for module <BCD_Addition> in library <work>.
=========================================================================
*
HDL Analysis
*
=========================================================================
Analyzing top module <BCD_Addition>.
Module <BCD_Addition> is correct for synthesis.
=========================================================================
*
HDL Synthesis
*
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <BCD_Addition>.
Related source file is "C:/Users/p2vld15017/Desktop/BCD_Addition.v".
Found 4-bit adder carry out for signal <sr$addsub0000>.
Found 5-bit comparator greater for signal <sum$cmp_gt0000> created at line 1
4.
Summary:
inferred 2 Adder/Subtractor(s).
inferred 1 Comparator(s).
Unit <BCD_Addition> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
4-bit adder carry out
5-bit adder
# Comparators
5-bit comparator greater

:
:
:
:
:

2
1
1
1
1

=========================================================================

=========================================================================
*
Advanced HDL Synthesis
*
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
4-bit adder carry out
5-bit adder
# Comparators
5-bit comparator greater

:
:
:
:
:

2
1
1
1
1

=========================================================================
=========================================================================
*
Low Level Synthesis
*
=========================================================================
Optimizing unit <BCD_Addition> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block BCD_Addition, actual ratio is
0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
*
Partition Report
*
=========================================================================
Partition Implementation Status
------------------------------No Partitions were found in this design.
------------------------------=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name
: BCD_Addition.ngr
Top Level Output File Name
: BCD_Addition
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: No
Design Statistics
# IOs

: 13

Cell Usage :
# BELS
: 12
#
LUT2
: 2
#
LUT3
: 2
#
LUT4
: 7
#
MUXF5
: 1
# IO Buffers
: 13
#
IBUF
: 8
#
OBUF
: 5
=========================================================================
Device utilization summary:
--------------------------Selected Device : 3s500efg320-4
Number
Number
Number
Number

of
of
of
of

Slices:
4 input LUTs:
IOs:
bonded IOBs:

6 out of
11 out of
13
13 out of

4656
9312

0%
0%

232

5%

--------------------------Partition Resource Summary:

--------------------------No Partitions were found in this design.
--------------------------=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -4
Minimum
Minimum
Maximum
Maximum

period: No path found

input arrival time before clock: No path found
output required time after clock: No path found
combinational path delay: 10.062ns

Timing Detail:
-------------All values displayed in nanoseconds (ns)
=========================================================================

Timing constraint: Default path analysis

Total number of paths / destination ports: 94 / 5
------------------------------------------------------------------------Delay:
10.062ns (Levels of Logic = 6)
Source:
i1<1> (PAD)
Destination:
sum<1> (PAD)
Data Path: i1<1> to sum<1>
Gate
Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
2 1.218 0.622 i1_1_IBUF (i1_1_IBUF)
LUT4:I0->O
4 0.704 0.622 Madd_sr_addsub0000_cy<1>11 (Madd_s
r_addsub0000_cy<1>)
LUT4:I2->O
3 0.704 0.566 Madd__AUX_1_cy<2>11 (Madd__AUX_1_c
y<2>)
LUT4:I2->O
2 0.704 0.526 sum_or00001 (sum_or0000)
LUT2:I1->O
1 0.704 0.420 sum<1>1 (sum_1_OBUF)
OBUF:I->O
3.272
sum_1_OBUF (sum<1>)
---------------------------------------Total
10.062ns (7.306ns logic, 2.756ns route)
(72.6% logic, 27.4% route)
=========================================================================
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.77 secs
-->
Total memory usage is 252088 kilobytes
Number of errors :
Number of warnings :
Number of infos
:

0 (
1 (
0 (

0 filtered)
0 filtered)
0 filtered)