Non-Volatile Memory: Flash

(NAND and NOR)

U Ganguly
IIT Bombay
8/25/2014

Agenda
Technology Choice: NAND vs. NOR (Intel vs
Toshiba)
Open Problems
A Device solution
A Circuit Controller Challenge: SanDisk

Coming soon

NAND Device: Using Electron as wave

CONTROL GATE

FG
TOX or TD

SOURCE

DRAIN
CHANNEL

Log(# of cells)

CD or IPD

VT

Retention (0V all terminals) leakage due to defects in the

dielectric

All electrons will reach FG and hence useful! FG charging only depends upon V (~18V) with
low current (nA)
05-Sep-15

U Ganguly IIT Bombay

Read operation
Vread
Log(# of cells)

2 contacts per row of cells in NAND

large space saving c.f. NOR

4.5V

Ion /Ioff ~ 100 required Device scalability is easy.

05-Sep-15

U Ganguly IIT Bombay

NAND-> functional scaling: SLC versus MLC

Q: What is the reason for the VTH distribution?

process control and uniformity
FG interference and data patterns
Electrons are discrete; Tunneling is stochastic. Defects are stochastics
Toshiba drive to 3bit/Cell at 4x node Challenges
05-Sep-15

U Ganguly IIT Bombay

NAND Memory
Operation

High E
+V
Low E

CGate

FGate

Channel

+V

Tox

IPD

1. Fresh device

2. Program
>Tox
> IPD

V=0
-V

3. Retention
4. Erase
6

-V

Inter poly
dielectric
(Al2O3)

NOR Memory: Use electrons as particle

Ec_ox
Ec_Si

A lucky electron
does not scatter, gains
sufficient KE to go
above oxide barrier ,
then suffers a lucky
scattering into the FG

Gate action causes barrier

modulation electron
current control J (Vg)
1 in a million electrons are lucky and hence useful!
Electron injection depends upon voltage (10V) and current (mA)!
Also as channel length scales below electron mean free path, scattering reduces;
High speed but power and scaling challenge!
Q: What limits NOR write speed?

4-6F

NOR

NAND

Circuit

As program current is low, resistance of contact can be high.

S/D metal contact eliminated

2F

2F
2F

S/D need to be
contacted 812F2

As current is low, S/D contact

is not necessary 4-6 F2 (2x
denser)

Transistor Ion/Ioff
= 10 is OK.
Transistor design
easy!

Technology run off

NOR

NAND

Ex- AMD

Year 2004: Which technology would

win the day?

Density
Program
Read

Comparison

NAND cf. NOR baseline

Comment

Cell size

2x smaller

cost advantage (1 node ahead=

2 years )

Speed

100x slower

Slow

Current

1000x lower

Parallel program

2x higher

Bigger charge pumps

Power

10x lower

Programming

comparable

Read

Not random -> have to read full

string Latency high. But
parallel read possible fast

NOR vs NAND: Speed vs cost,

power was the trade-off
Simpler more scalable
Market changed from
performance (desktops) to
mobile (phones, laptops)
Cost/power & scaling won!

NAND is good for data storage

NOR is for code storage

What drives technology in Flash Memory?

Flash memory industry acquires new markets as cost per bit
reduces to sustain growth.
Current threat Hard Disk Drive to Solid State Drive

05-Sep-15

U Ganguly IIT Bombay

11

Technology run off

Ex- AMD

New challenges was scaling; new

entrants have addressed these
successfully

Extra Material
Only for reference

NAND Scalability challenge

FG

Ref for CR and FGI calculation:

J.-D Lee et al EDL 2002

CG
FG

STI
Si

S/D

1. IPD and TD does not scale

2. Scaling reduces sidewall cap => reduces CR

3.Scaling increases FGI

As NAND cells are densely packed FGs interfere

How can we scale with similar performance?
05-Sep-15

U Ganguly IIT Bombay

14

Scaling options

Planar FG improves FGI

Highk IPD improves CR

High-k IPD is still at

developmental stage
J Van Houdt et al IRPS 2005

Shaped FG

J.R. Power et al, NVSMW, 2008

Inverted T FG improves
both CR and FGI

U-shaped FG
K Kim, IEDM, 2005

Conventional
scaling
05-Sep-15

P. Blomme et al IMW 2009

No new materials needed!

U Ganguly IIT Bombay

15

Research

U Ganguly (IMW 2010)

05-Sep-15

production
Hynix 26nm (VLSI 2011)

U Ganguly IIT Bombay

16

Planar FG by Micron
High-k dielectric
FG metal with high WF
J =J (E, fB)
fB

Jin
SiO2 -> Al2O3

Si
fB

Jout
FG
Si -> TiN
CG

Charge Trap Flash

Materials wish-list
1. Trap Layer

3. Metal gate:

High trap density

2. Blocking dielectric

Si
Gate

Trap L.
Tun Ox.

High-k
High band-gap

Block Ox

Jin~jout

Jin~jout
jin>>jout

Program

High-k/metal gate application is promising!

18

High work function

Erase

Charge Trap
Flash
Materials wish-list
1. Trap Layer
Low trap density (vs. high for Program)
Deep traps
Uniform/profiled composition
2. Blocking dielectric
Low trap density
Low trap generation
High-k
High band-gap
Retention

Nitride Profile: High Vt Shift vs Longer Retention

Complex Charge Leakage Path

Step 1. Si N transport
Trap to trap
Trap to band
Step 2. Tunnel/Block oxide
Trap assisted tunneling
Direct/FN tunneling

Nitride engineering promising enabler to optimize for P/E and retention trade-off
19

Vertical NAND

Vertical NAND reduces

device size scaling
requirements

Other Challenges
Defect generation high voltage causes
electron-solid interaction bond breaking
reliability challenge
Few e.g. 100 electrons stored per FG at 20nm
node
10% loss per 10 year 1 electron loss per year
spec what is the level of perfection needed?

Conclusions
Flash memory is basically a magnetic HDD
replacement
It enables improved computation and real
time human computer interface
Its success is based on scaling power and
increasing density
Challenges are based on
Few electron effects
Reliability

Self Aligned STI SA-STI

Source: Gary Xing,
Applied Materials

UV
Mask

A Micro/NanoPhotoresist
Fabrication Introduction (PR)
Fab Operation
1. Patterning is by lithography
2. Etching can be

exposure

Solvent developer

isotropic or
Anisotropic /Line of Sight

3. Layer by Layer deposition

Conformal
line-of-sight

Anisotropic

Isotropic

4. Fill and polish

5 Implant and anneal
Ion
PR
Conformal

Line of sight

p
Ion implant using PR mask

n
p
PR mask removed by ashing

anneal

Fill by flowable
oxide or CVD

Mechanical polish

Self Aligned STI SA-STI

RIE
Photo exp/dev/clean/SEM/UV hardening
PR
CVD nitride, BARC, etc.
CVD oxide
Poly 1.1
Tox

Floating gate poly dep

Tunnel oxidation
Wet etch
Sac oxidation

Fact
Fact to
to remember:
remember:
POLYgen
grainthe
structure
RadOx offers
most
Si Substrate

control
Flash
reliable enhances
tunnel oxide
reliability

Self Aligned STI SA-STI

Resist removal

Wet clean/SEM

Poly 1.1
Tox

Self Aligned STI SA-STI

Oxide etch
Nitride removal
CMP
Poly 1.1
Tox

STI Fill
STI liner Oxidation

Fact to remember:
RadOx offers the best
corner rounding and
least encroachment

Self Aligned STI SA-STI

Photo exp/dev/clean/SEM/UV
hardening
PR

Nitride dep
Oxide dep
Poly 1.2

FG poly dep (poly 1.2)

Poly 1.1
Tox

Self Aligned STI SA-STI

Nitride/oxide etch
PR removal/clean/CD
Poly 1.2
Poly 1.1

Poly etch

Tox

Nitride removal
Oxide removal

Self Aligned STI SA-STI

FG
Tox

3D view
FG
Tox

The advantage of wings:

Wings help increase surface

area, thus increase the
capacitance between control
and floating gates. critical
for Flash coupling ratio

Self Aligned STI SA-STI

Samsung 90nm
70nm
sub-lithographic
space

The Issue with the Wings:

Wings force litho spacing to be less than half
pitch, thus demand the most advanced litho
technology

Alignment becomes more and more critical

at sub 90nm tech nodes

Hynix 90nm

< half pitch

75nm
sub-lithographic
space

FG
Tox

Micron 90nm

60nm
sub-lithographic
space

Images: Semiconductor Insight

Self Aligned STI SA-STI

PR
SiN

Nitride dep

WSix

WSix dep W dep/CoSi2

Poly 2

Control gate poly dep

ONO

FG

ONO Stack formation

Tox

Fact to remember:
RadOx/SiNgen integrated ONO stack
offers the best performance with
EOT scalability to 125A

Self Aligned STI SA-STI

Photo exp/dev/clean/SEM/UV
hardening
HM etch

SiN
WSix

PR removal

Poly 2

Cell definition

ONO

FG
Tox

S/D

S/D

Drawing rotate 90 to bit line direction

S/D implant/anneal

Self Aligned STI SA-STI

Samsung 90nm

Birds beak: sidewall ox

SiN
Toshiba 90nm

WSix
Poly 2
ONO

FG
Tox

S/D

S/D
Micron 90nm

Images: Chipworks

Self Aligned STI SA-STI

Samsung 90nm

Wordlines

3D view
Wordlines removed, FG exposed
Images: Chipworks