Introduction

Objectives

Implementation of Costas Loop

Summary

BPSK Supressed Carrier NRZ Data Demodulation

using Costas Loop on Actel Microsemi FPGA
IP Seminar
Prabhpreet Singh Dua

June 21, 2016

Introduction

Objectives

Implementation of Costas Loop

Outline
1

Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs

Objectives

Implementation of Costas Loop

Clock
Costas Loop Components
Results

Summary

Introduction

Objectives

Implementation of Costas Loop

Outline
1

Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs

Objectives

Implementation of Costas Loop

Clock
Costas Loop Components
Results

Summary

Introduction

Objectives

Implementation of Costas Loop

BPSK and NRZ

PSK: Phase Shift Keying

sin(0 t + )
Encode data in

BPSK: Binary phase shift keying

=
= m(t)sin(0 t), m(t) = 1

NRZ: Non Return to Zero

Data encoding technique
0 A, 1 +A

Summary

Introduction

Objectives

Implementation of Costas Loop

Outline
1

Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs

Objectives

Implementation of Costas Loop

Clock
Costas Loop Components
Results

Summary

Introduction

Objectives

Implementation of Costas Loop

Summary

BPSK and Coherent Demodulation

Need synchronized carrier for demodulation!

m(t)sin(0 t)

m(t)
LPF

sin(0 t)
Data: m(t) = 1 , Carrier Frequency: 0

Introduction

Objectives

Implementation of Costas Loop

Summary

Residual Carrier

Transmit a residual carrier and use a phase lock loop with narrow
loop bandwidth to obtain reference carrier:

y (t) = 2Psin(0 t + m m(t))

= 2Pcos(m )sin(0 t) + 2Psin(m m(t))cos(0 t)

|
{z
} |
{z
}
ResidualCarrier

Data

Vary power of residual carrier and data through 0 < m < 2 .

Problems:
Data power interferes with residual carrier SNR.
Carrier power could be used towards transmitting data

Introduction

Objectives

Implementation of Costas Loop

Summary

PLL

sin(0 t)
cos(0 t + )
sin(0 t)

cos(0 t + )

1
2 sin()

LPF
Loop Filter

Feedback

z}|{
cos(0 t + )

VCO

Introduction

Objectives

Implementation of Costas Loop

Problems in residual carrier method

Problems:
Data power interferes with residual carrier SNR.
Carrier power could be used towards transmitting data

Summary

Introduction

Objectives

Implementation of Costas Loop

Summary

Supressed Carrier

Use all power for transmitting data.

y (t) = 2Pm(t)sin(0 t)
Problem: PLL needs a carrier reference to track!
Solution: Use Costas Loop which can reconstruct carrier reference
for tracking (a special kind of PLL).

Introduction

Objectives

Implementation of Costas Loop

Summary

Costas Loop

1
m(t) {cos()
2

1
m(t)cos()
2

cos(20 t + )}

LPF
sin(0 t + )

m(t)sin(0 t)

1 2
m (t)sin(2)
8

VCO

Loop Filter
=

cos(0 t + )

1
sin(2)
8

LPF
1
m(t) {sin()
2

+ sin(20 t + )}

1
m(t)sin()
2

Introduction

Objectives

Implementation of Costas Loop

Outline
1

Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs

Objectives

Implementation of Costas Loop

Clock
Costas Loop Components
Results

Summary

Introduction

Objectives

Implementation of Costas Loop

Summary

Costas Loop as BPSK Demodulator

In-phase arm of Costas Loop can be used to demodulate BSPK
when loop is locked, i.e. = 0!
1
m(t) {cos(0)
2

1
2 m(t)

cos(20 t)}

LPF
sin(0 t)

m(t)sin(0 t)

VCO

Loop Filter

cos(0 t)

LPF
1
m(t) {sin(0)
2

+ sin(20 t)}

Introduction

Objectives

Implementation of Costas Loop

Outline
1

Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs

Objectives

Implementation of Costas Loop

Clock
Costas Loop Components
Results

Summary

Introduction

Objectives

Implementation of Costas Loop

Clock Extraction

Provide a clock reference in sync with data.

Different methods
Open loop synchronizers
Closed loop (feedback) synchronizers

Summary

Introduction

Objectives

Implementation of Costas Loop

Outline
1

Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs

Objectives

Implementation of Costas Loop

Clock
Costas Loop Components
Results

Summary

Introduction

Objectives

Implementation of Costas Loop

FPGAs
Flexible digital circuits
Comprised of logic blocks and routing channels
Actel FPGAs: Use fuses instead of SRAM to avoid EM
interference
Programmed using VHDL/Verilog and synthesis tools

Figure: Structure of Actel FPGAs

Summary

Introduction

Objectives

Implementation of Costas Loop

Summary

Objectives

Primary Objective
To implement supressed carrier BPSK demodulation using a Type
II Costas Loop on a Microsemi Actel FPGA (Field Programmable
Array) for 8-16KHz carrier signal and data rate of 2-4 kbps.

Introduction

Objectives

Implementation of Costas Loop

Summary

Objectives
Secondary Objectives
The secondary outcomes are the following features in the Costas
Loop:
Subcarrier lock: To indicate subcarrier lock has been achieved
Clock and bit sync lock: A clock in sync with the demod data
of 50 % duty cycle, and a bit sync lock indication to indicate
synchronization between your data and clock outputs (The
clock should be such that after initial sync, even if continuous
0s or 1s are given for 40 bits and then alternate 0 and 1s are
restored, the clock should not loose sync.)
Infinite Impulse Response filter implementation (aside from
use of FIR filters)

Introduction

Objectives

Implementation of Costas Loop

Outline
1

Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs

Objectives

Implementation of Costas Loop

Clock
Costas Loop Components
Results

Summary

Introduction

Objectives

Implementation of Costas Loop

Summary

Clock

Clock Speed is variable in the requirements.

Therefore, minimum clock speed depends on the highest frequency
being used in the loop (64KHz) into 2.
Minimum clock speed: 128KHz.
We are using 256KHz.

Introduction

Objectives

Implementation of Costas Loop

Outline
1

Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs

Objectives

Implementation of Costas Loop

Clock
Costas Loop Components
Results

Summary

Introduction

Objectives

Implementation of Costas Loop

Costas Loop Components

NCO (Digital equivalent of VCO)

Multiplier
Arm filters (Can be FIR, IIR)
Loop filter design (IIR)

Summary

Introduction

Objectives

Implementation of Costas Loop

NCO

Implementation: N=6, M=8, P=5

Summary

Introduction

Objectives

Implementation of Costas Loop

NCO VHDL Testbench Simulation

Summary

Introduction

Objectives

Implementation of Costas Loop

Summary

Arm Filters
Low pass filters to remove the component of 20 .
Implemented using 10th Order Least Squares Method Optimization
FIR
order = 10;
Fpass = 6000;
Fstop = 8000;
Wpass = 1;
Wstop = 0.05;
arm coeffs = firls(order, [0 Fpass Fstop f sampling/2]/
(f sampling/2), [1 1 0 0], [Wpass Wstop]);
Coefficients are Q1.17 fixed point.

Introduction

Objectives

Implementation of Costas Loop

Summary

Arm Filters
Used MATLABs filter design toolbox to visualize filters and
created a class for simulating FIR filter fixed point implementation.

Introduction

Objectives

Implementation of Costas Loop

Summary

Linearized model of a PLL/Costas Loop

(t)

Loop Filter

VCO

F (s)

1
s

Transfer function
F (s)
s
(s)
F (s)
H(s) =
=
(s)
s + F (s)
G (s) =

(t)

Introduction

Objectives

Implementation of Costas Loop

Summary

Transfer function type

Type of transfer function: Important parameter in describing

PLL
From Control Theory: Number of poles at zero (integrators)
in a unit negative feedbacks transfer function (G (s)).
Type II can acquire (zero steady state error) unit step and
unit ramp response, can track (finite steady state error) unit
acceleration functions.
In terms of phase, it means it can exactly replicate carriers
phase and frequency but can only track steady change in
frequency in the carrier (due to Doppler effects).

Introduction

Objectives

Implementation of Costas Loop

PI Loop Filter

Loop filter: Proportional + Integral Controller

s
s +
= G (s) =
s2
F (s) = +

Two poles at zero = Type 2 system

Converted to z-domain using bilinear transform
s=
where T is sampling time.

2 1 z 1
T 1 + z 1

Summary

Introduction

Objectives

Implementation of Costas Loop

Outline
1

Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs

Objectives

Implementation of Costas Loop

Clock
Costas Loop Components
Results

Summary

Introduction

Objectives

MATLAB Simulation

Implementation of Costas Loop

Summary

Introduction

Objectives

Implementation of Costas Loop

Summary

Summary

Accomplished: Costas Loop Pre-Synthesis Simulation finished

Next TODO
Subcarrier Lock Indication
Clock Extraction