Structures and Unions

UNPACKED STRUCTURES :
A structure in C++ is simply a composite data type consisting of a number of elements of other
types.
typedef struct {
bit [7:0] opcode;
bit [23:0] addr;
} instruction; // named structure type
instruction IR; // define variable
PACKED STRUCTURES:
A packed structure is a mechanism for subdividing a vector into subfields that can be
conveniently accessed as members. Consequently, a packed structure consists of bit fields, which
are packed together in memory without gaps.
struct packed signed {
int a;
shortint b;
byte c;
bit [7:0] d; } pack1
UNIONS:
UnPacked Union:
Unlike structures, the components of a union all refer to the same location in memory. In this
way, a union can be used at various times to hold different types of objects, without the need to
create a separate object for each new type.
typedef union { // default unsigned
s_atmcell acell;
bit [423:0] bit_slice;
bit [52:0][7:0] byte_slice;
} u_atmcell
Packed Union:
A packed union shall contain members that must be packed structures, or packed arrays or
integer data types all of the same size .
typedef union packed { // default unsigned
s_atmcell acell;
bit [423:0] bit_slice;
bit [52:0][7:0] byte_slice;
} u_atmcell;
http://www.systemverilog.in/structures-unions.php
STRUCTURES AND UNIOUNS
Structure:
The disadvantage of arrays is that all the elements stored in then are to be of the
same data type. If we need to use a collection of different data types, it is not
possible using an array. When we require using a collection of different data items of
different data types we can use a structure. Structure is a method of packing data of
different types. A structure is a convenient method of handling a group of related
data items of different data types.

struct {
int a;
byte b;
bit [7:0] c;
} my_data_struct;
The keyword "struct" declares a structure to holds the details of four fields namely
a,b and c. These are members of the structures. Each member may belong to
different or same data type. The structured variables can be accessed using the
variable name "my_data_struct".
my_data_struct.a = 123;
$display(" a value is %d ",my_data_struct.a);
Assignments To Struct Members:
A structure literal must have a type, which may be either explicitly indicated with a
prefix or implicitly indicated by an assignment-like context.
my_data_struct = `{1234,8'b10,8'h20};
Structure literals can also use member name and value, or data type and default
value.
my_data_struct = `{a:1234,default:8'h20};
Union
Unions like structure contain members whose individual data types may differ from
one another. However the members that compose a union all share the same
storage area. A union allows us to treat the same space in memory as a number of
different variables. That is a Union offers a way for a section of memory to be
treated as a variable of one type on one occasion and as a different variable of a
different type on another occasion.
union {
int a;
byte b;
bit [7:0] c;
} my_data;
memory allocation for the above defined struct "my_data_struct".

Memory allocation for the above defined union "my_data_union".

Packed Structures:
In verilog , it is not convenient for subdividing a vector into subfield. Accessing
subfield requires the index ranges.
For example
reg [0:47] my_data;
`define a_indx 16:47
`define b_indx 8:15
`define c_indx 0:7
my_data[`b_indx] = 8'b10; // writing to subfield b
$display(" %d ",my_data[`a_indx]); // reading subfield a
A packed structure is a mechanism for subdividing a vector into subfields that can
be conveniently accessed as members. Consequently, a packed structure consists
of bit fields, which are packed together in memory without gaps. A packed struct or
union type must be declared explicitly using keyword "packed".
struct packed {
integer a;
byte b;
bit [0:7] c;
} my_data;
my_data.b = 8'b10;
$display("%d", my_data.a);
Memory allocation for the above defined packed struct "my_data".

One or more bits of a packed structure can be selected as if it were a packed array,
assuming an [n-1:0] numbering:
My_data [15:8] // b
If all members of packed structure are 2-state, the structure as a whole is treated as
a 2-state vector.
If all members of packed structure is 4-state, the structure as a whole is treated as a
4-state vector.
If there are also 2-state members, there is an implicit conversion from 4-state to 2state when reading those members, and from 2-state to 4-state when writing them.

What Is Dpi-C ?
From long time , Users have needes a simple way of communication to foreign
languages from verilog. VPI and PLI are not easy interfaces to Use . Users need
detailed knowledge of PLI and VPI even for a simple program. Most of the time,
users do not need the sophisticated capabilities of VPI and PLI. DPI also permits
C/C++ code to wait for Verilog events and C/C++ tasks and functions can be
disabledfrom SystemVerilog.
SystemVerilog introduces a new foreign language interface called the Direct
Programming Interface (DPI). The DPI provides a very simple, straightforward, and
efficient way to connect SystemVerilog and foreign language code unlike PLI or VPI.
DPI developed based on the donations from Synopsys "DirectC interface".
DPI consists of two separate layers: the SystemVerilog layer and a foreign language
layer. Both sides of DPI-C are fully isolated. Which programming language is actually
used as the foreign language is transparent and irrelevant for the System-Verilog
side of this interface. Neither the SystemVerilog compiler nor the foreign language
compiler is required to analyze the source code in the others language. Different
programming languages can be used and supported with the same intact
SystemVerilog layer.
DPI-C follows the principle of a black box: the specification and the implementation
of a component are clearly separated, and the actual implementation is transparent
to the rest of the system. Therefore, the actual programming language of the
implementation is also transparent, although this standard defines only C linkage
semantics. The separation between SystemVerilog code and the foreign language is
based on using functions as the natural encapsulation unit in SystemVerilog.
LAYERS
Two Layers Of Dpi-C
DPI-C consists of two separate layers: the SystemVerilog layer and a foreign
language layer. The SystemVerilog layer does not depend on which programming
language is actually used as the foreign language. Although different programming
languages can be supported and used with the intact SystemVerilog layer,
SystemVerilog defines a foreign language layer only for the C programming
language. Nevertheless, SystemVerilog code shall look identical and its semantics
shall be unchanged for any foreign language layer.
Dpi-C Systemverilog Layer
The SystemVerilog side of DPI-C does not depend on the foreign programming
language. In particular, the actual function call protocol and argument passing

mechanisms used in the foreign language are transparent and irrelevant to

SystemVerilog. SystemVerilog code shall look identical regardless of what code the
foreign side of the interface is using. The semantics of the SystemVerilog side of the
interface is independent from the foreign side of the interface.
The SystemVerilog DPI-C allows direct inter-language function calls between
SystemVerilog and any foreign programming language with a C function call
protocol and linking model:
Functions implemented in C and given import declarations in SystemVerilog can
be called from SystemVerilog; such functions are referred to as imported functions.
Functions implemented in SystemVerilog and specified in export declarations can
be called from C; such functions are referred to as exported functions.
Tasks implemented in SystemVerilog and specified in export declarations can be
called from C; such functions are referred to as exported tasks.
Functions implemented in C that can be called from SystemVerilog and can in turn
call exported tasks; such functions are referred to as imported tasks.
Dpi-C Foreign Language Layer
The foreign language layer of the interface (which is transparent to SystemVerilog)
shall specify how actual arguments are passed, how they can be accessed from the
foreign code, how SystemVerilog-specific data types (such as logic and packed) are
represented, and how they are translated to and from some predefined C-like types.
IMPORT
Import Methods
Methods implemented in C and given import declarations in SystemVerilog can be
called from SystemVerilog, such methods are referred to as imported
methods.Imported tasks or functions are similar to SystemVerilog tasks or functions.
Imported tasks or functions can have zero or more formal input, output, and inout
arguments.
Imported tasks always return an int result as part of the DPI-C disable protocol and,
thus, are declared in foreign code as int functions. We will discusses about the DPI-C
disable protocol in following sections.
Imported functions can return a result or be defined as void functions.
The syntax import method:
import {"DPI" | "DPI-C"} [context | pure] [c_identifier =] [function|task]
[function_identifier|task_identifier] ([tf_port_list]);
Steps To Write Import Metyhods
In SV Code
Step1 : Import the C function
import "DPI-C" string_sv2c=task string_sv2c();
Step2 : Invoke the Importted C function
initial
begin

string_sv2c();
end
In C code:
Step3: Define the Imported function
void string_sv2c(){
printf(" C: Hellow from C ");
}
Full Example:
CODE: SV_file
program main;
string str;
import "DPI-C" string_sv2c=task string_sv2c();
initial
begin
string_sv2c();
end
endprogram
CODE: C_file
#include "svdpi.h"
void string_sv2c(){
printf(" C: Hellow from C ");
}
RESULTS
C: Hellow from C
EXAMPLE: optional default arguments
Standard C Functions
Users can also call the standared C functions.
EXAMPLE:
import "DPI" function chandle malloc(int size);
import "DPI" function void free(chandle ptr);
EXPORT
Export Methods
Methods implemented in SystemVerilog and specified in export declarations can be
called from C, such methods are referred to as exported methods.
Steps To Write Export Methods
In SV Code :
Setp1: Export the systemverilog function
export "DPI-C" function export_func;
Step2: Define the systemverilog function
function void export_func();
$display("SV: Hello from SV ");

endfunction
In C code :
Step3: Export the Systemverilog function
extern void export_func(void);
Step4: Invoke the systemverilog function
void import_func()
{
export_func();
}
Full Example:
CODE: SV_file.sv
program main;
export "DPI-C" function export_func;
import "DPI-C" function void import_func();
function void export_func();
$display("SV: Hello from SV ");
endfunction
initial
begin
import_func();
end
endprogram
CODE: C_file.c
#include "stdio.h"
#include "vc_hdrs.h"
#include "svdpi.h"
extern void export_func(void);
void import_func()
{
export_func();
}
RESULTS:
SV: Hello from SV
Blocking Export Dpi Task
SV Dpi allows C to call a SystemVerilog method which consumes time.
CODE:SV_file.sv
program main;
export "DPI-C" task export_task;

import "DPI-C" context task import_task();

task export_task();
$display("SV: Entered the export function . wait for some time : %0d ",$time);
#100;
$display("SV: After waiting %0d",$time);
endtask
initial
begin
$display("SV: Before calling import function %0d",$time);
import_task();
$display("SV: After calling import function %0d",$time);
end
endprogram
CODE: C_file.c
extern void export_task();
void import_task()
{
printf(" C: Before calling export function\n");
export_task();
printf(" C: After calling export function\n");
}
RESULTS
SV: Before calling import function 0
C: Before calling export function
SV: Entered the export function . wait for some time : 0
SV: After waiting 100
C: After calling export function
SV: After calling import function 100