Escolar Documentos
Profissional Documentos
Cultura Documentos
Microprocessor &
Microcontroller
syllabus
BOOK References
Main Book:
1. Microprocessors and Interfacing, Programming and Hardware by
Doughlas V.Hall
Other Authors:
2. Microcomputer Systems: The 8086 / 8088 Family Architecture, Programming and Design by Yu-Cheng Liu, Glenn
A.Gibson
3. INTEL Microprocessors 8086/8088, 80186/80188, 80286, 80386,
80486, Pentium, Prentium ProProcessor, Pentium II, III, 4 by Barry B.
Bery
4. Advanced microprocessor and peripherals by A K RAY
LOCAL AUTHOR:
8086 Microprocessor by Nagoor Kani
Microprocessor Basics
Microprocessor (P) is the brain of a computer
that has been implemented on one
semiconductor chip.
The word comes from the combination micro and
processor.
Processor means a device that processes
whatever(binary numbers, 0s and 1s)
To process means to manipulate. It describes all
manipulation.
Micro - > extremely small
6
Definition of a Microprocessor.
The microprocessor is a
programmable device that takes in numbers,
performs on them arithmetic or logical
operations according to the program stored in
memory and then produces other numbers as
a result.
Microprocessor ?
A microprocessor is multi
programmable clock driven
register based semiconductor
device that is used to fetch ,
process & execute a data
within fraction of seconds.
8
Applications
Calculators
Accounting system
Games machine
Instrumentation
Traffic light Control
Multi user, multi-function environments
Military applications
Communication systems
9
MICROPROCESSOR HISTORY
10
Processor
Pinless
Processor
Slot
Processor
ProcessorSl
ot
11
8086 - 1979
286 - 1982
386 - 1985
486 - 1989
Pentium - 1993
Pentium Pro - 1995
Pentium MMX -1997
Pentium II - 1997
Pentium II Celeron - 1998
Pentium II Zeon - 1998
Pentium III - 1999
Pentium III Zeon - 1999
Pentium IV - 2000
Pentium IV Zeon - 2001
12
GENERATION OF PROCESSORS
Processor
Bits
Speed
8080
2 MHz
8086
16
4.5 10
MHz
8088
16
4.5 10
MHz
80286
16
10 20
MHz
80386
32
20 40
MHz
80486
32
40 133
MHz
13
GENERATION OF PROCESSORS
Processor
Bits
Speed
Pentium
32
60 233
MHz
Pentium
Pro
32
150 200
MHz
Pentium II,
Celeron ,
Xeon
32
233 450
MHz
Pentium
III, Celeron
, Xeon
32
450 MHz
1.4 GHz
Pentium IV,
Celeron ,
Xeon
32
1.3 GHz
3.8 GHz
Itanium
64
800 MHz
3.0 GHz
14
Intel 4004
Introduced in 1971.
It was the first microprocessor
by Intel.
It was a 4-bit P.
Its clock speed was 740KHz.
It had 2,300 transistors.
It could execute around
60,000 instructions per
second.
15
Intel 4040
Introduced in 1971.
It was also 4-bit P.
16
8-bit Microprocessors
17
Intel 8008
Introduced in 1972.
It was first 8-bit P.
Its clock speed was
500 KHz.
Could execute
50,000 instructions
per second.
18
Intel 8080
Introduced in 1974.
It was also 8-bit P.
Its clock speed was
2 MHz.
It had 6,000
transistors.
19
Intel 8085
Introduced in 1976.
It was also 8-bit P.
Its clock speed was 3 MHz.
Its data bus is 8-bit and
address bus is 16-bit.
It had 6,500 transistors.
Could execute 7,69,230
instructions per second.
It could access 64 KB of
memory.
It had 246 instructions.
20
16-bit Microprocessors
21
INTEL 8086
Introduced in 1978.
22
INTEL 8088
Introduced in 1979.
It was created as a
cheaper version of
Intels 8086.
It was a 16-bit processor
with an 8-bit external
bus.
23
Introduced in 1982.
24
INTEL 80286
Introduced in 1982.
It was 16-bit P.
It could address 16 MB
of memory.
It had 1,34,000
transistors.
25
32-BIT MICROPROCESSORS
26
INTEL 80386
Introduced in 1986.
27
INTEL 80486
Introduced in 1989.
INTEL PENTIUM
Introduced in 1993.
Introduced in 1995.
It had 21 million
transistors.
Cache memory:
8 KB for instructions.
8 KB for data.
30
INTEL PENTIUM II
Introduced in 1997.
31
Introduced in 1998.
32
Introduced in 1999.
33
INTEL PENTIUM IV
Introduced in 2000.
34
Introduced in 2006.
It is 32-bit or 64-bit P.
35
36
64-BIT MICROPROCESSORS
37
Intel Core 2
Intel Core i3
38
INTEL CORE I5
INTEL CORE I7
39
Basic Terms
Bit: A digit of the binary number { 0 or 1 }
Nibble: 4 bit
Byte: 8 bit word: 16 bit
Double word: 32 bit
Data: binary number/code operated by an
instruction
Address: Identification number for memory
locations
Clock: square wave used to synchronize various
devices in P
Memory Capacity = 2^n ,
n->no. of address lines
40
BUS CONCEPT
BUS: Group of conducting lines that carries data ,
address & control signals.
CLASSIFICATION OF BUSES:
1.DATA BUS: group of conducting lines that carries
data.
2. ADDRESS BUS: group of conducting lines that
carries address.
3.CONTROL BUS: group of conducting lines that
carries control signals {RD, WR etc}
CPU BUS: group of conducting lines that directly
connected to P
SYSTEM BUS: group of conducting lines that carries
data , address & control signals in a P system
41
TRISTATE LOGIC
42
Input
Devices
ArithmeticControl
Logic
Unit
ProcessingUnit
Data into
Information
Primary
Storage
Unit
Keyboard,
Mouse
etc
Output
Devices
Monitor
Printer
Disks, Tapes,
Optical Disks
43
UNIT
1
THE 8086 MICROPROCESSOR
44
UNIT 1 Syllabus
Introduction to 8086
Microprocessor architecture
Addressing modes
Instruction set
Assembler directives
Assembly language programming
Modular Programming
1.Linking and Relocation
2.Stacks , Procedures , Macros
Interrupts and interrupt service routines
Byte & String Manipulation.
45
8086 Microprocessor-introduction
INTEL launched 8086 in 1978
8086 is a 16-bit microprocessor with
16-bit Data Bus {D0-D15}
20-bit Address Bus {A0-A19} [can access upto
2^20= 1 MB memory locations] .
8086 Microprocessor
It provides 14, 16-bit registers.
8086 requires one phase clock with a 33%
duty cycle to provide optimized internal
timing.
Range of clock:
5 MHz for 8086
8Mhz for 8086-2
10Mhz for 8086-1
47
CPU functions
1. Fetch
2. Decode
3. Execute
8086 CPU
Bus Interface
Unit (BIU)
Execution Unit
(EU)
48
49
Execution Unit
Tells BIU (addresses) where to fetch
instructions or data
Decodes & Executes instructions
Dividing the work between BIU & EU
speeds up processing
50
51
Memory
Interface
BIU
Instruction Queue
Instruction
Decoder
AH
AL
BH
BL
CH
CL
DH
DL
ARITHMETIC
LOGIC UNIT
CONTROL
SYSTEM
OPERANDS
FLAGS
EU
52
Execution Unit
Main components are
Instruction Decoder
Control System
Arithmetic Logic Unit
General Purpose Registers
Flag Register
Pointer & Index registers
53
Instruction Decoder
Translates instructions fetched from memory
into a series of actions which EU carries out
Control System
Generates timing and control signals to
perform the internal operations of the
microprocessor
AH
AL
BH
BL
CH
CL
DH
DL
AH
AL
AX
BH
BL
BX
CH
CL
CX
DH
DL
DX
55
Flag Register
8086 has a 16-bit flag register
Contains 9 active flags
There are two types of flags in 8086
Conditional flags six flags, set or reset
by EU on the basis of results of some
arithmetic operations
Control flags three flags, used to control
certain operations of the processor
56
Flag Register
U U U U OF DF IF TF SF ZF U AF U PF U CF
1.
CF
CARRY FLAG
2.
PF
PARITY FLAG
3.
AF
AUXILIARY CARRY
4.
ZF
ZERO FLAG
5.
SF
SIGN FLAG
6.
OF
OVERFLOW FLAG
7.
TF
TRAP FLAG
8.
IF
INTERRUPT FLAG
9.
DF
DIRECTION FLAG
Conditional Flags
(Compatible with 8085,
except OF)
Control Flags
57
Flag Register
Auxiliary Carry Flag
Carry Flag
Sign Flag
Zero Flag
Parity Flag
15
14
13
12
11
10
OF
DF
IF
TF
SF
ZF
Direction Flag
4
AF
2
PF
0
CF
Tarp Flag
If this flag is set, the processor
enters the single step execution
mode by generating internal
interrupts after the execution of
each instruction
Interrupt Flag
Causes the 8086 to recognize
external mask interrupts; clearing IF
disables these interrupts.
58
Registers, Flag
8086 registers
categorized
into 4 groups
Sl.No.
1
Type
General purpose
register
15
14
13
12
11
10
OF
DF
IF
TF
SF
ZF
Register width
4
AF
PF
CF
Name of register
16 bit
8 bit
Pointer register
16 bit
SP, BP
Index register
16 bit
SI, DI
Instruction Pointer
16 bit
IP
Segment register
16 bit
Flag (PSW)
16 bit
Flag register
59
Special Function
AX
16-bit Accumulator
AL
8-bit Accumulator
BX
Base register
CX
Count Register
DX
Data Register
SP
Stack Pointer
BP
Base Pointer
SI
Source Index
DI
Data Index
60
61
Instruction Queue
8086 employs parallel processing
When EU is busy decoding or executing
current instruction, the buses of 8086 may
not be in use.
At that time, BIU can use buses to fetch upto
six instruction bytes for the following
instructions
BIU stores these pre-fetched bytes in a FIFO
register called Instruction Queue
When EU is ready for its next instruction, it
simply reads the instruction from the queue
in BIU
62
Pipelining
EU of 8086 does not have to wait in
between for BIU to fetch next
instruction byte from memory
So the presence of a queue in 8086
speeds up the processing
Fetching the next instruction while the
current instruction executes is called
pipelining
63
Memory Segmentation
8086 has a 20-bit address bus
So it can address a maximum of 1MB of
memory
8086 can work with only four 64KB segments
at a time within this 1MB range
These four memory segments are called
Code segment
Stack segment
Data segment
Extra segment
64
Memory
64KB Memory
Segment
00000H
2
3
4
4
5
6
7
8
9
10
1MB
Address
Range
11
12
13
14
15
16
FFFFFH
65
Code Segment
That part of memory from where BIU is
currently fetching instruction code bytes
Stack Segment
A section of memory set aside to store
addresses and data while a subprogram
executes
Memory
Code Segment
00000H
2
3
4
5
6
7
8
9
10
1MB
Address
Range
11
12
13
14
15
Stack Segment
16
FFFFFH
67
Segment Registers
hold the upper 16-bits of the starting
address for each of the segments
The four segment registers are
68
Memory
1
CS
1000 0H
00000H
Code Segment
3
4
DS
ES
4000 0H
5000 0H
Data Segment
Extra Segment
Starting Addresses
of Segments
7
8
9
10
1MB
Address
Range
11
12
13
14
15
SS
F000 0H
Stack Segment
FFFFFH
69
71
348A0H
00000H
Data
Segment
IP = 4214H
Code Byte
Memory
38AB4H
MOV AL, BL
Code
Segment
Extra
Segment
7
8
9
CS
IP
Physical Address
348A0 H
+ 4214 H
38AB4 H
1MB
Address
Range
10
11
12
13
14
15
Stack
Segment
72
FFFFFH
74
ADDRESSING
MODES OF
8086
75
76
AL=ABH, AH=10H
77
78
[SI+3]
81
82
83
[BX+SI+6] ; AH
JMP [BX+DI+6] ;
IP
[BX+SI+7]
[BX+DI+7 : BX+DI+6]
84
[ES:DI]
SI+1
SI-1
[DS:SI]
, DI
, DI
DI+1
DI-1
85
INSTRUCTION
SET of 8086
86
88
89
BEFORE
EXECUTION
AX
AFTER
EXECUTION
MOV BX,AX
2000H
BEFORE
EXECUTION
A
H
AL
B
H
BL
C
H
CL
D
H
DL
2000H
AFTER
EXECUTION
MOV CL,M
40
BX
A
H
AL
B
H
BL
C
H
CL 40
D
H
DL
40
91
Stack Pointer
92
E.g.:
(1). PUSH AX;
(2). PUSH DS;
(3). PUSH [5000H];
93
INITIAL POSITION
(1) STACK
POINTER
DECREMENTS SP & STORES HIGHER
BYTE
(2) STACK POINTER
HIGHER BYTE
LOWER BYTE
HIGHER BYTE
94
BEFORE EXECUTION
SP
2002H
BH
BL
CH
10
DH
CL
50
DL
2000H
2001H
2002H
PUSH CX
AFTER EXECUTION
SP
2000H
BH
CH
DH
BL
10
CL
DL
2000H
50
2001H
10
50
2002H
95
E.g.
(1). POP AX;
(2). POP DS;
(3). POP [5000H];
96
(1) STACK
POINTER
LOWER BYTE
HIGHER BYTE
INCREMENTS SP
LOWER BYTE
HIGHER BYTE
(3) STACK
POINTER
97
BEFORE EXECUTION
SP 2000H
BH
BL
2000H 30
2001H 50
2002H
POP BX
AFTER EXECUTION
SP 2002H
2000H 30
2001H 50
BH 5
2002H
BL 30
98
BEFORE EXECUTION
AFTER EXECUTION
AH 20 AL 40
AH 70
AL 80
BH 70 BL 80
BH 20
BL 40
XCHG AX,BX
100
101
BEFORE EXECUTION
PORT
80H
10
AL
IN AL,80H
AFTER EXECUTION
PORT
80H
10
AL 10
102
103
BEFORE EXECUTION
PORT
50H
10
AL 40
OUT 50H,AL
AFTER EXECUTION
PORT
50H
40
AL 40
104
(7) XLAT
105
E.g.
(1). LEA BX,Address;
(2). LEA SI,Address[BX];
106
E.g.
(1). LDS BX,5000H;
(2). LES BX,5000H;
107
BX 20
10
7
0
10
5000H
20
DS/ES 40
30
5001H
30
5002H
40
5003H
108
Addition,
Subtraction,
Increment,
Decrement.
111
AFTER EXECUTION
BEFORE EXECUTION
AH
10
AL
10
ADD AX,2020H
AH 30
AL 30
1010
+2020
3030
BEFORE EXECUTION
AFTER EXECUTION
AH 10
AL 10
AH 30
AL 30
BH 20
BL
BH 20
BL 20
20
ADD AX,BX
113
BEFORE EXECUTION
AH 10
AL 11
INC AX
BEFORE EXECUTION
5000H
1011
AFTER EXECUTION
AH 10
AL 12
AFTER EXECUTION
INC [5000H]
5000H
1012
116
4. DEC source
This instruction decreases the contents of
source operand by 1.
The source may be memory location or register.
The source can not be immediate data.
The result is stored in the same place.
BEFORE EXECUTION
AH 10
AL 11
DEC AX
BEFORE EXECUTION
5000H
1051
AFTER EXECUTION
AH 10
AL 10
AFTER EXECUTION
DEC [5000H]
5000H
1050
118
119
BEFORE EXECUTION
AH 20
AL 00
AFTER EXECUTION
SUB AX,1000H
AH 10
AL 00
2000
-1000
=1000
BEFORE EXECUTION
AH 20
BH 10
AL
BL
00
00
AFTER EXECUTION
SUB AX,BX
AH 10
AL
00
BH 10
BL
00
120
BEFORE EXECUTION
B 1
AFTER EXECUTION
SBB AX,1000H
AH 10 AL 19
AH 20 AL 20
BEFORE EXECUTION
2020
- 1000
10201=1019
AFTER EXECUTION
B 1
AH
20
AL
20
BH
10
BL
10
SBB AX,BX
AH 10
AL 19
BH 10
BL
10
2050
122
BEFORE EXECUTION
AH
10
AL
00
BH
10
BL
00
D=S: CY=0,Z=1
D>S: CY=0,Z=0
D<S: CY=1,Z=0
CMP AX,BX
BEFORE EXECUTION
AH
10
AL
00
BH
00
BL
10
CMP AX,BX
BEFORE EXECUTION
AH
10
AL
00
BH
20
BL
00
CMP AX,BX
AFTER EXECUTION
CY
AFTER EXECUTION
CY
AFTER EXECUTION
CY
1 Z
124
MUL operand
Unsigned Multiplication.
Operand contents are positively signed.
Operand may be general purpose register or memory
location.
If operand is of 8-bit then multiply it with contents of AL.
If operand is of 16-bit then multiply it with contents of AX.
Result is stored in accumulator (AX).
(2). MUL CX
127
IMUL operand
Signed Multiplication.
Operand contents are negatively signed.
Operand may be general purpose register, memory location
or index register.
If operand is of 8-bit then multiply it with contents of AL.
If operand is of 16-bit then multiply it with contents of AX.
Result is stored in accumulator (AX).
(2). IMUL CX
// AX= AL*BH;
// AX=AX*CX;
128
DIV operand
Unsigned Division.
Operand may be register or memory.
Operand contents are positively signed.
Operand may be general purpose register or
memory location.
AL=AX/Operand (8-bit/16-bit) & AH=Remainder.
MOV BL, 04
IDIV BL
// BL=04
// AL=0203/04=50 (i.e. AL=50 & AH=03)
129
IDIV operand
Signed Division.
Operand may be register or memory.
Operand contents are negatively signed.
Operand may be general purpose register or
memory location.
AL=AX/Operand (8-bit/16-bit) & AH=Remainder.
MOV BL, 04
DIV BL
AH=03)
// AX=-0203
// BL=04
// AL=-0203/04=-50 (i.e. AL=-50 &
130
131
BEFORE EXECUTION
AH
00
AL
05
BH
CH
00
BL
CL
03
MUL BX
AFTER EXECUTION
AH
BH
CH
DH
00
AL
0F
00
BL
CL
DL
00
132
BEFORE EXECUTION
AH 00
AL
0F
BH
BL
02
CH
00
CL
AX=Quotient {0007}
DX=Reminder {0001}
DIV BX
AFTER EXECUTION
AH
BH
CH
DH
000F
=7 1
0002
00
AL
07
00
BL
CL
DL
01
133
134
135
136
137
OR
Used in setting certain bits
138
XOR
Used in Inverting bits
xxxx xxxx XOR 0000 1111 = xxxxxxxx
-Example:
Clear bits 0 and 1, set bits 6 and 7, invert
bit 5 of register CL:
AND CL, FCH ;
OR CL, C0H ;
XOR CL, 20H ;
139
1111 1100 B
1100 0000B
0010 0000B
BEFORE EXECUTION
AH FF
AL FF
BH 11
BL
11
AFTER EXECUTION
AND AX,BXH
AH 11
AL 11
BH 11
BL 11
140
BEFORE EXECUTION
AH FF
AL FF
BH 11
BL
11
AFTER EXECUTION
OR AX,BXH
AH FF
AL FF
BH 11
BL 11
141
BEFORE EXECUTION
AH FF
AL FF
BH 11
BL
11
AFTER EXECUTION
XOR AX,BXH
AH EE
AL EE
BH 11
BL 11
142
AFTER EXECUTION
BEFORE EXECUTION
AH FF
AL FF
NOT AXH
AH 00
AL 00
143
SHL Instruction
The SHL (shift left) instruction performs a logical left shift
0
CF
mov dl,5d
shl dl,1
144
SHR Instruction
The SHR (shift right) instruction performs a logical right shift
MOV DL,80d
SHR DL,1
SHR DL,2
145
; DL = 40
; DL = 10
SAR Instruction
SAR (shift arithmetic right) performs a right
CF
; DL = -40
; DL = -10
For example, 80 / 23 = 10
mov dl,5
shl dl,1
147
Before:
00000101
=5
After:
00001010
= 10
ROL Instruction
ROL (rotate) shifts each bit to the left
The highest bit is copied into both the Carry flag
CF
148
MOV Al,11110000b
ROL Al,1
; AL = 11100001b
MOV Dl,3Fh
ROL Dl,4
; DL = F3h
ROR Instruction
ROR (rotate right) shifts each bit to the right
The lowest bit is copied into both the Carry flag and
CF
149
MOV AL,11110000b
ROR AL,1
; AL = 01111000b
MOV DL,3Fh
ROR DL,4
; DL = F3h
RCL Instruction
RCL (rotate carry left) shifts each bit to the left
Copies the Carry flag to the least significant bit
Copies the most significant bit to the Carry flag
CF
CLC
MOV BL,88H
RCL BL,1
RCL BL,1
150
;
;
;
;
CF = 0
CF,BL = 0 10001000b
CF,BL = 1 00010000b
CF,BL = 0 00100001b
RCR Instruction
RCR (rotate carry right) shifts each bit to the right
Copies the Carry flag to the most significant bit
Copies the least significant bit to the Carry flag
CF
STC
MOV AH,10H
RCR AH,1
151
; CF = 1
; CF,AH = 00010000 1
; CF,AH = 10001000 0
SHL Instruction
BEFORE
0
EXECUTION
CF
AFTER 0
EXECUTION
=05H
=0AH
152
SHR Instruction
0
CF
BEFORE
0
EXECUTION
1 =05H
AFTER
0
EXECUTION
CF
=02H
153
ROL Instruction
CF
BEFORE
EXECUTION 0
=05H
CF
0
AFTER 0
EXECUTION
=0AH
154
ROR Instruction
CF
BEFORE
EXECUTION
=05H
CF
1
AFTER
EXECUTION
=82H
155
of instruction.
unconditional.
156
CALL Des:
This instruction is used to call a subroutine or function or
procedure.
RET:
It returns the control from procedure to calling program.
Every CALL instruction should have a RET.
157
Call subroutine A
Next instruction
158
Return
JMP Des:
This instruction is used for unconditional jump from one place to
another.
159
160
Meaning
JA
Jump if Above
JAE
JB
Jump if Below
JBE
JC
Jump if Carry
JE
Jump if Equal
JNC
JNE
JNZ
JPE
JPO
JZ
Jump if Zero
Loop Des:
This is a looping instruction.
The number of times looping is required is placed in the CX
register.
161
String Instructions
String in assembly language is just a sequentially stored bytes or
words.
considerably reduced.
162
SCAS String:
It scans a string.
It compares the String with byte in AL or with word in
AX.
163
SI and DI store the offset values for source and destination index.
164
L1
MOV CX,0003
MOV SI,1000
MOV DI,2000
CLD
MOV SB
DEC CX
JNZ L1
HLT
decrement CX
165
166
REP (Repeat):
This is an instruction prefix.
It causes the repetition of the instruction until CX becomes zero.
E.g.: REP MOVSB STR1, STR2
It copies byte by byte contents.
REP repeats the operation MOVSB until CX becomes zero.
167
attached.
168
STC
It sets the carry flag to 1.
CLC
It clears the carry flag to 0.
CMC
It complements the carry flag.
169
STD:
It sets the direction flag to 1.
If it is set, string bytes are accessed from higher memory address to
CLD:
It clears the direction flag to 0.
If it is reset, the string bytes are accessed from lower memory
170
The HLT instruction will cause the 8086 to stop fetching and
executing instructions.
NOP instruction
LOCK instruction
WAIT instruction
this instruction takes 8086 to an idle condition. The CPU
will not do any processing during this.
171
INSTRUCTION SET-summary
1.DATA TRANSFER INSTRUCTIONS
Mnemonic
Meaning
Format
Operation
Move
Mov D,S
(S) (D)
Exchange
XCHG D,S
(S)
LEA Reg16,EA
EA
PUSH BX
POP
POP BX
IN
IN AL,28
OUT
OUT 28,AL
MOV
XCHG
LEA
PUSH
(D)
(Reg16)
sp=sp-2
Copy 16 bit value to top
of stack
Copy top of stack to 16
bit reg
sp=sp+2
172
2. ARITHMETIC INSTRUCTIONS
Mnemonic
SUB
Meaning
Subtract
Format
SUB D,S
Operation
(D) - (S)
Borrow
(D)
(CF)
(D)
SBB
Subtract with
borrow
SBB D,S
DEC
Decrement by one
DEC D
NEG
Negate
NEG D
DAS
DAS
AAS
AAS
ADD
Addition
ADD D,S
(S)+(D)
ADC
ADC D,S
(S)+(D)+(CF)
INC
Increment by one
INC D
(D)+1 (D)
AAA
AAA
DAA
DAA
(D) - 1
(D)
(D)
(D)
carry (CF)
carry (CF)
is incremented by 1
Adjust AL for decimal Packed BCD
173
Meaning
Format
Operation
AND
Logical AND
AND D,S
OR
Logical Inclusive OR
OR D,S
(S)+(D) (D)
XOR
Logical Exclusive OR
XOR D,S
(S) + (D)(D)
NOT
LOGICAL NOT
NOT D
(D) (D)
174
Meaning
Format
SAL/SHL D, Count
SHR
SHR D, Count
SAR
Shift arithmetic
right
SAR D, Count
Mnemonic
Meaning
Format
ROL
ROR
Rotate Left
ROL D,Count
Rotate Right
ROR D,Count
RCL
RCL D,Count
RCR
RCR D,Count
175
4. Branching or PROGRAM
EXECUTION TRANSFER INSTRUCTIONS
CALL - call a subroutine
RET - returns the control from procedure to calling
program
176
5. STRING INSTRUCTIONS
CMPS Des, Src - compares the string bytes
SCAS String - scans a string
MOVS / MOVSB / MOVSW - moving of byte or
word
REP (Repeat) - repetition of the instruction
177
Assembler
Directives
ASSUME,END,ENDP,EQU,EVEN,DD 8 mark
179
Directives Expansion
180
181
184
Directives examples
185
Assembly Language
Programming(ALP)
8086
186
187
194
Detailed coding
16 BIT ADDITION
195
Detailed coding
16 BIT SUBTRACTION
196
16 BIT MULTIPLICATION
197
16 BIT DIVISION
198
SUM of N numbers
L1:
MOV AX,0000
MOV SI,1100
MOV DI,1200
MOV CX,0005
MOV DX,0000
ADD AX,[SI]
INC SI
INC DX
CMP CX,DX
JNZ L1
MOV [1200],AX
HLT
199
Average of N numbers
L1:
MOV AX,0000
MOV SI,1100
MOV DI,1200
MOV CX,0005
MOV DX,0000
ADD AX,[SI]
INC SI
INC DX
CMP CX,DX
JNZ L1
DIV CX
MOV [1200],AX
HLT
AX=AX/5(AVERAGE OF 5 NUMBERS)
200Erode
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech,
FACTORIAL of N
L1:
ASCENDING ORDER
202
203
DECENDING ORDER
JNB L1 into JB L1
in the LINE 10
204
205
LARGEST NUMBER
206
SMALLEST NUMBER
207
Modular
Programming
208
CHARACTERISTICS of module:
1. Each module is independent of other modules.
2. Each module has one input and one output.
3. A module is small in size.
4. Programming a single function per module is a goal
Advantages of Modular Programming:
It is easy to write, test and debug a module.
Code can be reused.
The programmer can divide tasks.
Re-usable Modules can be re-used within a program
DRAWBACKS:
Modular programming requires extra time and memory
210
MODULAR PROGRAMMING:
1.LINKING & RELOCATION
2.STACKS
3.Procedures
4.Interrupts & Interrupt Routines
5.Macros
211
LINKING &
RELOCATION
212
LINKER
A linker is a program used to join together several
object files into one large object file.
The linker produces a link file which contains the
binary codes for all the combined modules.
The linker program is invoked using the following
options.
C> LINK
or
C>LINK MS.OBJ
213
214
215
Loader
216
Procedures
CALL & RET instruction
219
220
m1 PROC
MOV BX, 5
RET ;
return to caller.
m1 ENDP
END
The above example calls procedure m1, does MOV BX, 5 &
returns to the next instruction after CALL: MOV AX, 2.
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
221
ORG 100h
MOV AL, 1
MOV BL, 2
CALL m2
CALL m2
CALL m2
CALL m2
RET
m2 PROC
MUL BL
RET
m2 ENDP
END
; AX = AL * BL.
; return to caller.
value of AL register is update every time the
procedure is called.
final result in AX register is 16 (or 10h)
MACROS
How to pass parameters using macros-6/8 Mark
227
MACRO
PUSH AX
PUSH BX
PUSH CX
ENDM
RETREIVE
MACRO
POP CX
POP BX
POP AX
ENDM
RETREIVE
229
230
; macro named
COPY with
2 parameters{x, y}
231
INTERRUPTS
&
INTERRUPT SERVICE
ROUTINE(ISR)
232
233
234
235
236
238
239
240
241
242
1. TYPE 0 TO TYPE 4 INTERRUPTSThese are used for fixed operations and hence are called
dedicated interrupts
{AX/0=}
PRIORITY OF INTERRUPTS
Interrupt Type
SINGLE STEP
Priority
Highest
Lowest
245
Byte &
String
Manipulation
246
Move,
compare,
store,
load,
scan
247
Byte Manipulation
Example 1:
MOV AX,[1000]
MOV BX,[1002]
AND AX,BX
MOV [2000],AX
HLT
Example 2:
MOV AX,[1000]
MOV BX,[1002]
OR AX,BX
MOV [2000],AX
HLT
Example 3:
MOV AX,[1000]
MOV BX,[1002]
XOR AX,BX
MOV [2000],AX
HLT
Example 4:
MOV AX,[1000]
NOT AX
MOV [2000],AX
HLT
248
STRING MANIPULATION
1. Copying a string (MOV SB)
L1
MOV CX,0003
MOV SI,1000
MOV DI,2000
CLD
MOV SB
DEC CX
JNZ L1
HLT
decrement CX
249
250
UNIT-2
8086 SYSTEM BUS
STRUCTURE
DEPARTMENTS: CSE,IT {semester 04}
ECE {semester 05}
Regulation : 2013
Presented by
C.GOKUL,AP/EEE
UNIT 2 Syllabus
252
8086 signals or
Pin Diagram
253
254
Power Supply
5V 10%
Ground
Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
Clock
If high for
minimum 4
clks
Address/Data Bus:
Contains address
bits A15-A0 when ALE
is 1 & data bits D15
D0 when ALE is 0.
256
INTERRUPT
Non - maskable
interrupt
Interrupt
acknowledge
Interrupt request
257
Direct
Memory
Access
Hold
Hold
acknowledge
258
Address/Status Bus
Address bits A19
A16 & Status bits S6
S3
259
BHE#, A0:
Enables most
significant data bits
D15 D8 during read
or write operation.
S7: Always 1.
1,1: No selection
260
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
261
Read Signal
Write Signal
Memory or I/0
Data
Transmit/Receive
Data Bus Enable
262
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access
101: read memory
110: write memory
111: none -passive
Status Signal
Inputs to 8288 to
generate eliminated
signals due to max
mode.
263
Lock Output
Used to lock peripherals
off the system
Activated by using the
LOCK: prefix on any
instruction
DMA
Request/Grant
Lock Output
264
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
Queue Status
Used by numeric
coprocessor (8087)
265
0V=0,
reference
for all
voltages
Time-multiplexed
Address / Data Bus
(bidirectional)
Hardware
interrupt
requests (inputs)
2...5MHz,
1/3 duty cycle
(input)
GND 1
40 Vcc
AD14
AD15
AD13
A16/S3
AD12
A17/S4
AD11
A18/S5
AD10
A19/S6
___
AD9
BHE/S7
___
AD8
MN/MX
___
AD7
INTEL
RD
AD6
8086
HOLD
AD5
HLDA
___
AD4
WR__
AD3
IO/M
__
AD2
DT/R
____
AD1
DEN
AD0
ALE
_____
NMI
INTA
_____
INTR
TEST
CLK
READY
GND 20
21 RESET
Minmode operation
signals (MN/MX=1)
5V10%
Maxmode operation
signals (MN/MX=0)
(HIGH)
Control
Bus
(in,out)
___ ____
(RQ/GT0)
___ ____
(RQ/GT1)
______
(LOCK)
__
(S2)
__
Status
(S1)
__
signals
(S0)
(outputs)
(QS0)
(QS1)
Interrupt
acknowledge
(output)
Timemultiplexed
Address Bus
/Status signals
(outputs)
Operation Mode,
(input):
1 = minmode
(8088 generates all
the needed control
signals for a small
system),
0 = maxmode
(8288 Bus
Controller expands
the status signals
to generate more
266
control signals)
Timing
Diagram
Basics
only for understanding
T-State
T1
T2
T3
T4
269
Signal Transition
occurs when the clock
signal is HIGH
Signal Transition
occurs when the clock
signal is LOW
Signal Transition
occurs from HIGH to
LOW on RISING EDGE
AD0-AD15
SYSTEM BUS
TIMING
276
277
278
Bus Timing
During T 1 :
The address is placed on the Address/Data bus.
Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the address
onto the address bus and set the direction of data transfer on data bus.
During T 2 :
8086 issues the RD or WR signal, DEN , and, for a write, the data.
DEN enables the memory or I/O device to receive the data for writes and the 8086 to
receive the data for reads.
During T 3 :
This cycle is provided to allow memory to access data.
READY is sampled at the end of T 2 .
If low, T 3 becomes a wait state.
Otherwise, the data bus is sampled at the end of T 3 .
During T 4 :
All bus signals are deactivated, in preparation for next bus cycle.
Data is sampled for reads, writes occur for writes.
279
Setup time The time before the rising edge of the clock, while the data
must be valid and constant
Hold time The time after the rising edge of the clock during which the data
must remain valid and constant
280
WAIT State
Tw
Clock
READY
Basic
configurations
282
Maximum mode(MN/MX=GND)
Pin #33 (MN/MX) connect to Ground
Some control signals are generated externally by the 8288
bus controller chip
Max mode is used when math processor is used.
283
1.Minimum
Mode
configuration
285
286
287
288
2.Maximum
Mode
configuration
NOTE: Explain Maximum mode signals also {refer pin diagram}
292
293
MAXIMUM MODE
294
295
296
MULTIPROCESSOR
CONFIGURATIONS
297
Coprocessor 8087
Multiprocessor
configuration
298
Multiprocessor configuration
Multiprocessor Systems refer to the use of multiple
processors that executes instructions simultaneously
and communicate with each other using mail boxes and
Semaphores.
Maximum mode of 8086 is designed to implement 3
basic multiprocessor configurations:
1. Coprocessor (8087)
2. Closely coupled (8089)
3. Loosely coupled (Multibus)
299
300
301
302
304
Closely Coupled
processor may take
control of the bus
independently.
Two 8086s cannot
be closely coupled.
305
307
Daisy Chaining:
Independent
Advantages of Multiprocessor
Configuration
INTRODUCTION
TO ADVANCED
PROCESSORS
314
Data bus
width
16
80286
16
24
16M
80386 DX
32
32
4G
80486
32
32
4G
Pentium 4 &
core 2
64
40
1T
315
80186
316
80286
317
80386
318
UNIT-3
I/O
INTERFACING
DEPARTMENTS: CSE,IT {semester 04}
ECE {semester 05}
Regulation : 2013
Presented by
C.GOKUL,AP/EEE
319
UNIT 3 Syllabus
Data Transfers
321
322
MEMORY DEVICES
I/O DEVICES
323
IO is treated as memory.
16-bit addressing.
More Decoder Hardware.
Can address 216=64k
locations.
Less memory is available.
IO Mapped IO
IO is treated IO.
8- bit addressing.
Less Decoder
Hardware.
Can address 28=256
locations.
Whole memory address
space is available.
324
325
Memory Mapped IO
IO Mapped IO
Special Instructions are
used like IN, OUT.
Special control signals
are used.
Arithmetic and logic
operations can not be
performed on data.
Data transfer b/w
accumulator and IO.
326
Parallel communication
interface
INTEL 8255
327
8255 PPI
328
Signals of 8085
329
8255 PIO/PPI
330
331
332
333
Control Logic
CS
A1
A0
Selected
0
0
0
0
0
0
1
1
0
1
0
1
Port A
Port B
Port C
Control
Register
8255 is not
selected
334
335
336
337
338
339
340
341
I/O Mode
1. BSR Mode
342
B3
B2
B1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit/pin of port C
selected
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
343
2. I/O MODE
Features
344
345
Features
346
347
348
Solution:
1
= AEH
349
Solution:
1
= 80H
350
Solution:
1
= 9BH
351
Parallel Transfer
TRANSMITTER
Receiver
352
Serial communication
interface
INTEL 8251 USART
353
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
354
355
BLOCK DIAGRAM
356
Five Sections
357
Input Signals
CS Chip Select
C/D Control/Data
358
359
WR Write
RD Read
RESET - Reset
CLK - Clock
360
CS C/D RD WR
0
Function
MPU writes instruction in the
control register
MPU reads status from the status
register
MPU outputs the data to the Data
Buffer
MPU accepts data from the Data
Buffer
USART is not Selected
361
Control Register
16-bit register
This register can be accessed an output port
when the C/D pin is high
Status Register
Checks ready status of a peripheral
Data Buffer
Transmitter Section
Buffer Register
Output Register
362
363
Receiver Section
Input Register
Buffer Register
364
365
366
Control words
367
368
369
370
371
372
373
11374
Programming 8251
8251 mode register
Number of
Stop bits
00: invalid
01: 1 bit
10: 1.5 bits
11: 2 bits
Parity enable
0: disable
1: enable
Parity
0: odd
1: even
Character length
00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits
Mode register
Baud Rate
00: Syn. Mode
01: x1 clock
10: x16 clock
11: x64 clock
11375
IR
RTS
ER
SBRK RxE
DTR
TxE
command register
11376
SYNDET
FE
OE
TxRDY:
RxRDY:
TxEMPTY:
PE:
OE:
FE:
SYNDET:
DSR:
PE
TxEMPTY
RxRDY
TxRDY
transmit ready
receiver ready
transmitter empty
parity error
overrun error
framing error
sync. character detected
data set ready
status
register
377
378
379
380
381
382
383
384
385
386
Features:
i. DAC0800 is a monolithic 8-bit DAC manufactured by
National semiconductor.
ii. It has settling time around 100ms
iii. It can operate on a range of power supply voltage i.e.
from 4.5V to +18V. Usually the supply V+ is 5V or +12V.
The V- pin can be kept at a minimum of -12V.
iv. Resolution of the DAC is 39.06mV
387
388
389
TIMER/COUNTER
390
391
392
393
8254 Programming
11-394
8254 Modes
Gate is low the
count will be
paused
Gate is high
Will continue
counting
Gate is
High output
will be high
395
396
397
398
Keyboard/Display
Controller
INTEL 8279
399
400
401
402
Keyboard section
Display section
Scan section
CPU interface section
403
404
405
406
407
408
409
410
411
412
D6
D5
D4
D3
D2
D1
D0
413
SENSOR MATRIX
SENSOR MATRIX
414
B) Programmable clock :
D6
D5
D4
D3
D2
D1
D0
c) Read
below.
D6
D5
D4
D3
D2
D1
D0
AI
416
d) Read
Display RAM :
D6
D5
D4
D3
D2
D1
D0
AI
417
d) Write
Display RAM :
D6
D5
D4
D3
D2
D1
D0
AI
D6
D5
D4
D3
D2
D1
D0
IW
IW
BL
BL
418
g) Clear
Display RAM :
D7
D6
D5
D4
D3
D2
D1
D0
CD2
CD1
CD0
CF
CA
CD2
CD1
CD0
419
h) End
D6
D5
D4
D3
D2
D1
D0
E- Error mode
X- dont care
420
INTERRUPT
CONTROLLER
6. 8259A PIC adds eight vectored priority encoded interrupts to the microprocessor.
slaves.
8
2
5
9
2. IR7- IR0, Interrupt Request inputs are used to request an interrupt and to connect to a slave
in a system with multiple 8259As.
5. INT - the interrupt output connects to the INTR pin on the microprocessor from the master,
and is connected to a master IR pin on a slave.
6. INTA - the interrupt acknowledge is an input that connects to the INTA signal on the system.
In a system with a master and slaves, only the master INTA signal is connected.
7. A0 - this address input selects different command words within the 8259A.
8. CS - chip select enables the 8259A for programming and control.
9. SP/EN - Slave Program/Enable Buffer is a dual-function pin.
ICW1:
Bits D7, D6 , D5and D2 are dont care for microprocessor operation and only
apply to the 8259A when used with an 8-bit 8085 microprocessor.
This ICW selects single or cascade operation by programming the SNGL bit. If
cascade operation is selected, we must also program ICW3.
The LTIM bit determines whether the interrupt request inputs are positive edge
triggered or level-triggered.
ICW2:
Selects the vector number used with the interrupt request inputs.
ICW3:
Is used only when ICW1 indicates that the system is operated in cascade mode.
This ICW indicates where the slave is connected to the master.
For example, if we connected a slave to IR2, then to program ICW3 for this
connection, in both master and slave, we place a 04H in ICW3.
Suppose we have two slaves connected to a master using IR0 and IR1. The
master is programmed with an ICW3 of 03H; one slave is programmed with an
ICW3 of 01H and the other with an ICW3 of 02H.
ICW4:
OCW1:
When a mask bit is set, it will turn off (mask) the corresponding
interrupt input. The mask register is read when OCW1 is read.
Because the state of the mask bits is known when the 8259A is
first initialized, OCW1 must be programmed after programming
the ICW upon initialization.
OCW2:
Is programmed only when the AEOI mod is not selected for the 8259A.
In this case, this OCW selects how the 8259A responds to an interrupt.
OCW3:
Selects the register to be read, the operation of the special mask register, and
the poll command.
If polling is selected, the P-bit must be set and then output to the 8259A. The
next read operation would read the poll word. The rightmost three bits of the
poll word indicate the active interrupt request with the highest priority.
The leftmost bit indicates whether there is an interrupt, and must be checked
to determine whether the rightmost three bits contain valid information.
8237DMA CONTROLLER
453
Introduction:
Direct Memory Access (DMA) is a method of allowing data
0: DRAM refresh
1: Free
2: Floppy disk controller
3: Free
455
8237 pins
CLK: System clock
CS: Chip select (decoder output)
RESET: Clears registers, sets mask register
READY: 0 for inserting wait states
HLDA: Signals that the p has relinquished buses
DREQ3 DREQ0: DMA request input for each channel
DB7-DB0: Data bus pins
IOR: Bidirectional pin used during programming
and during a DMA write cycle
IOW: Bidirectional pin used during programming
and during a DMA read cycle
EOP: End of process is a bidirectional signal used as input to terminate a DMA process or
as output to signal the end of the DMA transfer
A3-A0: Address pins for selecting internal registers
A7-A4: Outputs that provide part of the DMA transfer address
HRQ: DMA request output
DACK3-DACK0: DMA acknowledge for each channel.
AEN: Address enable signal
ADSTB: Address strobe
MEMR: Memory read output used in DMA read cycle
MEMW: Memory write output used in DMA write cycle
456
457
1.
2.
3.
4.
5.
READ/CONTROL LOGIC:
It control all internal Read/Write operation.
Slave mode ,it accepts address bits and control
signal from microprocessor.
Master mode ,it generate address bits and control
signal.
459
1.
2.
3.
It contains ,
Control logic
Mode set register and
Status Register.
CONTROL LOGIC:
461
Programming and
applications Case
studies
462
1. TRAFFIC
LIGHT
CONTROL
463
464
LAN Direction
465
8086 LINES
MODULES
466
8086 ALP:
467
Lookup Table
1200
1201
1205
1209
120D
1211
468
80H
21H,09H,10H,00H (SOUTH WAY)
0CH,09H,80H,00H (EAST WAY)
64H,08H,00H,04H (NOURTH WAY)
24H,03H,02H,00H (WEST WAY)
END
2. LED DISPLAY
469
470
471
472
3. LCD DISPLAY
474
475
476
PORTS
Control port
PORT A
PORT B
PORT C
ADDRESS
FF26
FF20
FF22
FF24
ADDRESS
FF36
FF30
FF32
FF34
478
PORTS
Control port
PORT A
PORT B
PORT C
479
ADDRESS
4003
4000
4001
4002
480
481
482
483
484
485
486
MVI A, 00H
OUT 81H
MVI A, 34H
OUT 81H
MVI A, 0BH
SIM
EI
HERE:
JMP HERE
Interrupt service routine
MVI A, 40H
OUT 81H
IN 80H
MVI H, 62H
MOV L, A
MVI A, 80H
OUT 81H
MOV A, M
OUT 80H
EI
RET
487
5. ALARM
CONTROLLER
Relevant
Material
Not exact
488
489
GPIO- I J1 Connecter
PORTS
ADDRESS
Control port
FF26
PORT A
FF20
PORT B
FF22
PORT C
FF24
GPIO- II J1 Connecter
PORTS
ADDRESS
Control port
FF36
PORT A
FF30
PORT B
FF32
PORT C
FF34
490
Basics
Microprocessor &
Microcontroller
491
What is Microcontroller?
Micro
Very Small
Controller
A mechanism that controls
the operation of a machine
492
493
A smaller computer
On-chip RAM, ROM, I/O ports...
Example: Motorolas 6811, Intels 8051, Zilogs
Z8 and PIC
494
495
Microcontroller
Microprocessor
Expansive
Not Expansive
General-purpose
Single-purpose
496
Home
Office
Auto
497
498
Regulation : 2013
Presented by
C.GOKUL,AP/EEE
UNIT 4 Syllabus
Architecture of 8051
Special Function Registers(SFRs)
I/O Pins Ports and Circuits {Pin Diagram}
Instruction set
Addressing modes
Assembly language programming
499
500
501
502
503
External Interrupts
Interrupt
Control
4K
ROM
Timer 0
256 B
RAM
Timer 1
Counter
Inputs
8bit
CPU
OSC
Bus
Control
Serial
Port
4 I/O Ports
P0
P1
P2
P3
TXD
RXD
504
8 bit CPU
On-chip clock oscillator
4K bytes of on-chip Program Memory-ROM
128 bytes of on-chip Data RAM
64KB Program Memory address space
64KB Data Memory address space
32 bidirectional I/0 lines (Port 0,1,2,3)
Port 0 { P0.0-P0.7 } 8 pins
Port 1 { P1.0-P1.7 } 8 pins
Port 2 { P2.0-P2.7 } 8 pins
Port 3 { P3.0-P3.7 } 8 pins
505
506
Pin Description
of the 8051
or
IO Port structure
507
EA/VPP
EA, external access
EA = 0, 8051 microcontroller access from
external program memory (ROM) only.
EA = 1, then it access internal and external
program memories (ROMS).
508
509
Port 3
Port 3 can be used as input or output.
Port 3 has the additional function of
providing some extremely important
signals
510
TYPE
Vss
Ground: 0 V reference.
Vcc
I/O
I/O
I/O
I/O
P0.0 - P0.7
P1.0 - P1.7
P2.0 - P2.7
P3.0 - P3.7
511
TYPE
RST
ALE
PSEN*
EA*/VPP
512
Architecture of
8051
microcontroller
513
514
515
516
517
8051
Program Memory,
Data Memory
structure
518
External
64K
External
60K
64K
SFR
EXT
INT
EA = 0
EA = 1
4K
Program Memory
128
Data Memory
519
Special
Function
Registers [SFR]
520
A Register (Accumulator)
B Register
Program Status Word (PSW) Register
Data Pointer Register (DPTR)
521
R0
R1
R2
R3
R4
R5
R6
R7
Bank 2
R0
R1
R2
R3
R4
R5
R6
R7
Bank 1
R0
R1
R2
R3
R4
R5
R6
R7
Bank 0
R0
R1
R2
R3
R4
R5
R6
R7
522
C AC F0 RS1 RS0 OV F1 P
Carry
Parity
Auxiliary Carry
User Flag 0
User Flag 1
Register Bank Select
00-Bank 0
01-Bank 1
10-Bank 2
11-Bank 3
Overflow
523
524
INSTRUCTION
SET OF
8051
526
527
1. Arithmetic Instructions
ADD A, source
A A + <operand>.
ADDC A, source
A A + <operand> + CY.
SUBB A, source
A A - <operand> - CY{borrow}.
528
INC
DEC
MUL AB
Multiplication
8 byte * 8 byte
A*B
Result
A=low byte,
B=high byte
DIV AB
Division
8 byte /8 byte
A/B
Quotient
Remainder
B
529
Multiplication of Numbers
MUL AB
A=07 , B=02
MUL AB
Division of Numbers
DIV
AB
A=07 , B=02
DIV AB
2. Logical
instructions
531
ANL D,S
-Performs logical AND of destination & source
- Eg: ANL A,#0FH ANL A,R5
ORL D,S
ORL A,@R0
XRL D,S
-Performs logical XOR of destination & source
- Eg: XRL A,#28H
XRL A,@R0
532
CPL A
-Compliment accumulator
-gives 1s compliment of accumulator data
RL A
-Rotate data of accumulator towards left without carry
RLC A
- Rotate data of accumulator towards left with carry
RR A
-Rotate data of accumulator towards right without carry
RRC A
3. Data Transfer
Instructions
534
MOV Instruction
MOV destination, source ; copy source to destination.
MOV A,#55H ;load value 55H into reg. A
MOV R0,A
;copy contents of A into R0
;(now A=R0=55H)
MOV R1,A
;copy contents of A into R1
;(now A=R0=R1=55H)
MOV R2,A
;copy contents of A into R2
;(now A=R0=R1=R2=55H)
MOV R3,#95H ;load value 95H into R3
;(now R3=95H)
MOV A,R3
;copy contents of R3 into A
;now A=R3=95H
535
MOVX
Data transfer between the accumulator and
a byte from external data memory.
MOVX
MOVX
A, @DPTR
@DPTR, A
536
PUSH / POP
Push and Pop a data byte onto the stack.
PUSH
POP
DPL
40H
537
XCH
Exchange accumulator and a byte variable
XCH
XCH
XCH
A, Rn
A, direct
A, @Ri
538
4.Boolean variable
instructions
539
CLR:
The operation clears the specified bit indicated in
the instruction
Ex: CLR C
clear the carry
SETB:
The operation sets the specified bit to 1.
CPL:
The operation complements the specified bit
indicated in the instruction
540
ANL C,<Source-bit>
-Performs AND bit addressed with the carry bit.
- Eg: ANL C,P2.7 AND carry flag with bit 7 of P2
ORL C,<Source-bit>
541
XORL C,<Source-bit>
-Performs XOR bit addressed with the carry bit.
MOV P2.3,C
MOV C,P3.3
MOV P2.0,C
542
5. Branching
instructions
543
Jump Instructions
LJMP (long jump):
Original 8051 has only 4KB on-chip ROM
544
Call Instructions
LCALL (long call):
Target address within 64K-byte range
545
546
547
8051
Addressing
Modes
1.
2.
3.
4.
5.
6.
7.
8.
Immediate
Register
Direct
Indirect
Relative
Absolute
Long
Indexed
549
550
551
552
MOVX
A,@DPTR
553
5. Relative Addressing
This mode of addressing is used with some type of jump
instructions, like SJMP (short jump) and conditional
jumps like JNZ
Loop
: DEC A
JNZ Loop
;Decrement A
;If A is not zero, Loop
554
6. Absolute Addressing
In Absolute Addressing mode, the absolute
address, to which the control is transferred, is
specified by a label.
Two instructions associated with this mode
of addressing are ACALL and AJMP
instructions.
These are 2-byte instructions
555
7. Long Addressing
This mode of addressing is used with the
LCALL and LJMP instructions.
It is a 3-byte instruction
It allows use of the full 64K code space.
556
8. Indexed Addressing
The Indexed addressing is useful when there is a
need to retrieve data from a look-up table (LUT).
557
8051
Assembly
Language
Programming(ALP)
558
LABEL
9100:
MNEMONICS
MOV A,#05
MOV B,#03
ADD A,B
MOV DPTR,#9200
MOVX @DPTR,A
HERE
SJMP HERE
559
LABEL
9100:
MNEMONICS
CLR C
MOV A,#05
MOV B,#03
SUBB A,B
MOV DPTR,#9200
MOVX @DPTR,A
HERE
After execution: A=02
SJMP HERE
560
MULTIPLICATION OF TWO
8 bit Numbers
Address
9000
Label
START
HERE
Mnemonics
MOV A,#05
9000
Label
START
Mnemonics
MOV A,#05
MOV B,#03
MOV B,#03
MUL AB
DIV AB
MOV DPTR,#9200
MOV DPTR,#9200
MOVX @ DPTR,A
MOVX @ DPTR,A
INC DPTR
INC DPTR
MOV A,B
MOV A,B
MOVX @DPTR,A
MOVX @DPTR,A
SJMP HERE
HERE
SJMP HERE
LOOP:
HERE
quotient
= 04 (remainder) , 01 (quotient)
563
Regulation : 2013
Presented by
C.GOKUL,AP/EEE
UNIT 5 Syllabus
8051
TIMERS
565
8051
Timer
Modes
8051 TIMERS
Timer 0
Timer 1
Mode 0
Mode 0
Mode 1
Mode 1
Mode 2
Mode 2
Mode 3
566
TMOD Register
GATE:
When set, timer/counter x is enabled, if INTx pin is high
and TRx is set.
When cleared, timer/counter x is enabled, if TRx bit set.
C/T*:
When set(1), counter operation (input from Tx input pin).
When clear(0), timer operation (input from internal clock).
567
TMOD Register
00- MODE 0
01- MODE 1
10- MODE 2
11- MODE 3
568
TCON Register
8051 Timer/Counter
OSC
12
C /T = 0
C /T =1
TLx
THx
(8 Bit) (8 Bit)
TFx
(1 Bit)
T PIN
TR
INTERRUPT
Gate
INT PIN
570
TIMER 0
OSC
12
C /T = 0
C /T =1
TL0 TH0
TF0
T 0 PIN
TR0
INTERRUPT
Gate
INT 0 PIN
571
TIMER 0 Mode 0
13 Bit Timer / Counter
OSC
12
C /T = 0
C /T =1
T 0 PIN
TL0
(5 Bit)
TH0
(8 Bit)
TF0
INTERRUPT
TR 0
Gate
INT 0 PIN
TIMER 0 Mode 1
16 Bit Timer / Counter
OSC
12
C /T = 0
C /T =1
T 0 PIN
TL0
(8 Bit)
TH0
(8 Bit)
TF0
INTERRUPT
TR 0
Gate
INT 0 PIN
TIMER 0 Mode 2
8 Bit Timer / Counter with AUTORELOAD
OSC
12
C /T = 0
C /T =1
T 0 PIN
TL0
(8 Bit)
TH0
(8 Bit)
TF0
INTERRUPT
TR 0
Reload
Gate
INT 0 PIN
TH0
(8 Bit)
TIMER 0 Mode 3
Two - 8 Bit Timer / Counter
OSC
12
C /T = 0
C /T =1
T 0 PIN
TL0
(8 Bit)
TF0
INTERRUPT
TH0
(8 Bit)
TF1
INTERRUPT
TR 0
Gate
INT 0 PIN
OSC
12
TR1
575
TIMER 1
OSC
12
C /T = 0
C /T =1
T 1PIN
TR1
TL1 TH1
TF1
INTERRUPT
Gate
INT 1 PIN
576
TIMER 1 Mode 0
13 Bit Timer / Counter
OSC
12
C /T = 0
C /T =1
T 1PIN
TL1
(5 Bit)
TH1
(8 Bit)
TF1
INTERRUPT
TR1
Gate
INT 1 PIN
TIMER 1 Mode 1
16 Bit Timer / Counter
OSC
12
C /T = 0
C /T =1
T 1PIN
TL1
(8 Bit)
TH1
(8 Bit)
TF1
INTERRUPT
TR1
Gate
INT 1 PIN
TIMER 1 Mode 2
8 Bit Timer / Counter with AUTORELOAD
OSC
12
C /T = 0
C /T =1
T 1PIN
TL1
(8 Bit)
TH1
(8 Bit)
TF1
INTERRUPT
TR1
Reload
Gate
INT 1 PIN
TH1
(8 Bit)
Timer modes
(MSB)
TF1 TR1
Timer 1
TR=1: on (start)
TF0 TR0
Timer0
IE1
IT1 IE0
for Interrupt
(LSB)
IT0
(MSB)
TF1 TR1
Timer 1
TF0 TR0
Timer0
IE1
IT1 IE0
for Interrupt
(LSB)
IT0
=
=
SETB TCON.4
CLR TCON.4
SETB TF0
CLR TF0
=
=
SETB TCON.5
CLR TCON.5
SETB TR1
CLR TR1
=
=
SETB TCON.6
CLR TCON.6
SETB TF1
CLR TF1
=
=
SETB TCON.7
CLR TCON.7
For timer 1
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer Mode 1
In following, we all use timer 0 as an example.
16-bit timer (TH0 and TL0)
TH0-TL0 is incremented continuously when TR0 is set to 1. And
the 8051 stops to increment TH0-TL0 when TR0 is cleared.
The timer works with the internal system clock. In other words,
the timer counts up each machine cycle.
When the timer (TH0-TL0) reaches its maximum of FFFFH, it
rolls over to 0000, and TF0 is raised.
Programmer should check TF0 and stop the timer 0.
FFFC
TF = 0
TH0
TR0=0
TL0
Stop timer
FFFD
TF = 0
TF
FFFE
FFFF
0000
TF = 0
TF = 0
TF = 1
Mode 1 Programming
XTAL
oscillator
12
C/T = 0
Timer
overflow
flag
TH
TR
TL
TF
Example 1 (1/3)
square wave of 50% duty on P1.5
Timer 0 is used
;each loop is a half clock
MOV TMOD,#01
;Timer 0,mode 1(16-bit)
HERE: MOV TL0,#0F2H ;Timer value = FFF2H
MOV TH0,#0FFH
CPL P1.5
ACALL DELAY
P1.5
SJMP HERE
50%
whole clock
50%
Example 1 (2/3)
;generate delay using timer 0
DELAY:
SETB TR0
;start the timer 0
AGAIN:JNB TF0,AGAIN
CLR TR0
;stop timer 0
CLR TF0
;clear timer 0 flag
RET
FFF2
FFF3
FFF4
FFFF
0000
TF0 = 0
TF0 = 0
TF0 = 0
TF0 = 0
TF0 = 1
Example 1 (3/3)
Solution:
In the above program notice the following steps.
1. TMOD = 0000 0001 is loaded.
2. FFF2H is loaded into TH0 TL0.
3. P1.5 is toggled for the high and low portions of the pulse.
4. The DELAY subroutine using the timer is called.
5. In the DELAY subroutine, timer 0 is started by the SETB TR0
instruction.
6. Timer 0 counts up with the passing of each clock, which is provided by the
crystal oscillator.
As the timer counts up, it goes through the states of FFF3, FFF4, FFF5, FFF6,
FFF7, FFF8, FFF9, FFFA, FFFB, FFFC, FFFFD, FFFE, FFFFH. One more
clock rolls it to 0, raising the timer flag (TF0 = 1). At that point, the JNB
instruction falls through.
7. Timer 0 is stopped by the instruction CLR TR0. The DELAY subroutine
ends, and the process is repeated.
Notice that to repeat the process, we must reload the TL and TH
registers, and start the timer again (in the main program).
Example 2 (1/2)
This program generates a square wave on pin P1.5 Using timer 1
Find the frequency.(dont include the overhead of instruction delay)
XTAL = 11.0592 MHz
MOV
AGAIN:MOV
MOV
SETB
BACK: JNB
CLR
CPL
CLR
SJMP
TMOD,#10H
TL1,#34H
TH1,#76H
TR1
TF1,BACK
TR1
P1.5
TF1
AGAIN
;timer 1, mode 1
;timer value=3476H
;start
;stop
;next half clock
;clear timer flag 1
;reload timer1
Example 2 (2/2)
Solution:
Note
Example 3 (1/2)
Solution:
1.
2.
3.
4.
5.
Example 3 (2/2)
MOV
AGAIN: MOV
MOV
SETB
BACK: JNB
CLR
CPL
CLR
SJMP
TMOD,#10H
TL1,#00
TH1,#0DCH
TR1
TF1,BACK
TR1
P2.3
TF1
AGAIN
;timer 1, mode 1
;Timer value = DC00H
;start
;stop
;clear timer flag 1
;reload timer since
;mode 1 is not
;auto-reload
Another Explanation
MODE 2 Programming
{8 bit mode}
Auto Reload Mode
8051
Serial
Port
611
612
614
615
616
617
618
SBUF Register
SBUF is an 8-bit register used solely for serial communication.
For a byte data to be transferred via the TxD line, it must be
placed in the SBUF register.
SBUF holds the byte of data when it is received by 8051 RxD
line.
621
SBUF Register
Sample Program:
622
SCON Register
SM0 SM1 SM2 REN TB8 RB8
Set to Enable
Serial Data
reception
Enable Multiprocessor
Communication Mode
TI
RI
623
624
{AUTO RELOAD}
; Timer 1, mode 2
TH1 is loaded to set the baud rate.
; Run Timer 1
; Monitor RI
; Timer 1, mode 2
TH1 is loaded to set the baud rate.
; Run Timer 1
; Monitor RI
8051
Interrupts
635
INTERRUPTS
An interrupt is an external or internal event that
interrupts the microcontroller to inform it that a device
needs its service
A single microcontroller can serve several devices by two
ways:
1. Interrupt
2. Polling
636
Interrupt
Upon receiving an interrupt signal, the
microcontroller interrupts whatever it is doing
and serves the device.
The program which is associated with the
interrupt is called the interrupt service routine
(ISR) .
637
Interrupt Vs Polling
1. Interrupts
Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal.
Upon receiving an interrupt signal, the microcontroller interrupts
whatever it is doing and serves the device.
The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
2. Polling
The microcontroller continuously monitors the status of a given
device.
When the conditions met, it performs the service.
After that, it moves on to monitor the next device until every one
is serviced.
Interrupt Sources
Original 8051 has 6 sources of interrupts
Reset (RST)
Timer 0 overflow (TF0)
Timer 1 overflow (TF1)
External Interrupt 0 (INT0)
External Interrupt 1 (INT1)
Serial Port events (RI+TI)
{Reception/Transmission of Serial Character}
642
644
EA : Global enable/disable.
--- : Reserved for additional interrupt hardware.
MOV IE,#08h
or
SETB ET1
Interrupt Priority
646
Reserved
PS
PT1 PX1
PT0
PX0
Serial Port
Timer 1 Pin
INT 1 Pin
INT 0 Pin
Timer 0 Pin
648
649
KEYBOARD
INTERFACING
KEYBOARD INTERFACING
Keyboards are organized in a matrix of rows
and columns
The CPU accesses both rows and columns
through ports .
651
4x4 matrix
652
653
Final Circuit
Stepper Motor
Interfacing
656
657
658
659
Full step
660
Step angle:
Step angle is defined as the minimum degree of rotation
with a single step.
No of steps per revolution = 360 / step angle
Steps per second = (rpm x steps per revolution) / 60
Example: step angle = 2
No of steps per revolution = 180
661
TURN:
CW:
662
SETB P2.7
MOV A, #66H
MOV P1,A
JNB P2.7, CW
RL A
ACALL DELAY
MOV P1,A
SJMP TURN
RR A
ACALL DELAY
MOV P1,A
SJMP TURN
LCD Interfacing
using 8051
663
664
665
666
A/D Interfacing
using 8051
668
ADC Interfacing:
669
D/A Interfacing
using 8051
671
672
SENSOR
INTERFACING
take temperature sensor for example
674
potentiometer
Shunt voltage
diodes
675
EXTERNAL
MEMORY
INTERFACING
Refer book Mohammad Ali
Explanation is not sufficient
676
678
Presented by C.GOKUL,AP/EEE , Velalar College of Engg & Tech, Erode
Documents References
8086 SYSTEM BUS STRUCTURE by Prof.L.PETER STANLEY
BEBINGTON ( PROFESSOR AND
DEAN(ACADEMIC),VCET,Erode)
I/O Interfacing by Prof.P.JAYACHANDAR , ASSOCIATE
PROFESSOR and DEAN(SA),VCET,Erode
8086 Microprocessor by Dr. M. Gopikrishna ,Assistant Professor of
Physics,Maharajas College ,Ernakulam
8086 architecture By Er. Swapnil Kaware
8086 presentations by Gursharan Singh Tatla (Eazynotes.com)
Microprocessor - Ramesh Gaonkar
8086 micro processor prasadpawaskar
8086 class notes-Y.N.M by MURTHY Y.N
Introduction to 8086 Microprocessor by Rajvir Singh
8086 micro processor by Poojith Chowdhary
8086 ASSEMBLY LANGUAGE PROGRAMMING Cutajar & Cutajar
Intel microprocessor history by Ramzi_Alqrainy
679
Website References
http://80864beginner.com/
www.eazynotes.com
www.slideshare.net
www.scribd.com
www.docstoc.com
www.slideworld.com
www.nptel.ac.in
http://opencourses.emu.edu.tr/
http://engineeringppt.blogspot.in/
http://www.pptsearchengine.net/
www.4shared.com
http://8085projects.info/
680