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Part 2: Applications
HAVING -D
the BIST pattern generation and response analysis
concepts in Part 1, we now focus on
their implementation.First we will d e
scribethe testing of general logic;then
we will briefly discuss testing a p
proaches for sbuctured logic such as
ROMs, RAMS, and PUS. We refer the
reader back to Table2 in Part 1, which
containstypicalpattern generatorand
response analyzersbuctures.Here,we
concentrate almost entirely on the
LFSR and MISR structures. For these
sttuctures,scan is an integml part of the
design. Note also that ROMs and
counters can be useful as supple
ments or alternatives to a number of
the structures described.
VlSHWANl D. AGRAWAL
AT&T Bell Laboratories
CHARLES R. KlME
KEWAL K. SALUJA
University of Wisconsin,
Madison
Concluding an overview of b *
self-test (BIST) concepts a
practices, Part 2 covers B
hardware structures, applica
and tools. The authors
testing approaches for g
structured logic. They illustrate BtST
techniques with rea
examples and present
structures and software tools
supporting BIST design.
0740-7475/93/0600-0069$03.00
0 1993 IEEE
Shift register
...
MlSR
ial
ibl
Figure 1. Test-per-clockconfigurations.
CUT
LFSR
li
...
Input network
LFSR
ibl
II
so+/eHuJ
1
Scan register SRI
...
MlSR
fd
Figure 2. Test-per-scanconfigurations.
70
B1
Dn-1
Dn
B2
so
SI
Clock
Q1
Q2
Qn
E]
0 Serial scan
fbl
fdl
(cl
Figure 3. A modified BllBO configuration: hardware (a),operating modes (b), application structure (c), and application modes (dl.
ScanjVCirculate
Qt
0) GP
SI
Inputs
1
:. C gA
:
Corn binational
logic
.. -
outputs
I-1
[r
:
i iz
4A
1
Internal flip-flops
JUNE 1993
BlST glossary
Aliasing: condition in which a faulty circuit with erroneous response produces the same signatureas a good circuit
Design for testability (DFT): any process applied to a circuit design that
facilitates testing the circuit
Exhaustive testing: a testingtechnique
that applies all possible input combinations to the circuit under test
Fault coverrrge: ratio, expressed as a
fractionor percentage, of all faults deteded by a test sequence to the toto1
modeledfaults in the circuit under test
In-cimuittesfing0:
a methodthat uses
direct access to the chip pins to test
chips or intercondons on a b a r d
Level-sensitive scan design (LSSD): a
variant of the serial scan design concept defined by IBM
Linear feedback shift register (LFSR):
a circuit made up of flip-flops and
XOR gates interconnected in certain
configurations (typically used for
BlST pattern generation and response analysis)
Muk+inputsignahJre register (MISR):
an LFSR-basedBlST circuit that simultaneously compacts multipleresponse
sequences for response analysis
Partialscan: a DFT technique in which
only a subset of all circuit flip-flops
is scannable
Patiwn an ordered set of binaty values
that is applied simultaneouslyto the inputs of a circuit or that appean simultaneously on the ouputs of a circuit
Programmable logic army (PIA):usually refers to a structured implementation of a digital function based on
a two-level AND/OR description of
the combinationalpartof the function
Pseudoexhaustive testing: a testing
Additional logic
in AND plane
Additional logic
to control
output lines
Additional
logic
to
control
product
lines
control
block
i
.
.:
AND plane
OR plane
t t
...
PLA inputs
Additional
logic
in
OR
plane
...
PLA outputs
that until some novel technique appears, BlST will be practical only for
small- to medium-size PLAs that can be
tested exhaustively or for cases where
multiple-fault detection is so important
that the silicon area overhead is a secondary consideration.
ROM, embedded orstand-alone,is relatively easy to test. The basic method is to
read the ROM contents and compact the
outputs by means of an MISR. Both the
pattern generator and the response analyzer are simple structures. Aliasing is a
problem only if the probability of rnultiple bit errors in the ROM outputs is high.
Typical multiple bit errors are caused by
the failure of an output buffer or a decoder circuit. Such faults either are not
masked by the MISR or can be detected
relatively easily by a few extra deterministic test vectors.Also, faults in the control
part of the ROM are often catastrophic
and hence are detected by a test that simply reads the ROM contents.
In deriving tests for RAMS, engineers
have used different fault models for different parts of a RAM. For example, the fault
model for decoders includes not only
stuck-at faults but also arbitrary addressmapping faults. For the memory array, on
74
RAM self-testand performs delay testing. Table 1. CAD fools for BIST/DFT. *
The RISC/6000sBIST system is hierar- ,
Vendor/Tool
Capabilities
chically structured,with a common on- ,
chip processor (COP) on each chip. The I
TRDC: test rules design checker; Scangen: automatic
Crosscheck
COP, which occupies less than 3%of the
AlDA Testability Tools scan insertion (single/multiplechain), combinational
chip area, contains an LESR for pattern
test generator; Fltsim: fault simulator; boundary-scan
generation, an MlSR for response comsupport available
paction, and a counter for addressing
Cerberus: design rule checker, automatic scan register
Siemens
during RAM testing. In addition,the COP
insertion, overhead optimization; Socrates:combinaCerberus, Socrates
contains a control finitestate machine,
tional test generator
attached by a few dozen control lines to
Full or partial scan, testability analyzers, sequential
Racal-Redac
the normal onchip and BIST logic. Each
circuit test generator, CADAT fault simulator, boundaryIntelligen 2
chip also has boundary scan.
scan support available
For delay tests, two normal clock p h s
Redundancyremoval from automatically synthesized
Synopsys
es are applied in sequence at normal o p
circuit, automatic scan insertion and test generation
Test Compiler
erating speed between scan-in and
Alert: design rule checker, combinational test
AT&T
scan-ut operations. For RAM tests, RAM
generator, fault simulators, scan overhead optimizer for
Titus, Testpilot
data inputs and outputs are attached distandard-cell design; Gentest/Pascant: partial scan and
rectly to scan paths by means of DFr
sequential circuit test generator; CKT: automatic circular
techniques, and RAM address and read/
BIST; PEST: pseudoexhaustive self-test; Maclog: BlST
write controls are attached to the COP.
~
BlST tools
Most designers of BIST circuits use
general-purpose tools such as logic and
fault simulators,but somespecialized tools
have also been developed. Table 1 pre
sents a list of commerciallyavailable CAD
tools suitable for BISTcircuit design.These
are largely analysis tools, and some have
their origin in the DFr environment. Such
tools can be useful because DlT is often a
precursor to BET. Next we describe some
hardware structures and software design
systems developed specifically for BIST
implementations.
Cadence
TestScan
Philips
Panther Tool Kit
Sunrise
TestGen/Test Syn
~
macrocell generator
Design rule audit (random and serial scan), manual
scan register implementation,combinational test
generator, fault simulator
DFT rule checker, testability hardware insertion,
automatic full-scan design and scan chain routing, test
control block generator, combinationaltest pattern
generator, boundary-scaninsertion
Partial scan and sequential circuit test generator
*Due to rapid growth in this field, vendor offerings may have changed and new products
may be available.
testing these blocks require special access to the I/O pins. Such access requires
extra routing area. BIST design of embedded memory blocks keeps the routing
overhead contained and is widely used
in ASIC3 and custom chip^.'^^'^ A variety
of tests can be generated from the BIST
circuitry-for example,tests for cellstuck
faults and data retention faults. The overhead is about 5% for l&Kbit static RAM
and decreases for larger memories. The
Cathedral-I1silicon compiler system also
uses a BlST memory approach?0
design sy9
General Electrics
ternz1partitionsa chip into macrocellsand
JUNE 1993
..
OF COMPUTERS
pp. 52-63.
13. B. Nadeau-Dostie, A. Silburt, and V.K.
Agarwal, Serial Interfacing for Embedded-MemotyTesting,IEEEDesign & Test
ofcomputers,Vol.7, No. 2, Apr. 1990,pp.
52-63.
14. K. Kinoshita and K.K. Saluja, Built-In
Testing of Memory Using an OnChip
Compact Testing Scheme, IEEE Trans.
Computers,Vol. C-35, No. 10, Oct. 1986,
pp. 862-870.
15. M. Franklin and K.K. Saluja, Built-InSelfTest of Random-AccessMemories,Computer,Vol.23, No. 10,Oct. 1990,pp. 45-56.
16. P. Gelsinger, Design and Test of the
80386,IEEEDesign & Test ofComputers,
Vol.4, No. 3,June 1987, pp. 42-50.
17. I.M. Ratiu and H.B. Bakoglu, Pseudorandom Built-In Self-Test Methodology and
Implementation for the IBM RlSC System/
6000 Processor,IBMJ. Research and Deoelopment,Vol. 34, Jan. 1990,pp. 78-84.
18. J.P. Mucha, W. Daehn, and J. Gross, SelfTest in a Standard Cell Environment,
IEEEDesign & Test of computers,Vol.3,
No. 6, Dec. 1986, pp. 3541.
19. R. Dekker, F. Beenker, and L. Thijssen,
Realistic Built-In Self-Test for Static
RAMS,IEEEDesign & Test ofComputers,
Vol. 6, No. 1, Feb. 1989,pp. 2&34.
20. F. Catthoor, J. van Sas, L. Inze, and H. de
Man, ATestabilityStrategy for Multipre
cessor Architecture, IEEEDesign & Test
ofComputers,Vol.6, No. 2, Apr. 1989,pp.
B34.
2 1. R.C. Kroeger,TestabilityEmphasis in the
General Electric ANLSl Program, IEEE
Design & Test of Computers,Vol. 1,No. 2,
May 1984,pp. 6165.
22. Y. Zorian, A Structured Approach to
Macrocell Testing Using Built-In SelfTest, Roc. IEEE Custom Integrated Circuits Con[, 1990, pp. 28.3.1-28.3.4.
23. E. Wu, PEST: A Tool for Implementing
PseudeExhaustiveSelf-Test,AT&TTechnicalJ.,Vol. 70, No. 1, Jan./Feb. 1991,pp.
87-100.
24. M.M. Pradhan et al., Circular BIST with
Partial Scan, Roc. Intl Test Cod, IEEE
CS Press, 1988,pp. 719729.
25. H.S. Fung and S. Hirschhom, An Auto
JUNE 1993
Lewal K. Saluja a professor in the Departlent of Electrical and Computer Engineerig at the University of Wisconsin-Madison,
rhere he teaches logic design, computer
rchitecture, microprocessor-based sysms, and VLSl design and testing. Previous{, he worked at the University of Newcastle,
ustralia. He has also held visiting and conulting positions at the University of Southrn California, the University of Iowa, and
liroshima University. His research interests
iclude design for testability, fault-tolerant
omputing, VLSI design, and computer arhitecture. He is an associate editor of the
ournal ofElectronic Testing: Theoryand Ap
dications. Saluja received the BE from the
Jniversity of Roorkee, India, and the MS and
he PhD in electrical and computer engileering from the University of Iowa. He is a
nember of the IEEE Computer Society.