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ADDRESSING MODES OF
Fixed point DSPs (TMS320C54X series)
mode
Parallel addressing mode
Bit-reversed addressing
mode
MMREG addressing mode
Stack addressing mode
0h - 7Fh in Hexadecimal
Long Immediate addressing mode:
Syntax ADD #200h,A ; SUB #1200h,B
If the operand size is greater than 7-bits the IW is two word
One word is opcode and the next word is operand
Then the mode is called Long immediate addressing
The mini. and max. value of the operand is 0 65535 in decimal
and 0h - FFFFh in Hexadecimal
8 MSBs Opcode
7th Bit - I bit, I = 0 Direct addressing
I = 1 Indirect addressing mode
7 LSBs location in a page
SP
10
11
12
Instructions
LD # 0Fh, BK
LD #1020h,AR2
LD #10, AR3
loop ADD *AR2+%,A
ADD *AR2+%, A
Operation
load the buffer size in BK
load the address in AR2
ADD *AR2+%, A
16th instruction
After the access of current AR2
content, AR2 is incremented by one
and it is compared with EOB, if the
comparison is true the AR2 is
automatically loaded with
TOB without any instruction.
Branch on no zero of AR3 to label loop
Decrementing of AR3 and checking its
zero value will be done by ARAU
without any instruction
13
14
15
16
Stack Addressing
The system stack is used to automatically store the program counter during
interrupts and subroutines
Four instructions access the stack using the stack addressing mode:
PSHD pushes a data-memory value onto the stack.
PSHM pushes a memory-mapped register onto the stack.
POPD pops a data-memory value from the stack.
POPM pops a memory-mapped register from the stack.
Register Addressing
Register addressing mode uses the CPU general purpose registers.
If the CPU of the processor has more number of general purpose registers,
then the CPU register can be used to hold operands and results.
Example: In `C3X there are eight general purpose registers R0-R7. These
register can be used for addressing.
ADD R0,R1
SUB R2,R3
MPY R1,R2
17
18
LD #1300h, AR3
19
the same.
20
21
22
23
(Smem) operand.
e.g. ADD *(1000h),A
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25
End of Part-3