Escolar Documentos
Profissional Documentos
Cultura Documentos
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96 kHz Sample Rate
Multibit Sigma-Delta Modulator with Perfect Differential
Linearity Restoration for Reduced Idle Tones and
Noise Floor
Data Directed Scrambling DACLeast Sensitive to Jitter
Differential Output for Optimum Performance
113 dB Dynamic Range at 48 kHz Sample Rate
(AD1854KRS)
112 dB Signal-to-Noise at 48 kHz Sample Rate
(AD1854KRS)
101 THD+N (AD1854KRS)
On-Chip Volume Control with 1024 Steps
Hardware and Software Controllable Clickless Mute
Zero Input Flag Outputs for Left and Right Channels
Digital De-Emphasis Processing
Supports 256 F S or 384 F S Master Mode Clock
Switchable Clock Doubler
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, LeftJustified, and I2S-Compatible
28-Lead SSOP Plastic Package
APPLICATIONS
DVD, CD, Set-Top Boxes, Home Theater Systems,
Automotive Audio Systems, Sampling Musical
Keyboards, Digital Mixing Consoles, Digital Audio
Effects Processors
CONTROL DATA
INPUT
VOLUME
MUTE
SERIAL CONTROL
INTERFACE
AD1854
16-/18-/20-/24-BIT
DIGITAL
DATA INPUT
SERIAL
DATA
INTERFACE
ATTEN/
MUTE
8 FS
INTERPOLATOR
ATTEN/
MUTE
8 FS
INTERPOLATOR
CLOCK
CIRCUIT
VOLTAGE
REFERENCE
DAC
OUTPUT
BUFFER
DAC
OUTPUT
BUFFER
ANALOG
OUTPUTS
SERIAL 2
MODE
2
PD/RST
MUTE
DE-EMPHASIS
ANALOG
SUPPLY
2
ZERO
FLAG
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
AD1854SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
5.0 V
25C
12.288 MHz (256 FS Mode)
1.0013 kHz
0.5 dB Full Scale
48 kHz
20 Hz to 20 kHz
20 Bits
100 pF
47 k
2.4 V
0.8 V
Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
ANALOG PERFORMANCE
Min
Resolution
Signal-to-Noise Ratio (20 Hz to 20 kHz)
No Filter (AD1854JRS)
No Filter (AD1854KRS)
With A-Weighted Filter (AD1854JRS)
With A-Weighted Filter (AD1854KRS)
Dynamic Range (20 Hz to 20 kHz, 60 dB Input)
No Filter (AD1854JRS)
No Filter (AD1854KRS)
With A-Weighted Filter (AD1854JRS)
With A-Weighted Filter (AD1854KRS)
Total Harmonic Distortion + Noise (AD1854JRS) VO = 0 dB
Total Harmonic Distortion + Noise (AD1854KRS) VO = 0 dB
Total Harmonic Distortion + Noise (AD1854JRS and
AD1854KRS) VO = 20 dB
Total Harmonic Distortion + Noise (AD1854JRS and
AD1854KRS) VO = 60 dB
Analog Outputs
Differential Output Range ( Full Scale)
Output Impedance at Each Output Pin
Output Capacitance at Each Output Pin
Out-of-Band Energy (0.5 FS to 100 kHz)
CMOUT
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Mute Attenuation
De-Emphasis Gain Error
106
108
88
94
Typ
Max
20
Bits
105
110
108
112
dB
dB
dB
dB
105
110
108
113
97
101
89
dB
dB
dB
dB
dB
dB
dB
49
dB
5.6
<200
V p-p
pF
dB
V
20
72.5
2.25
11.0
0.15
Unit
3.0
200
120
0.1
100
+11.0
+0.15
300
0.1
%
dB
ppm/C
dB
Degrees
dB
dB
Max
Unit
Min
Input Voltage HI (VIH)
Input Voltage LO (VIL)
High Level Output Voltage (VOH) IOH = 1 mA
Low Level Output Voltage (VOL) IOL = 1 mA
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
Input Capacitance
Typ
2.2
0.8
2.0
0.4
10
10
20
V
V
V
V
A
A
pF
REV. A
AD1854
POWER
Supplies
Voltage, Analog and Digital
Analog Current
Analog CurrentPower-Down
Digital Current
Digital CurrentPower-Down
Dissipation
OperationBoth Supplies
OperationAnalog Supply
OperationDigital Supply
Power-DownBoth Supplies
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
Min
Typ
Max
Unit
4.5
26
26
14
1.5
5
30
29
17
2.5
5.5
35
33.5
20
5.5
V
mA
mA
mA
mA
190
mW
mW
mW
mW
250
150
100
60
50
dB
dB
TEMPERATURE RANGE
Min
Specifications Guaranteed
Functionality Guaranteed
Storage
Typ
Max
Unit
70
+125
C
C
C
25
0
55
DIGITAL TIMING (Guaranteed over 0C to 70C, AVDD = DVDD = 5.0 V 10%)
Min
tDMP
tDMP
tDMP
tDML
tDMH
tDBH
tDBL
tDBP
tDLS
tDLH
tDDS
tDDH
tPDRP
Max
35
48
70
0.4 tDMP
0.4 tDMP
20
20
140
20
5
5
10
4 MCLK Periods
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
0.04
47
0.448
0.552
106/FS
0
Passband Ripple
Stopband Attenuation
Passband
Stopband
Group Delay
Group Delay Variation
Specifications subject to change without notice.
REV. A
Typ
Max
Unit
dB
dB
FS
FS
sec
s
AD1854
ABSOLUTE MAXIMUM RATINGS*
DVDD to DGND
AVDD to AGND
Digital Inputs
Analog Outputs
AGND to DGND
Reference Voltage
Soldering
PIN CONFIGURATION
Min
Max
Unit
0.3
0.3
DGND 0.3
AGND 0.3
0.3
+6
+6
DVDD + 0.3
AVDD + 0.3
+0.3
(AVDD + 0.3)/2
300
10
V
V
V
V
V
DGND 1
28
DVDD
MCLK 2
27
SDATA
CLATCH 3
26
BCLK
CCLK 4
25
L/RCLK
CDATA 5
24
PD/RST
23
MUTE
384/256 6
C
sec
ZEROL
TOP VIEW
ZEROR 8 (Not to Scale) 21 IDPM0
X2MCLK 7
22
DEEMP 9
20
IDPM1
96/48 10
19
FILTB
AGND 11
18
AVDD
OUTR+ 12
17
OUTL+
OUTR 13
16
OUTL
FILTR 14
15
AGND
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE CHARACTERISTICS
Min
JA (Thermal Resistance
[Junction-to-Ambient])
JC (Thermal Resistance
[Junction-to-Case])
Typ
Max
AD1854
Unit
109
C/W
39
C/W
ORDERING GUIDE
Model
Temperature
Package Description
Package Option
AD1854JRS
AD1854JRSRL
AD1854KRS
AD1854KRSRL
0C to 70C
0C to 70C
0C to 70C
0C to 70C
RS-28
RS-28 on 13" Reels
RS-28
RS-28 on 13" Reels
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1854 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
AD1854
PIN FUNCTION DESCRIPTIONS
Pin
Input/Output
Pin Name
Description
1
2
I
I
DGND
MCLK
3
4
I
I
CLATCH
CCLK
CDATA
384/256
7
8
I
O
X2MCLK
ZEROR
DEEMP
10
11, 15
12
13
14
I
I
O
O
O
96/48
AGND
OUTR+
OUTR
FILTR
16
17
18
19
20
O
O
I
O
I
OUTL
OUTL+
AVDD
FILTB
IDPM1
21
IDPM0
22
ZEROL
23
MUTE
24
PD/RST
25
26
I
I
L/RCLK
BCLK
27
SDATA
28
DVDD
Digital Ground.
Master Clock Input. Connect to an external clock source at either 256, 384
or 512 FS.
Latch input for control data. This input is rising-edge sensitive.
Control clock input for control data. Control input data must be valid on the
rising edge of CCLK. CCLK may be continuous or gated.
Serial control input, MSB first, containing 16 bits of unsigned data per
channel. Used for specifying channel-specific attenuation and mute.
Selects the master clock mode as either 384 times the intended sample
frequency (HI) or 256 times the intended sample frequency (LO). The state
of this input should be hardwired to logic HI or logic LO, or may be changed
while the AD1854 is in power-down/reset. It must not be changed while the
AD1854 is operational.
Selects internal clock doubler (LO) or internal clock = MCLK (HI).
Right Channel Zero Flag Output. This pin goes HI when Right Channel has
no signal input for more than 1024 LR Clock Cycles.
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI.
This is used to impose a 50 s/15 s response characteristic on the output
audio spectrum at an assumed 44.1 kHz sample rate.
Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.
Analog Ground.
Right Channel Positive line level analog output.
Right Channel Negative line level analog output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10 F and 0.1 F capacitors to the AGND.
Left Channel Negative line level analog output.
Left Channel Positive line level analog output.
Analog Power Supply. Connect to analog 5 V supply.
Filter Capacitor connection, connect 10 F capacitor to AGND.
Input serial data port mode control one. With IDPM0, defines one of four
serial modes.
Input serial data port mode control zero. With IDPM1, defines one of four
serial modes.
Left Channel Zero Flag Output. This pin goes HI when Left Channel has no
signal input for more than 1024 LR Clock Cycles.
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.
Power-Down/Reset. The AD1854 is placed in a low power consumption
mode when this pin is held LO. The AD1854 is reset on the rising edge of
this signal. The serial control port registers are reset to the default values.
Connect HI for normal operation.
Left/Right clock input for input data. Must run continuously.
Bit clock input for input data. Need not run continuously; may be gated or
used in a burst fashion.
Serial input, MSB first, containing two channels of 16, 18, 20, and 24 bits of
twos complement data per channel.
Digital Power Supply Connect to digital 5 V supply.
REV. A
AD1854
Figure 1 shows the right-justified mode (16-bit mode). L/RCLK
is HI for the left channel, LO for the right channel. Data is valid
on the rising edge of BCLK. The MSB is delayed 16-bit clock
periods from an L/RCLK transition, so that when there are 64
BCLK periods per L/RCLK period, the LSB of the data will be
right justified to the next L/RCLK transition. The right-justified
mode can also be used with 20-bit or 24-bit inputs as selected
in Table I.
OPERATING FEATURES
Serial Data Input Port
L/RCLK is HI for the left channel, and LO for the right channel.
Data is valid on the rising edge of BCLK. The MSB is leftjustified to an L/RCLK transition, with no MSB delay. The
left-justified mode can be used with 16-/18-/20- or 24-bit inputs.
IDPM1
(Pin 20)
IDPM0
(Pin 21)
0
0
1
1
Bit Clock
0
1
0
1
0
FS
96/48
MCLK
X2MCLK
384/256
0
0
0
0
1
1
1
1
256 FS
384 FS
512 FS
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
L/RCLK
INPUT
128 FS
(384/2) FS
256 FS
LEFT CHANNEL
Note
Not Allowed
Not Allowed
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB
MSB
MSB1 MSB2
LSB+2 LSB+1
LSB
MSB
MSB1 MSB2
LSB+2 LSB+1
LSB
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB1 MSB2
LSB+2
LSB+1
LSB
MSB
MSB1 MSB2
LSB+2 LSB+1
LSB
MSB
REV. A
AD1854
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB1 MSB2
LSB+2
LSB+1
LSB
MSB
MSB1 MSB2
LSB+2
LSB+1
LSB
MSB
MSB1
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB
MSB
MSB1
MSB2
LSB+2
LSB+1
LSB
MSB
MSB1
MSB2
LSB+2
LSB+1
LSB
MSB
MSB1
t CCP
CDATA
D15
CCLK
D14
D0
t CCH
t CCL
t CSU
t CLL
t CLH
CLATCH
The serial control port is byte oriented. The data is MSB first,
and is unsigned. There is one control register for the left
channel or the right channel, as distinguished by Bit Data 10.
For power-up and reset, the default settings are: Data 11 the
mute control bit, reset default state is LO, which is the normal
(nonmuted) setting. Data 10 is LO, the Volume 9 through
Volume 0 control bits have a reset default value of 11 1111 1111,
which is an attenuation of 0.0 dB (i.e., full scale, no attenuation).
The intent with these reset defaults is to enable AD1854 applications without requiring the use of the serial control port. For those
users who do not use the serial control port, it is still possible to
mute the AD1854 output by using the MUTE (Pin 23) signal.
tCCH
tCCL
tCCP
tCSU
tCHD
tCLL
tCLH
CCLK HI Pulsewidth
CCLK LO Pulsewidth
CCLK Period
CDATA Setup Time
CDATA Hold Time
CLATCH LO Pulsewidth
CLATCH HI Pulsewidth
Min
Unit
40 (Burst Mode)
40 (Burst Mode)
80 (Burst Mode)
10
10
10
130 (Burst Mode)
ns
ns
ns
ns
ns
ns
ns
The SPI port can be used in either of two modes, Burst Mode,
or Continuous CCLK Mode, as described below.
Continuous CCLK Mode
REV. A
IDPM0
Input
Mode0
Select
Soft
PowerDown
Data 11
Data 10 Data 9
Soft
1/Mute
1/Right
De0/Normal 0/Left
Emphasis (Nonmute)
Data 8
Data 7
LSB
Data 0
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Volume
Control
Data
Volume
Control
Data
Volume
Control
Data
Volume
Control
Data
Volume
Control
Data
Volume Volume
Control Control
Data
Data
AD1854
CLATCH
>130ns
CCLK
CDATA
20
40
60
80
100
120
140
160
180
TIME ns
CLATCH
CCLK
CDATA
200
400
600
800
1000
1200
1400
1600
1800
TIME ns
Mute
Power-Down Reset
De-Emphasis
LEVEL dB
Control Signals
60
0
ACTUAL VOLUME REGISTER
60
20ms
TIME
REV. A
AD1854
Timing Diagrams
minimum setup time is tDDS and the minimum serial data hold
time is tDDH.
The serial data port timing is shown in Figures 9 and 10. The
minimum bit clock HI pulsewidth is tDBH and the minimum bit
clock LO pulsewidth is tDBL. The minimum bit clock period is
tDBP. The left/right clock minimum setup time is tDLS and the
left/right clock minimum hold time is tDLH. The serial data
tDBH
The power-down/reset timing is shown in Figure 11. The minimum reset LO pulse width is tPDRP (four MCLK periods) to
accomplish a successful AD1854 reset operation.
tDBP
BCLK
tDBL
tDLS
L/RCLK
SDATA
LEFT-JUSTIFIED
MODE
tDDS
MSB
MSB-1
tDDH
tDDS
SDATA
I2S-JUSTIFIED
MODE
MSB
tDDH
tDDS
tDDS
SDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
tDDH
tDDH
tDBH
tDBP
BCLK
tDBL
tDLS
L/RCLK
tDLH
tDDS
SDATA
LEFT-JUSTIFIED
DSP SERIAL
PORT STYLE MODE
MSB
MSB-1
tDDH
Figure 10. Serial Data Port TimingDSP Serial Port Style Mode
tDMP
tDMH
MCLK
PD/RST
tDML
tPDRP
REV. A
AD1854
MCLK/SR SELECT
SELECT RATE X2MCLK 384/256 96/48
DVDD
MCLK/SR
SEL JP1
R3
10k
R2
10k
R1
10k
SPDIF
DIRECT
DIRECT
0
0
1
0
0
0
0
0
0
44.1
48.0
96.0
MCLK
11.2896
12.2880
12.2880
SDATA
AUDIO
DATA
DVDD
AVDD
C3
100nF
C2
100nF
LRCLK
SCLK
DVDD
MCLK
IDPM1 IDPM0
RJ, 16-BIT
I2S
RJ, 20-BIT
RJ, 24-BIT
LJ
0
0
1
1
BCLK
C13
1nF, NP0
X2MCLK
R17
1.96k
SDATA
OUTL+
L/RCLK
R20
549
R10
953
JP2
U1
AD1854JRS
MCLK
R5
10k
IDPM0
DE-EMPHASIS
OUTR
DEEMP
R12
953
MUTE
C16
R19 1nF, NP0
1.96k
CLATCH
CCLK
CCLK
CDATA
+AVCC
C11
390pF
NP0
C5
100nF
R21
549
R14
953
R15
2.15k
ZR
ZEROR
LEFT
OUT
53.6k
U3A
OUTR+
CDATA
C15
2.2nF
NP0
J1
C17
1nF, NP0
MUTE
CLATCH
R13
2.15k
R18
1.96k
IDPM1
SSM2135
C10
390pF
NP0
BCLK
R4
10k
U3B
R11
2.15k
DVDD
I/F
MODE
C9
390pF
NP0
C14
1nF, NP0
384/256
0
1
0
1
0
R8
953
OUTL
96/48
I/F MODE
R9
2.15k
R16
1.96k
AVDD
C12
390pF
NP0
C18
2.2nF
SSM2135 NP0
C6
100nF
J2
RIGHT
OUT
53.6k
ZL
RST
ZEROL
FILTR
PD/RST
FITLB
DGND
AVEE
C1
100nF
AGND AGND
+ C8
10F
DGND
FB1
600Z
CDATA
CONTROL
PORT
+ C7
10F
CCLK
DVDD
CLATCH
C4
100nF
NOTE:
= DGND
ZL
U2A
HC04
1
2
= AGND
CR1
ZERO LEFT
R6
221
CR2
ZERO RIGHT
R7
221
U2B
HC04
ZR
10
REV. A
AD1854
8
10
12
14
FREQUENCY kHz
16
18
20
20
40
40
60
60
80
80
100
100
120
120 110 100 90 80 70 60 50 40 30 20 10
AMPLITUDE dBFS
40
45
45
50
50
55
55
60
60
65
65
70
70
75
75
80
80
85
85
dBr A
40
dBr B
40
40
45
45
50
50
55
55
60
60
65
65
70
70
75
90
90
75
95
95
80
80
85
85
100
100
105
105
110
110
20
10
12
14
8
FREQUENCY kHz
16
18
90
20
50
60
50
60
70
80
90
70
80
90
100
110
120
130
100
110
120
130
140
150
160
140
150
160
8
10
12
14
FREQUENCY kHz
16
18
20
200
2k
500 1k
FREQUENCY Hz
5k
10k
20k
90
0
10
10
20
20
30
40
50
30
40
50
60
dBr B
10
20
30
40
100
10
20
30
40
50
dBr A
dBr A
dBr A
120
0
dBr B
60
70
70
80
90
100
110
80
90
100
110
120
130
120
130
140
150
140
150
160
dBr B
60
65
70
75
80
85
90
95
100
105
110
115
120
125
130
135
140
145
150
155
160
20
dBr A
60
65
70
75
80
85
90
95
100
105
110
115
120
125
130
135
140
145
150
155
160
dBr B
dBr A
dBr B
TYPICAL PERFORMANCE
8
10
12
14
FREQUENCY kHz
16
18
160
20
11
AD1854
0
30
20
30
40
40
50
50
60
60
70
70
80
80
90
90
100
100
110
120
110
130
130
140
140
30
40
dBr A
60
70
80
90
100
20
40
60
80
100
FREQUENCY kHz
120
150
160
140
120
8
10
12
14
FREQUENCY kHz
16
18
150
20
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28
15
0.32 (8.20)
0.29 (7.40)
0.22 (5.60)
0.20 (5.00)
1
0.079 (2.0)
MAX
0.002
(0.05)
MIN
14
PIN 1
0.026
(0.65)
BSC
0.073 (1.85)
0.065 (1.65)
0.015 (0.38)
SEATING
0.009 (0.22)
PLANE
12
0.01 (0.25)
0.004 (0.09)
8
0
0.037 (0.95)
0.022 (0.55)
PRINTED IN U.S.A.
MAGNITUDE RESPONSE dB
20
C36942.54/00 (rev. A)
10
20
10
50
10
dBr B
REV. A