DEPARTMENT OF ELECTRONICS

AND COMMUNICATION
ENGINEERING

DIGITAL COMMUNICATION
LABORATORY MANUAL (08L710)

PSG COLLEGE OF TECHNOLOGY,

COIMBATORE 641 004

1. STUDY OF SCRAMBLERS AND
DESCRAMBLERS

AIM:
To study the concept of scramblers and descramblers and
implement them using hardware and software tool.
SOFTWARE USED:
A system loaded with MATLAB.
THEORY:
SCRAMBLER:
In general a scrambler tends to make more random by removing
long strings of 0s and 1.Scrambling can be thought of helpful tool in
timing extraction by removing long strings of 0s in binary tool. This is
mainly used to prevent unauthorized access to data and is optimized
for that purpose.
Scramblers consist of a feedback shift register and the matching
descrambler has a feed- forward register. Each stage stores a bit and
delays it by one unit .Consider a sequence T to the scrambler then
S^

T^

Where D represents delay operation

T=T
T is delayed by n units

.The symbol ^ indicates XOR/modulo 2 sum .Recall that Xor of any

3
5
sequence with itself gives 0. Adding ( D ^ D T

the equation we get

S = T^( D
= [1^( D

^ D
^ D

)T
)]T

to both sides of

S = [1^ F]T

where F= D

D
^ D 5

DESCRAMBLER:
To design descrambler at receiver we start with T, sequence
received at the scrambler from equation it follows that
S = [1^ F]T
3
5
S = T^( D ^ D )T

This is the equation where we generate the input sequences from the
received sequence T is readily implemented by descrambler. A single
detection error in reeived sequence T will affect the output bits in R
.Hence scrambling has disadvantages of causing multiple error for
single received bit error.

CIRCUIT DIAGRAM

FIG 1.1. SCRAMBLER

FIG 1.2. DESCRAMBLER

TABLE 1.1 SCRAMBLER

I/P

Q1

Q2

Q3

Q4

Q5

Q3

Q4

Q5

TABLE 1.2 DESCRAMBLER

T

Q1

PROCEDURE:

Q2

The circuit connections are given as shown in the figure 1.1 for
scrambler.
The flip-flop outputs are cleared by by setting FF (CLR).
Then for a given sequence of inputs the states of the flip-flop are
checked in accordance with the table and the output is verified.
The same procedure is repeated in implementation of
descrambler.

RESULT:
Thus scramblers and descramblers are studied and implemented
using hardware and software.

2. DESIGN AND IMPLEMENTATION OF LINEAR BLOCK

CODER AND DECODER

AIM:
To design and implement linear block codes and decode using
hardware and software.
COMPONENT:
IC 74LS138
IC 7404
IC 7486
Bread board
Trainer kit
Power supply
Wires
THEORY
CODER

A coder word consists of ndigits and the dataword consists of k

digits. They are n tuple. We shall use row vector to represent these
words.
C=(c1,c2,c3,..Cn)

d=(d1,d2,d3,dn)

For a general class of LBC, all the n digits of codeword are formed by
linear combination of data word.
A special call where the first k digits of the code word is same as the
data and the rest k-n digits are linear combination of the data word ie.,
called systematic code. The last k-n digits are parity erect digits.
The k*n matrix is called as the generator. It has identity parity check
matrix. All the elements are either 0 or 1.the codeword can be
expressed as
e=dG
Thus knowing the data we can calculate the check digits.
FIGURE 2.1 ENCODER CIRCUIT

TABLE 2.1 ENCODER

d1

d2

d3

c1

c2

c3

c4

c5

c6

DECODING
From the coding equations Im is the identity matrix of order m. Let the
received word be R. due to channel noise it differs from C. The
hamming distance between R and C is the number of ones in e. But
because of possible channel errors RTH is usually a non zero value
indicating the occurrence of error. The non zero vector is called
syndrome defined as
S=RTH
The detector uses s to detect and correct errors.

FIGURE 2.2 DECODER CIRCUIT

TABLE 2.2 DECODER

RECIEVED BITS
SYNDROME
r1

r2

r3

r4

r5

r6

s1

s2

s3

RESULT
Thus linear block coder and decoder is implemented using software.

3. DESIGN AND TESTING OF CYCLIC CODER AND

DECODER

AIM
To design and implement cyclic coder and decoder using hardware and
software tool.

APPARATUS REQUIRED
IC 7486
IC 7474
IC7408
IC 7432
bread board, trainer kit, wires.

THEORY
A code c is cyclic code if
1. c is a linear code.
2. cyclic property is satisfied.
In a systematic code the first k digits are data and the last n-k digits
are check bits. The codeword c(x) is corresponding to the daya
polynomial d(x) is given by
C(x)=xn-k d(x)+p(x).
Where p(x) is the remainder by dividing xn-k d(x) by g(x).

FIGURE 3.1 CYCLIC CODER

TABLE 3.1 ENCODER

d1

d2

d3

c1

c2

c3

c4

c5

c6

DECODER
Every valid code polynomial is a multiple of p(x).if an error during
transmission, the received polynomial r(x) will be a multiple of g(x).
FIGURE 3.2 CYCLIC DECODER

TABLE 3.2 SYNDROME GENERATOR

ERROR BITS
SYNDROME
e1

e2

e3

e4

e5

e6

s1

s2

s3

RESULT:
Thus the cyclic coder was implemented using software tools.

4. Design and Implementation of Convolution Coder

and Decoder
AIM
To design and implement convolution coder and decoder using
hardware and software tools.
APPARATUS REQUIRED

IC 7486
IC 7474
Bread board.

SOFTWARE
A system loaded with MATLAB 7.0.1.
THEORY
A convolution coder operates on the incoming message
continuously in a serial manner. The encoder of a binary convolution

coder with rate 1/n measured in bits/symbol may be viewed as finite

state machine that has m-state shift registers with prescribed
connections to n-modulo 2-adder and a multiplier that serializes the
output of the adder.

n modulo 2
adder

An 1 bit sequence produces a coded output sequence of length,

n(L+M). The code rate is
r = L/n(L+M) bits/symbol.
Let the response g(0), g(1),.. g(m) be the input impulse response
for the input top-adder output path. The sequence [g 0(z), g1(z),.. gm(z)]
denotes the impulse response of the bottom adder output path. The
impulse responses are called generator sequences.
The encoder generates the output sequences by convolving the
message sequence with the impulse response of the input to adder
output and input bottom adder output path
{xi} = {x0(1), x0(2), x1(1), x2(2), ...}
For a convolution coder the output depends on present and previous
input bits
M Number of stages of shift registers.
L Number of bits at a given line.
N Number of bits which are encoded.
The constraint length of convolution coder is expressed in terms
of number of bit shifts over which a single message can influence the
encoded output.
For the last bits from Flip-flop, (k-1) zeros are added and given as
inputs.

DECODING
A viterbi algorithm is used for decoding the convolution code.
The input to the algorithm is the reason for preferring the trellis over
the tree is the number of nodes at any level of the trellis does not
continue to grow as the number of incoming message increases being
the constraint length.

The algorithm operates by computing a metric for every possible

path in trellis. The metric is hamming distance between coded and
received sequence. The path retained by algorithm is called survivor.
The viterbi algorithm is a maximum likelihood decider which is
optimum for a white gaussian noise channel. For a k-bit message
sequence and an encoder of memory M, the survivor matrix of paths
has to be found.
CIRCUIT DIAGRAM

TABLE:
ENCODING
Table:
CLK

I/P

S1

S2

S3

V1

V2

PROCEDURE

The input data is obtained.

Enter the generator polynomial.
Convolve generator with input.
The codeword is formed from convolved outputs.
The received error code is entered.
All possible paths in the trellis is traced.
All possible receiver code is generated.
The one that closely matches is the received code.

RESULT
Thus the convolution coder and decoder is done using software
and hardware tools.

5. DESIGN AND IMPLEMENTATION OF DELTA SIGMA

MODULATOR
AIM:
To design a delta sigma modulator using SIMULINK.

COMPONENTS:
Delta sigma modulator kit
CRO
Power supply
A system loaded with Simulink.

THEORY:
Sample correlation used in DPCM is exploited in Delta sigma
modulation by over sampling at a rate greater than Nyquist rate. This
increases between adjacent samples which results in small prediction
error that can be encoded using one bit. The error can be a one bit
DPCM. Single bit error is typically a

one bit DPCM. m[k]-

mq

k[ ].

FIGURE 5.1 DELTA SIGMAMODULATION

FIGURE 5.2 SIMPLIFIED VERSION OF DELTA SIGMA MODULATION

The Quantizer input in the conventional form of delta modulation

may be viewed as an approximation of the derivative of incoming
message signal. This leads to accumulation of noise in the
demodulated signal. This is overcome by integration (LPF), prior to
delta modulation. A delta modulation that incorporates integration

prior to modulation is delta sigma modulator. In delta modulation, we

use first order predictor to give a time delay.
mq [k ]=

m[k-1]+ d q [k ]

mq [k1]=

mq [k-2]+ d q [k-1]

Therefore,

mq [k ]=

Assuming

mq [0]

mq

dq

[k-1]+

Thus the receiver is just an adder. If

d q [k ]

[k-2]+

dq

[k-1]

=0

mq [k ]= d q [m]
0

is the output represented

by pulse, then the receiver is realized as an integrator.

FIGURE 5.3 DEMODULATING FILTER

FIGURE 5.4 DELTA SIGMA MODULATOR (KIT DIAGRAM)

FIGURE 5.5 DELTA MODULATOR (KIT DIAGRAM)

PROCEDURE:

The block diagram of the delta sigma modulator is connected

in Simulink.
The message is set to 100 Hz.
The pulse generates is set to 400 Hz.
The Output is observed.
Demodulation is done by passing through an analog filter.
The output is viewed using scope.

HARDWARE:

Set up the circuit on the module.

Leave the input socket of differential amplifier unconnected
and clock frequency to min.
Connect the output to CRO.
Set Y1 sensitivity to 5V/division, Y2 to 100 mV/div and time
base is 50s/div.
Set the signal generator to sine 500 Hz and connect the
output to the -ve input of the differential amplifier.
Change the amplitude of the sine signal, at the same time
reducing Y2 sensitivity.
Observe the signal at Integrator 2, which is the received
signal.

Delta modulation is unsuitable for high frequency transmission

because of rate limiting. Delta sigma Modulation on the other hand, is
capable of handling high frequency and it does preserve the dc level of
signal.

RESULT:
Thus delta sigma modulation is done with the help of Simulink and
Hardware.

6. DESIGN AND IMPLEMENTATION OF

DIFFERENTIAL PULSE CODE MODULATION

AIM:
To design and implement differential pulse code modulation using
SIMULINK, MATLAB.

APPARATUS REQUIRED:
A system loaded with MATLAB.

THEORY:
In ordinary PCM no of bits are transmitted corresponding to the
level of signal. But in DPCM the difference between the present and
previous value is transmitted. There are basically two types of DPCM
.The first one is transmitting the difference
d[k]=m[k]-m[k-1];
Instead of m[k],d[k] is transmitted
m[k]=d[k]+m[k+1]
The chief advantage is the reduction in the no of bits transmitted and
the quantization error.
Type 2 is the estimate m[k] from previous sample

d[k]=m[k]- m [k ]

and m[k]=d[k]+

m [k ]

at the

receiver end.
Here prediction error is smaller using taylor series.

m[k+1]=m[k]+ t s m [t ]

Simplifying we get, m[k+1]=im[k]-m[k-1]

Thus it is possible to estimate the value of m[k+1].For future
from previous values for prediction to be accurate the co-efficient of
prediction should be as close as possible.
m [t ] = a1m[k-1]+a2mk[k-2]+......
For the prediction to be accurate co-efficient a1,a2... should be
as close as possible. Ie., closely correlated Minimum mean square error
filter is used. For best prediction usually linear predictor of different
order is used to increase the accuracy of prediction.
FIGURE 6.1 DPCM TRANSMITTER

FIGURE 6.2 DPCM RECEIVER

PROCEDURE:

The input sine wave at a particular sampling rate is obtained.

It is then quantized.
Using predictor the value of the next sample is estimated.
It is then plotted using scope.
The analog filter design block is used to demodulate the signal.
The signal is also plotted using scope.

RESULT:
Thus differential pulse code modulation is implemented using
SIMULINK.

7. Design and Implementation of Adaptive Delta

Modulation

AIM:
To design and implement ADM modulation using MATLAB
SOFTWARE USED:
A system loaded with MATLAB
THEORY:
The delta modulation considers the sample values of present and the
one immediately preceding it. So if the value at present is greater, 1
is sent or else 0 is sent. The step size is constant. There is its greatest
disadvantage. When the sine wave steep or less varying the slope is
less, the error is high. So we go for adaptive delta modulation.
Here the size of the step is varied in accordance the input.
When the slope is steep the step size is increased. When the slope is
less, the width is increased. So the slope overload and granular noise
seen in delta modulation is avoided.
The following steps are to be considered while performing ADM
d min

d max

The step size is between

d min

and

d max

d max

is to control slope overload.

d min

is to control ideal noise condition( to control channel noise)

(nTs)=g(nTs) (nTs-Ts)

Where g(nTs) depends on present binary output and m previous bits.

(i.e) b(nTs),
b(nTs-Ts)......., (nTs-mTs).
g(nTs)=K

if b(nTs)= b(nTs-Ts)

g(nTs)= K

if b(nTs) b(nTs-Ts)

value of K depends on application. K=1.5 is optimum for speech and

image.

ADM MODULE-Block Diagram:

Input Stage:

Output stage:

I/P

Demodulate
d signal

PROCEDURE
The input sine wave frequency and step size are got from user.

By comparing with the previous value if the step size is greater than
a threshold value, the result is scaled accordingly.
Else the step size is added if the present value is greater than
previous and vice versa. The modulated signal is plotted.
In demodulator using the value of the size,the sine wave is got
back.
RESULT
Thus adaptive delta modulation scheme is performed using MATLAB.

8. STUDY OF LINE CODES

AIM:
To implement the various types of line codes such as unipolar,
bipolar and observe the power spectral densities of various line codes.

APPARATUS REQUIRED:
A PC loaded with MATLAB.

THEORY:
The output of the multiplexer is coded into electrical pulses or
waveforms for transmission .This is called Line coding. In ON-OFF code
1-p(t),
0-no pulse
In POLAR code
1-p(t),
0-(-p(t))
In BIPOLAR code
1-Alternate p(t) and p(t),

0-no pulse
The bipolar code is able to detect errors easily because the received
pulses will violate the bipolar rule when an error occurs.
When Full width pulses are used to code, the pulse amplitude is
held constant at a particular value .This is called as NRZ .When half
width pulse is used it is RZ scheme.

POWER SPECTRAL DENSITY:

I) UNRZ SIGNAL:
A2T b
2
sinc (F T b )[ 1+
S(F)=
4

1
T b (F)]

II) PNRZ SIGNAL:

2
2
T
S(F)= A T b sinc (F b )

III) URZ SIGNAL:

F Tb
A2T b
2
S(F)= 16 sinc ( 2 )[ 1+

1
n
( F )

T b n=
Tb

IV) BIPOLAR RZ SIGNAL:

2
F Tb
A Tb
2
sinc2 ( F T b )
sinc
S(F)=
(
2
4

V) MANCHESTER CODING:
2
2
S(F)= A T b sinc (

F Tb
F T b
sinc 2 (
)
)
2
2

PROCEDURE:

The input is obtained from user.

The power spectral densities are viewed with help of function
spectrum.

The codes for URZ, UNRZ, BRZ, BNRZ, and MANCHESTER are
written in MATLAB.
The output and power spectral density of each type is plotted.

RESULT:
Thus different line coding schemes are implemented using
MATLAB and their PSDs are plotted.

9. Study of Spread Spectrum Systems

AIM
The aim of the experiment is to study spread spectrum technologies.

SOFTWARE USED
A system loaded with MATLAB.

THEORY
The spread spectrum uses multiple access technique to use bandwidth
efficiently to avoid intentional and unintentional interferences. Spread
of spectrum is a technique whereby a modulated waveform is spread in
such a way as to generate expanded bandwidth signals that do not
interfere with other signals.
BPSK or OPSK modulation can be used for spread spectrum.
Spreading after modulation is same as spreading using PN-sequence
generator.
FHSS- Frequency Hopped Spread Spectrum has implementation
on concept familiar to that of DHSS. The hopping rate is higher than bit
rate, then it is Fast FHSS. If it is slower, then it is called Slow FHSS
where there are several bits per frequency hop.

DSSS SYSTEM

DSSS TRANSMITTER

DSSS RECEIVER

FHSS
TRANSMITTER

FHSS RECEIVER

PROCEDURE
Obtain the input binary sequence.
Apply DSSS to input for two different chip rates.
Plot the power spectral density and compare results.
Apply FHSS to input for two different hop sets.
Plot the power spectral density and compare results.

RESULT
Thus various spread spectrum technique is implemented using
MATLAB.

10. Design and Implementation of Tapped Delay

Equalizer
AIM
To design and implement tapped delay equalizer using MATLAB.
SOFTWARE
PC loaded with MATLAB
THEORY
Due to the occurrence of some amount of residual inter symbol
interference in real time system, because of incomplete knowledge of
channel characteristics and imperfect filer design. It is necessary to
have an equalizer which is an adjustable filter to compensate for
distortion.

Equalizer construction circuit

Equalizing filter is most often inserted between receiving filter

and A-D converters.

A tapped line equalizer is a linear equalizer.

The impulse response is

N

l(t) =

k (tkT )

k=N

Suppose if the equalizer is connected in cascade with a linear system

impulse response c(t)
p(t) = c(t)*h(t)
N

k c (t kT )

k=N

Evaluation of discrete sample time t=nT,

N

p(nT) =

k c [(mk )T ]

k=N

To eliminate ISI we must satisfy Nyquist criterion for distortion less

transmission
N

p(nT) =

k c [(mk )T ]

k=N

{1,0,n=0
n 0

But since there are only (2N+1) adjustable co-efficients the ideal
condition can be approximated as,
p(nT) =

Denoting Cnt as Cn in matrix form,

{1,0,n=0
n 0

This type of tapped delay equalizer is zero forming equalizer. Such an

equalizer is optimum in the sense that it minimizes the peak duration
(ISI).
PROCEDURE

The
The
The
The

code for implementation of tapped delay equalizer is written.

order of tap is given.
response before and after equalization is displayed.
value of tap co-efficient is displayed.

RESULT
Thus tapped delay equalizer is done using MATLAB.
C0
C1

C-1 C-2 ... C-2N

C0 C-1 ... C-

W-N
W-

(2N+1)

N+1

.
. . ... .
.
. . ... .
CN CN-1CN-2... C-N
.
. . ... .
.
. . ... .
C2N C2N-1 C2N-2 ...
C0

.
.
W0
.
.

0
0
.
.
1
.
.
0