EE

ESE-2016 : TEST SERIES

ONLINE

UPSC Engineering Services Examination

MODE

Subjectwise Test No. 8 (Conventional) : Analog Circuits

EXPLANATIONS
1.

(a)
Pin diagram of the 555 Timer
The below figure shows the schematic of 555 integrated timer. The device may be connected to carry out
either astable or monostable operation.
GND

Trigger

+ VCC

Discharge

555
Output

Threshod

Reset

Control

Pin Description :
Pin-1: Gr
ound T
er
minal
Ter
erminal
Ground
This pin represents ground. All voltages are measured with respect to this terminal.
Pin-2: T
rigger
Trigger
This pin is an inverting input to a comparator that is responsible for transition of flip-flop from set to reset.
The external trigger pulse is applied to this terminal. The output voltage of the timer depends on the
amplitude of the trigger pulse.
Pin-3: Output
A load may be connected between this pin and the ground pin.
Pin-4: Reset
To reset or disable the timer a negative pulse is applied to this pin due to which it is referred as reset
terminal. When this pin is not to be used for reset purpose, it should be connected to +Vcc to avoid any
possibility of false triggering.

ESE Online Test Series 2016 : Conventional Paper

Pin-5: Contr
ol V
oltage
Control
Voltage
When an external voltage is applied to control voltage, both trigger and threshold voltages vary, so that
output voltage pulse width changes.
Pin-6: Thr
eshold V
oltage
Threshold
Voltage
This is the non inverting input terminal of comparator-1. When the voltage at this terminal exceeds the
control voltage 2/3 VCC, the output of comparator-1 goes high, as a result the timer output goes low.
Pin-7: Discharge
This pin is connected to the collector terminal of the discharge transistor Q1. During operation, when the
timer output is low, Q1 is saturated and it short circuits the capacitor connected across it externally. When
the timer output is high, Q1 is cut-off.
Pin-8: +VCC Supply
A supply voltage of +5 V to +18 V is applied to this terminal with respect to ground (pin-1).

For astable multivibrator using 555 timer

(i) Output frequency

f=

D=

(ii) Duty cycle

0.693 (R A + 2RB ) C

1
6

0.693(0.1 10 )(4.6 + 10) 103

= 988.36 Hz

1 + 2.3 / 10
1 + RB / R A
100% = 84.24%
100% =
2 2.3

(1 + 2RB / R A )
1 +

10

(iii) Current sourcing

Pavg

1
=
T1 + T2

T1

VCC
VCC
T1
RL dt = T1 + T2 RL
0

12
= Duty cycle
1 103

12
= 0.8424
1000

= 0.121 mW

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna

EOTEE16

Electrical Engineering Analog Circuits

8
1.

(b)
RS
+

+
IS

1 mA

VS = 20 V 20%

IL
RL

VL = 6.8 V

For Zener regulator

IZ min = 1 mA
This current through Zener should flow even when the load draws the maximum current
i.e.
IL max = 30 mA + 50%
45 mA
Therefore
IS max = IZ max + IL max
=10 + 45 = 55 mA
Therefore
IS min = IZ min + IL min
IS min = 1 mA + 15 mA = 16 mA
The value of the source resistance

RS min =

VS min VL
IS max

Here

VS min = 20 V 20% = 16 V

RS min =

RS max =

16 6.8 9.2
=
= 167
55 mA
55
VS max VL
IS min

Here

VS max = 20 V + 20% = 24 V

RS max =

24 6.8
= 1075
16 mA

The load resistance varies between minimum and maximum current.

RL max =

6.8
15 103

= 453

6.8

= 151
45 103
hence the value for RS varies between 167 to 1075 and RL is varies between 151 to 453 .

and

EOTEE16

RL min =

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna

ESE Online Test Series 2016 : Conventional Paper

2.

(a)
When switch S closed
iin
5V

40 k VB
VA

Vout

+
3V

Vout = VA = VB = +3 V
When switch S opened

...(i)

iin
5V
40 k

VB
VA

C = 0.2 F

Vout

3V

By virtual ground concept

VA = VB = 3 V

Vout VB =

Vout =

Also

iin =

...(ii)

1
i dt
C 0 in
t

1
i dt + 3
C 0 in

Vin VB
53
=
= 0.05 mA
40 k 40 k

...(iii)

...(iv)

Substituting values in equation (iii), we get

Vout =

1
(0.05 103 ) dt + 3
0.2 106 0

Vout = (250 t + 3) V
for t = 50 msec
Vout(50 ms) = (250 50 103 + 3) V = 9.5 V
Hence the sketch for Vout versus t is

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna

...(v)
...(vi)

EOTEE16

Electrical Engineering Analog Circuits

10

Vout
3V

50 msec

9.5 V

2.

(b)

S=

Stability factor:

RB =

RB + RE
R
RE + B
+1
R1 R2
90 10 900
=
=
= 9 k
R1 + R2 90 + 10 100

9+1
10
=
= 8.613
9
1.161
1+
56
Operating Point: This may be found from the forward characteristics by writing the bias equation. As
the characteristics are not given we proceed as follows.

S=

VCC

I
I
IB = C = C
55

RC

Applying KVL to the BE loop

V = IB RB + VBE + (IB + IC) RE

V = VCC

RB

R2
22.5 10
=
= 2.25 V
R1 + R2
100

2.25 = IB (9 k) + 0.6 + 56 IB 1 k

IB
V

Taking IB in mA,

VBE
RE

65 IB = 2.25 0.6 = 1.65

IB =

The Q-point is

EOTEE16

IC =
VCE =
=
(VCEQ, ICQ) =

1.65
= 0.0254 mA = 25.4 A
65
55 25.4 = 1.397 mA
22.5 IC RC (IB + IC) RE
22.5 1.397 5.6 1.4224 = 13.254 V
(13.254 V, 1.397 mA)

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna

11

ESE Online Test Series 2016 : Conventional Paper

3.

(a)
The given circuit is a triangular wave generator.

The triangular wave generator consists of a comparator A1 and an integrator A2. The comparator A1
compares the voltage at point P continuously with the inverting input that is at 0V. When the voltage at
P goes slightly below or above 0V, the output of A1 is at the negative or positive saturation level,
respectively.
Integrator A2
R1

A1
+

A2

V0

R2
P

R3

Let us set the output of A1 at positive saturation +Vsat(+VCC). This +Vsat is an input of the integrator A2.
The output of A2, therefore, will be a negative going ramp. When the negative going ramp attains a
certain value VRamp, point P is slightly below 0V; hence the output of A1 will now stop going negatively
and will begin to go positively. The output of A2 will continue to increase until it reaches +VRamp. At this
time, the point P is slightly above 0V; therefore, the output of A1 is switched back to the positive
saturation level +Vsat. The sequence then repeats. The output wave is shown in the figure below:

From the figure, when the voltage at point P is 0V, then

VRam p
R3

or

VRamp

+Vsat
=
R2
R3
=
(+Vsat)
R2

Similarly,

Voltage
+Vsat

V0

+VRamp

t
VRamp

+VRamp =

R3
(Vsat)
R2

Vsat
T

Peak-to-peak output amplitude

V0(pp) = +VRamp (VRamp)

V0(pp) =

2R3
(Vsat)
R2

V0(pp) =

1 T /2
(Vsat )dt
R1C 0

From the integrator equation,

V T
= sat
R1C 2
Hence,

T
2

V0 (pp)
(R1C)
Vsat

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna

EOTEE16

Electrical Engineering Analog Circuits

12

V (pp)
T = (2R1C) 0
Vsat

T =

4R1CR3
R2

f0 =

R2
1
=
4R1CR3
T

Frequency of oscillation is:

56 103
4 22 103 0.022 10 6 18 103

f0 = 1606.98 Hz
Frequency of oscillation can be changed by changing the component values
Let us change only R2 keeping other element values constant.

f0 =

f0
f0

10 103
1606.98

R2
R2
R2

56 103

R2 = 0.348 M
Thus, we can change the frequency of signal to 10kHz by making R2 = 0.348 M and other values as those
are.

3.

(b)
Amplifier gain,

A = 100180 = 100

Upper cutoff frequency,

fH = 100 kHz

Lower cutoff frequency,

fL = 1 kHz

Negative feedback,

= 0.1

Closed loop gain,

Af =

A
100
100
=
=
1 + A 1 + (100) (0.1)
11

Af

100
11

fL

fL
1000
=
Hz =90.90 Hz
1 + A
11

fH

= fH (1 + A ) = 100(11) kHz = 1.1 MHz

Lower cutoff frequency,

Upper cutoff frequency,

feedback

dB of feedback

=
= 20 log10 = 20 log10 (0.1)

The statement (1) and (3) are correct

EOTEE16

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna

ESE Online Test Series 2016 : Conventional Paper

4.

13

(a)
M1 and M2 both are in saturation therefore

ID1 = ID 2
Kn1 (VGS1 VT )2 = Kn2 (VGS 2 VT )2
K1(VGS1 VT )2 = K 2 (VGS 2 VT )2

K1(Vin Vo VT )2 = K2(VB + Vss VT )2

(V in Vo VT )2 =

Vin Vo VT =

K2
(VB + Vss VT )2
K1

K2
(V + V V )
K1 B ss T

Vo = Vin VT

K2
K2
K2
V
V +
V
K1 B
K1 ss
K1 T

K2

K2
Vo = Vin + VT K 1 K (VB + Vss )

1
1
The given circuit is common drain MOS amplifier with active load.
+VDD
Vin

M1

Vout
r02
VSS

A.C. equivalent circuit is given below:

G1
Vi

gm1 vgs1

r01
D1

Voltage gain Av =

+ D2

S1
r02

Vo
S2

Vo
= gm1(r01 || r02 )
Vi

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna

EOTEE16

Electrical Engineering Analog Circuits

14
4.

(b)
+6 V

I1

I2

I3

10 k
I0

1.4 k

Ro

R1

300

R2

400

R3

500

6 V

The base currents are neglected i.e. of the transistors are very high.
Applying KVL in Ist transistor
6 Io(10 k) 0.7 1.4 k Io + 6 = 0
11.3 = Io(10 + 1.4)k
11.3
mA
11.4
Io 1 mA
Since all transistors are coupled to each other, therefore emitter voltages are same in all the transistors as
they are connected in parallel.

Io =

VR0 = 1.4 k 1 mA
VR0 = 1.4 V
VR1 = 1.4 V = I1 300
I1 =

1.4
= 4.67 mA
300

VR2 = 1.4 V = I2 400

I2 =

1.4
= 3.5 mA
400

VR3 = 1.4 V = I2 500

I2 =

EOTEE16

1.4
= 2.8 mA
500

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna

ESE Online Test Series 2016 : Conventional Paper

5.

15

(a)
The op-amp is ideal so i1 = i2 = 0
So if we observe the circuit, it works as a buffer

VL = VS

so,

isat = 2 mA

but,
so i0 < 2mA
VL
so R < 2mA
L
VS
< 2mA
RL

( VS

< 2mA .R L

This is the condition on magnitude of VS to get VL = VS

Another condition is slew rate of op-amp i.e 5 105 V/s
Slew rate = max
so,

dVout
dt

{ }
dVout
dt

< 5 105 V/s

dVS
< 5 105 V/s
dt

So
(i)
(ii)

VL = VS with two conditions

dVS
< 5 105 V/s
dt

VS

< 2 103 RL V

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna

EOTEE16

Electrical Engineering Analog Circuits

16
5.

10 V

(b)
Now,

VDS = 2 VGS

VDS > VGS VT

ID

thus the MOS will remain in saturation region.

10 M

k
2
Now, ID = (VGS VT ) for saturation region
2

VGS

VDS
=
and VDS = 10 IDRD
2

Let

RD = 1 k

ID =

VD

10 M

k
2
0.5 103
10 (1k ) ID + 1) =
(
(10 1k ID + 1)2
2
2

4k I D = (11 (1k) I D ) 2
4k I D = 121 + (1k)2 I D2 22 k I D
(1k) 2 I D 2 (26 k) I D + 121 = 0
ID = 0.0199
ID = 6.07 103
Thus,

ID = 19.9 mA is not possible thus

ID = 6.07 mA

EOTEE16

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna