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1. General description
The TDA8954 is a stereo or mono high-efficiency Class D audio power amplifier in a
single IC featuring low power dissipation. It is designed to deliver up to 2 210 W into a
4 load in a stereo Single-Ended (SE) application, or 1 420 W into an 8 load in a
mono Bridge-Tied Load (BTL) application.
It combines the benefits of Class D efficiency (93 % into a 4 load) with audiophile
sound quality comparable to that associated with Class AB amplification.
The amplifier operates over a wide supply voltage range from 12.5 V to 42.5 V and
features low quiescent current consumption.
The TDA8954 is supplied with two diagnostic pins for monitoring the status of Thermal
Fold Back (TFB), Over Current Protection (OCP) and other protection circuits.
2. Features
High output power in typical applications:
SE 2 210 W, RL = 4 (VDD = 41 V; VSS = 41 V)
SE 2 235 W, RL = 3 (VDD = 39 V; VSS = 39 V)
SE 2 150 W, RL = 6 (VDD = 41 V; VSS = 41 V)
BTL 1 420 W, RL = 8 (VDD = 41 V; VSS = 41 V)
Symmetrical operating supply voltage range from 12.5 V to 42.5 V
Stereo full differential inputs, can be used as stereo SE or mono BTL amplifier
Low noise
Smooth pop noise-free start-up and switch off
2-pin diagnostics for protection circuits
Fixed frequency internal or external clock
High efficiency 93 %
Zero dead time switching
Low quiescent current
Advanced protection strategy: voltage protection and output current limiting
Thermal FoldBack (TFB) with disable functionality
Fixed gain of 30 dB in SE and 36 dB in BTL applications
Fully short-circuit proof across load
BD modulation in BTL configuration
Clock protection
TDA8954
NXP Semiconductors
3. Applications
DVD
Mini and micro receiver
Subwoofers
Symbol Parameter
Conditions
Min
Typ
Max
Unit
41
42.5
General
VDD
Operating mode
[1]
12.5
VSS
Operating mode
[2]
12.5 41
42.5 V
Vth(ovp)
overvoltage protection
threshold voltage
85
90
IDD(tot)
50
60
mA
65
75
mA
210
150
420
total negative supply current the sum of the currents through pins VSSA, VSSP1
and VSSP2
Operating mode; no load; no filter; no RC-snubber
network connected;
output power
THD + N = 10 %; RL = 4 ; VDD = 41 V;
VSS = 41 V
[3]
THD + N = 10 %; RL = 4 ; VDD = 35 V;
VSS = 35 V
Mono bridge-tied load configuration
Po
output power
[1]
[2]
[3]
Output power is measured indirectly; based on RDSon measurement; see Section 14.3.
[3]
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDA8954J
DBS23P
plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1
TDA8954TH
HSOP24
TDA8954_1
SOT566-3
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6. Block diagram
VDDA
DIAG1
3 (20)
IN1M
IN1P
OSCREF
OSC
MODE
SGND
10 (4)
VDDP2
STABI PROT
18 (12)
13 (7)
23 (16)
IN2M
14 (8)
15 (9)
BOOT1
9 (3)
PWM
MODULATOR
INPUT
STAGE
8 (2)
11 (5)
SWITCH1
CONTROL
AND
HANDSHAKE
mute
DRIVER
HIGH
16 (10)
OUT1
DRIVER
LOW
STABI
VSSP1
7 (1)
6 (23)
OSCILLATOR
MANAGER
MODE
TEMPERATURE SENSOR
CURRENT PROTECTION
VOLTAGE PROTECTION
TDA8954TH
(TDA8954J)
VDDP2
22 (15)
BOOT2
2 (19)
mute
IN2P
VDDP1
CONTROL
SWITCH2
AND
HANDSHAKE
5 (22)
4 (21)
INPUT
STAGE
1 (18)
VSSA
PWM
MODULATOR
12 (6)
DIAG2
24 (-)
VSSA
19 (17)
n.c.
DRIVER
HIGH
21 (14)
OUT2
DRIVER
LOW
17 (11)
VSSP1
20 (13)
VSSP2
010aaa556
Fig 1.
Block diagram
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7. Pinning information
7.1 Pinning
OSC
IN1P
IN1M
DIAG1
OSCREF
DIAG2
PROT
VDDP1
BOOT1
OUT1 10
VSSP1 11
VSSA 24
VSSA
STABI 12
VDDP2 23
SGND
VSSP2 13
BOOT2 22
VDDA
OUT2 21
IN2M
BOOT2 15
VSSP2 20
IN2P
VDDP2 16
n.c. 19
MODE
OSC
VSSA 18
VSSP1 17
IN1P
SGND 19
OUT1 16
IN1M
VDDA 20
STABI 18
TDA8954TH
BOOT1 15
10 DIAG1
VDDP1 14
11 OSCREF
OUT2 14
n.c. 17
IN2M 21
IN2P 22
12 DIAG2
PROT 13
TDA8954J
MODE 23
010aaa557
Fig 2.
010aaa558
Fig 3.
TDA8954_1
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Pin description
Pin
Description
TDA8954TH
TDA8954J
VSSA
18
SGND
19
signal ground
VDDA
20
IN2M
21
IN2P
22
MODE
23
OSC
IN1P
IN1M
DIAG1
10
OSCREF
11
DIAG2
12
PROT
13
VDDP1
14
BOOT1
15
OUT1
16
10
VSSP1
17
11
STABI
18
12
n.c.
19
17
not connected
VSSP2
20
13
OUT2
21
14
BOOT2
22
15
VDDP2
23
16
VSSA
24
8. Functional description
8.1 General
The TDA8954 is a two-channel audio power amplifier that uses Class D technology.
For each channel, the audio input signal is converted into a digital Pulse Width Modulation
(PWM) signal using an analog input stage and a PWM modulator; see Figure 1. To drive
the output power transistors, the digital PWM signal is fed to a control and handshake
block and to high- and low-side driver circuits. This level-shifts the low-power digital PWM
signal from a logic level to a high-power PWM signal switching between the main supply
lines.
A second-order low-pass filter converts the PWM signal to an analog audio signal that can
be used to drive a loudspeaker.
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The TDA8954 single-chip Class D amplifier contains high-power switches, drivers, timing
and handshaking between the power switches, along with some control logic. To ensure
maximum system robustness, an advanced protection strategy has been implemented to
provide overvoltage, overtemperature and overcurrent protection.
Each of the two audio channels contains a PWM modulator, an analog feedback loop and
a differential input stage. The TDA8954 also contains circuits common to both channels
such as the oscillator, all reference sources, the mode interface and a digital timing
manager.
The two independent amplifier channels feature high output power, high efficiency, low
distortion and low quiescent currents. They can be connected in the following
configurations:
Operating mode: the amplifier is fully operational, de-muted and can deliver an output
signal
A slowly rising voltage should be applied (e.g. via an RC network) to pin MODE to ensure
pop noise-free start-up. The bias-current setting of the (VI converter) input stages is
related to the voltage on the MODE pin.
In Mute mode, the bias-current setting of the VI converters is zero (VI converters are
disabled). In Operating mode, the bias current is at a maximum. The time constant
required to apply the DC output offset voltage gradually between Mute and Operating
mode levels can be generated using an RC network connected to pin MODE. An example
of a circuit for driving the MODE pin, optimized for optimal pop noise performance, is
shown in Figure 4. If the capacitor was omitted, the very short switching time constant
could result in audible pop noises being generated at start-up (depending on the DC
output offset voltage and loudspeaker used).
+5 V
5.6 k
470
MODE
TDA8954
5.6 k
10 F
mute/
operating
S1
standby/
operating
S2
SGND
010aaa588
Fig 4.
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The smooth transition between Mute and Operating modes causes a gradual increase in
the DC offset output voltage, which becomes inaudible (no pop noise because the DC
offset voltage rises smoothly). An overview of the start-up timing is provided in Figure 5.
For proper switch-off, the MODE pin should be forced LOW at least 100 ms before the
supply lines (VDD and VSS) drop below 12.5 V.
audio output
(1)
modulated PWM
VMODE
50 %
duty cycle
operating
> 4.2 V
mute
0 V (SGND)
standby
> 350 ms
100 ms
time
50 ms
audio output
(1)
modulated PWM
VMODE
50 %
duty cycle
operating
> 4.2 V
mute
0 V (SGND)
standby
> 350 ms
100 ms
50 ms
time
001aah657
Fig 5.
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8.2 Diagnostics
The TDA8954 provides two diagnostic signals on pins DIAG1 and DIAG2. Both are
open-drain outputs that can be pulled up via a resistor (10 k recommended) to a
maximum of 5 V relative to the GND pin. The maximum input current on these pins is
1 mA.
Pin DIAG1 provides a TFB warning signal. Pin DIAG2 can be used to monitor the OCP
status and the protection status (whether one of the protection circuits has switched off the
amplifier).
Details of the timing of these signals can be found in Section 8.4.1.1 and Section 8.4.2;
see also Table 5.
010aaa596
500
fOSC
(kHz)
400
300
200
20
25
30
35
40
45
ROSC (k)
Fig 6.
If two or more Class D amplifiers are used in the same audio application, an external clock
circuit must be used to synchronize all amplifiers (see Section 14.4). This will ensure that
they operate at the same switching frequency, thus avoiding beat tones (if the switching
frequencies are different, audible interference known as beat tones can be generated).
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8.4 Protection
The following protection circuits are incorporated into the TDA8954:
Thermal protection:
Thermal FoldBack (TFB)
OverTemperature Protection (OTP)
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VLOAD
T
Tact(th_fold)
Tact(warn)th_fold
t
Fig 7.
010aaa561
TDA8954_1
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VPULL-UP
VDIAG1
30
Gain
[dB]
24
Thg(th_fold)
2
Tact(th_prot)
Tact(th_fold)
Trst(warn)th_fold
Tact(warn)th_fold
3
010aaa562
(1) Duty cycle of PWM output modulated according to the audio input signal.
(2) Duty cycle of PWM output reduced due to TFB.
(3) Amplifier is switched off due to OTP.
Fig 8.
Short-circuit impedance > Zth: the amplifier limits the maximum output current to IORM
but the amplifier does not shut down the PWM outputs. Effectively, this results in a
clipped output signal across the load (behavior very similar to voltage clipping).
Short-circuit impedance < Zth: the amplifier limits the maximum output current to IORM
and at the same time discharges the capacitor on pin PROT. When CPROT is fully
discharged, the amplifier shuts down completely and an internal timer is started.
The value of the protection capacitor (CPROT) connected to pin PROT can be between
10 pF and 220 pF (typically 47 pF). While OCP is activated, an internal current source is
enabled that will discharge CPROT.
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When OCP is activated, the active power transistor is turned off and the other power
transistor is turned on to reduce the current (CPROT is partially discharged). Normal
operation is resumed at the next switching cycle (CPROT is recharged). CPROT is partially
discharge each time OCP is activated during a switching cycle. If the fault condition that
caused OCP to be activated persists long enough to fully discharge CPROT, the amplifier
will switch off completely and a restart sequence will be initiated.
After a fixed period of 100 ms, the amplifier will attempt to switch on again, but will fail if
the output current still exceeds the OCP threshold. The amplifier will continue trying to
switch on every 100 ms. The average power dissipation will be low in this situation
because the duty cycle is short.
Switching the amplifier on and off in this way will generate unwanted audio holes. This
can be avoided by increasing the value of CPROT (up to 220 pF) to delay amplifier
switch-off. CPROT will also prevent the amplifier switching off due to transient
frequency-dependent impedance drops at the speakers.
The amplifier will switch on, and remain in Operating mode, once the overcurrent
condition has been removed. OCP ensures the TDA8954 amplifier is fully protected
against short-circuit conditions while avoiding audio holes.
Table 4.
Type
VDD/VSS (V)
TDA8954 +41/41
[1]
Short
(Zth = 1 )
20
10
yes[1]
yes[1]
yes[1]
1000
10
yes
no
no
20
15
yes[1]
yes[1]
yes[1]
1000
15
yes
no
no
1000
220
no
no
no
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IMAX
current
limiting
short
circuit
protection
IOUT
short to VDDP applied
t
Fig 9.
010aaa563
Current limiting
During the start-up sequence, when the TDA8954 is switching from Standby to Mute.
Start-up will be interrupted if a short-circuit is detected between one of the output
terminals and one of the supply pins. The TDA8954 will wait until the short-circuit to
the supply lines has been removed before resuming start-up. The short circuit will not
generate large currents because the short-circuit check is carried out before the
power stages are enabled.
When the amplifier is shut down completely because the OCP circuit has detected a
short circuit to one of the supply lines.
WP will be activated when the amplifier attempts to restart after 100 ms (see
Section 8.4.2). The amplifier will not start-up again until the short circuit to the supply
lines has been removed.
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Protection
name
Complete
shutdown
Restart
directly
Restart
after
100 ms
PROT pin
active
DIAG1 pin
active
DIAG2 pin
active
TFB[1]
Y[2]
OTP
OCP
Y[3]
N[3]
Y[3]
WP
N[4]
UVP
OVP
UBP
Y[5]
CP
[1]
[2]
[3]
The amplifier shuts down completely only if the short-circuit impedance is below the impedance threshold
(Zth; see Section 8.4.2). In all other cases, current limiting results in a clipped output signal.
[4]
Fault condition detected during any Standby-to-Mute transition or during a restart after OCP has been
activated (short-circuit to one of the supply lines).
[5]
Stereo operation: to avoid supply pumping effects and to minimize peak currents in
the power supply, the output stages should be configured in anti-phase. To avoid
acoustical phase differences, the speakers should also be connected in anti-phase.
Mono BTL operation: the inputs must be connected in anti-parallel. The output of one
channel is inverted and the speaker load is connected between the two outputs of the
TDA8954. In practice (because of the OCP threshold) the maximum output power in
the BTL configuration can be boosted to twice the maximum output power available in
the single-ended configuration.
The input configuration for a mono BTL application is illustrated in Figure 10.
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OUT1
IN1P
IN1M
Vin
SGND
IN2P
IN2M
OUT2
power stage
mbl466
Fig 10.
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9. Internal circuitry
Table 6.
Internal circuitry
Pin
Symbol
TDA8954TH
TDA8954J
Equivalent circuit[1]
OSC
VDD
150 A
7 (1)
VSS
11
010aaa589
OSCREF
2
VSS
11 (5)
010aaa590
10
DIAG1
12
DIAG2
10, 12
(4, 6)
SGND
010aaa591
13
PROT
50 A
current limiting
13 (7)
OCP
28 A
1.5 mA
VSS
010aaa592
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Table 6.
Pin
Symbol
TDA8954TH
TDA8954J
21
IN2M
22
IN2P
IN1P
IN1M
Equivalent circuit[1]
2 k
5, 8
(22, 2)
50 k
SGND
SGND
50 k
2 k
4, 9
(21, 3)
010aaa593
23
MODE
6 (23)
50 k
SGND
standby
gain (mute
on)
TFB on
VSS
010aaa594
18
VSSA
19
SGND
20
VDDA
14
VDDP1
15
BOOT1
16
10
OUT1
17
11
VSSP1
18
12
STABI
20
13
VSSP2
21
14
OUT2
22
15
BOOT2
23
16
VDDP2
[1]
14, 23
(8, 16)
15, 22
(9, 15)
3 (20)
16, 21
(10, 14)
2 (19)
18 (12)
10 V
1 (18)
17, 20
(11, 13)
010aaa595
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Parameter
Conditions
Min
Max
Unit
voltage difference
90
IORM
12
Tstg
storage temperature
55
+150
Tamb
ambient temperature
40
+85
Tj
junction temperature
150
VOSC
relative to VSSA
SGND + 6
Vpu
pull-up voltage
VI
input voltage
+5
VPROT
12
VMODE
referenced to SGND
II
input current
mA
VESD
2000
+2000
500
+500
120
VPWM(p-p)
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
in free air
40
K/W
Rth(j-c)
0.9
K/W
Parameter
Conditions
Min
Typ
Max
Unit
VDD
Operating mode
[1]
12.5
41
42.5
VSS
Operating mode
[2]
12.5
41
42.5
Vth(ovp)
overvoltage protection
threshold voltage
85
90
Vth(uvp)
undervoltage protection
threshold voltage
VDD VSS
20
25
Vth(ubp)
33
Supply
[3]
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Table 9.
Static characteristics continued
VDD = 41 V; VSS = 41 V; fosc = 335 kHz; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDD(tot)
50
60
mA
65
75
mA
490
650
[4]
Standby mode
[4][5]
0.8
Mute mode
[4][5]
2.2
3.0
Operating mode
[4][5]
4.2
5.5
[4][5]
6.6
110
150
37
+37
mV
150
+150
mV
30
+30
mV
210
+210
mV
9.5
10
10.5
138
139
Istb
standby current
II
input current
referenced to SGND
VI = 5.5 V
input voltage
DC input
[4]
[6]
[6]
Temperature protection
Tact(th_fold)
145
Thg(th_fold)
153
Tact(th_prot)
154
[1]
[2]
[3]
Unbalance protection activated when VDDA > 2 |VSSA| OR |VSSA| > 2 VDDA.
[4]
[5]
The transition between Standby and Mute modes has hysteresis, while the slope of the transition between Mute and Operating modes is
determined by the time-constant of the RC network on pin MODE; see Figure 11.
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[6]
DC output offset voltage is gradually applied to the output during the transition between Mute and Operating modes. The slope caused
by any DC output offset is determined by the time-constant of the RC network on pin MODE.
On
VO[V]
Mute
Standby
VO(offset)(on)
VO(offset)(mute)
0.8
2.2
3.0
4.2
5.5
VMODE[V]
Fig 11.
6.6
8
010aaa564
Parameter
Conditions
Min
Typ
Max
Unit
ROSC = 30.0 k
290
335
365
kHz
250
450
kHz
SGND + 4.5
SGND + 5
SGND + 6
SGND + 2.5
500
1000
kHz
Internal oscillator
fosc(typ)
fosc
oscillator frequency
Vtrip
trip voltage
HIGH-level
[1]
ftrack
tracking frequency
Zi
input impedance
Ci
input capacitance
15
pF
tr(i)
100
ns
from SGND + 0 V to
SGND + 5 V
[2]
[1]
When using an external oscillator, the frequency ftrack (500 kHz minimum, 1000 kHz maximum) will result in a PWM frequency fosc
(250 kHz minimum, 500 kHz maximum) due to the internal clock divider; see Section 8.3.
[2]
When tr(i) > 100 ns, the output noise floor will increase.
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Parameter
Conditions
output power
Gv(cl)
SVRR
Typ
Max Unit
160
210
[3]
235
Po = 1 W; fi = 1 kHz
[4]
0.03 0.1
Po = 1 W; fi = 6 kHz
[4]
0.05 -
29
30
31
dB
THD = 10 %; RL = 3 ; VP = 39 V
THD
Min
[2]
[5]
90
dB
[5]
70
dB
[5]
75
dB
[5]
120
dB
[5]
80
dB
[5]
60
dB
[5]
80
dB
[5]
115
dB
45
56
Zi
input impedance
Vn(o)
[6]
160
Mute mode
[7]
85
[8]
70
dB
dB
75
dB
cs
channel separation
|Gv|
mute
mute attenuation
fi = 1 kHz; Vi = 2 V (RMS)
CMRR
Vi(CM) = 1 V (RMS)
75
dB
po
SE, RL = 4
93
SE, RL = 3
90
[9]
BTL, RL = 8
RDSon(hs)
RDSon(ls)
93
[10]
110
[10]
105
[1]
RsL is the series resistance of the low-pass LC filter inductor used in the application.
[2]
Output power is measured indirectly; based on RDSon measurement; see Section 14.3.
[3]
One channel driven at maximum output power; the other channel driven at one eight maximum output power.
[4]
THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall filter.
[5]
Vripple = Vripple(max) = 2 V (p-p); measured independently between VDDPn and SGND and between VSSPn and SGND.
[6]
[7]
[8]
Po = 1 W; fi = 1 kHz.
[9]
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Parameter
Conditions
output power
THD
Gv(cl)
SVRR
Min
Typ
Max Unit
330
[2]
420
Po = 1 W; fi = 1 kHz
[3]
0.03 0.1
Po = 1 W; fi = 6 kHz
[3]
0.05 -
36
dB
[5]
80
dB
[5]
80
dB
[5]
95
dB
[5]
120
dB
[5]
75
dB
[5]
75
dB
[5]
90
dB
[5]
130
dB
45
56
Zi
input impedance
Vn(o)
[5]
190
45
75
dB
75
dB
Mute mode
[6]
mute
mute attenuation
fi = 1 kHz; Vi = 2 V (RMS)
[7]
CMRR
Vi(CM) = 1 V (RMS)
[1]
RsL is the series resistance of the low-pass LC filter inductor used in the application.
[2]
Output power is measured indirectly; based on RDSon measurement; see Section 14.3.
[3]
THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall filter.
[4]
[5]
22 Hz to 20 kHz, using an AES17 20 kHz brick wall filter; low noise due to BD modulation.
[6]
[7]
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(1)
(2)
Where:
Remark: Note that Io(peak) should be less than 12 A (Section 8.4.2). Io(peak) is the sum of
the current through the load and the ripple current. The value of the ripple current is
dependent on the coil inductance and the voltage drop across the coil.
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(3)
(4)
Where:
Remark: Note that Io(peak) should be less than 12 A; see Section 8.4.2. Io(peak) is the sum
of the current through the load and the ripple current. The value of the ripple current is
dependent on the coil inductance and the voltage drop across the coil.
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T j T amb
Rth (j a ) = ---------------------P
(5)
mbl469
30
P
(W)
(1)
20
(2)
10
(3)
(4)
(5)
0
0
20
40
60
80
100
Tamb (C)
Fig 12. Derating curves for power dissipation as a function of maximum ambient
temperature
TDA8954_1
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TDA8954
NXP Semiconductors
Rth(h-a) (thermal resistance from heatsink to ambient) = 10.3 (0.9 + 1) = 8.4 K/W
The derating curves for power dissipation (for several Rth(j-a) values) are illustrated in
Figure 12. A maximum junction temperature Tj = 150 C is taken into account. The
maximum allowable power dissipation for a given heatsink size can be derived, or the
required heatsink size can be determined, at a required power dissipation level; see
Figure 12.
Speaker impedance
Supply voltage
Audio signal frequency
Value of supply line decoupling capacitors
Source and sink currents of other channels
Pumping effects should be minimized to prevent the malfunctioning of the audio amplifier
and/or the voltage supply source. Amplifier malfunction due to the pumping effect can
trigger UVP, OVP or UBP.
The most effective way to avoid pumping effects is to connect the TDA8954 in a mono
full-bridge configuration. In the case of stereo single-ended applications, it is advised to
connect the inputs in anti-phase (see Section 8.5 on page 14). The power supply can also
be adapted; for example, by increasing the values of the supply line decoupling
capacitors.
Connect a solid ground plane around the switching amplifier to avoid emissions
Place 100 nF capacitors as close as possible to the TDA8954 power supply pins
Connect the heatsink to the ground plane or to VSSPn using a 100 nF capacitor
Use a thermally conductive, electrically non-conductive, Sil-Pad between the
TDA8954 heat spreader and the external heatsink
TDA8954_1
26 of 46
NXP Semiconductors
TDA8954_1
RVDDA
5.6 k
VDD
10
470
mode control
VDD
VDD
CVP
22 F
470 k
VSS
VSS
mute/
operating
RVSSA
VSS
10
mode
control
RPU2
10 k
VDD
ROSC
30 k
OSC
OSCREF
DIAG1
IN1P
10 k
standby/
operating
T1
HFE > 80
VPU
RPU1
10 k
10 k
470 k
CIN2
CVP1
CVSSP1
100 nF
100 nF
100 nF
23
VDD
CSN1
220 pF
RSN1
10
CSN2
220 pF
11
VSS
10
470 nF
LLC1
OUT1
BOOT1
CBO1
CLC1
15 nF
SGND
CIN3
19
TDA8954J
15
IN2P
LLC2
OUT2
VDD
21
220 nF
220 nF
VSS
VSS
VSSP2
RSN2
10
CVDDP2
CVP2
CVSSP2
100 nF
100 nF
100 nF
CPROT(1)
VSS
(1) The value of CPROT can be in the range 10 pF to 220 pF (see Section 8.4.2)
13
VDDP2
PROT
CSTAB
470 nF
16
VDD
CSN3
220 pF
VSS
CLC2
RZO2
22
CZO2 +
100 nF
CSN4
220 pF
VSS
010aaa559
TDA8954
27 of 46
CVSSA
17
n.c.
STABI
VSSA
VDDA
12
18
CVDDA
VDD
CZO1
100 nF
CBO2
470 nF
20
15 nF
14
IN2M
RZO1
22
CIN4
BOOT2
22
470 nF
IN2
680 nF
470 nF
T2
HFE > 80
IN1M
15 H
22 H
VSS
CVDDP1
470 nF
IN1
3 to 6
4 to 8
SGND
VPU
CIN1
10 F
5.6 k
VSSP1
CVSSP3
470 F
VDDP1
SGND
SINGLE-ENDED
OUTPUT FILTER VALUES
LOAD
LLC
CLC
+5 V
MODE
CVDDP3
470 F
DIAG2
+5 V
TDA8954
NXP Semiconductors
10
THD+N
(%)
1
(1)
(2)
101
(3)
102
102
101
102
10
103
Po (W)
VDD = 41 V, VSS = 41 V, fosc = 325 kHz (external 650 kHz oscillator), 2 4 SE configuration.
(1) fi = 1 kHz.
(2) fi = 6 kHz.
(3) fi = 100 Hz.
010aaa599
10
THD+N
(%)
1
(1)
(2)
101
(3)
102
102
101
10
102
103
Po (W)
VDD = 39 V, VSS = 39, fosc = 325 kHz (external 650 kHz oscillator), 2 3 SE configuration.
(1) fi = 1 kHz.
(2) fi = 6 kHz.
(3) fi = 100 Hz.
TDA8954_1
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TDA8954
NXP Semiconductors
010aaa600
10
THD+N
(%)
1
(2)
(1)
101
102
102
(3)
101
102
10
103
Po (W)
VDD = 41 V, VSS = 41, fosc = 325 kHz (external 650 kHz oscillator), 1 8 BTL configuration.
(1) fi = 1 kHz.
(2) fi = 6 kHz.
(3) fi = 100 Hz.
Fig 16. THD + N as a function of output power, BTL configuration with 1 8 load
010aaa655
THD+N
(%)
101
(3)
(1)
(2)
102
10
102
103
104
105
fi (Hz)
VDD = 41 V, VSS = 41, fosc = 325 kHz (external 650 kHz oscillator), 2 4 SE configuration.
(1) Po = 1 W.
(2) Po = 10 W.
(3) Po = 100 W.
TDA8954_1
29 of 46
TDA8954
NXP Semiconductors
010aaa656
THD+N
(%)
(3)
101
(1)
(2)
102
10
102
103
104
105
fi (Hz)
VDD = 39 V, VSS = 39, fosc = 325 kHz (external 650 kHz oscillator), 2 3 SE configuration.
(1) Po = 1 W.
(2) Po = 10 W.
(3) Po = 100 W.
010aaa629
THD+N
(%)
(3)
101
(1)
(2)
102
10
102
103
104
105
fi (Hz)
VDD = 41 V, VSS = 41, fosc = 325 kHz (external 650 kHz oscillator), 1 8 BTL configuration.
(1) Po = 1 W.
(2) Po = 10 W.
(3) Po = 100 W.
TDA8954_1
30 of 46
TDA8954
NXP Semiconductors
010aaa604
0
Chan sep
(dB)
20
40
60
80
100
102
10
103
104
105
fi (Hz
VDD = 41 V, VSS = 41, fosc = 325 kHz (external 650 kHz oscillator), 2 4 SE configuration.
Channel B S/N (dB).
010aaa605
0
Chan sep
(dB)
20
40
60
80
100
102
10
103
104
105
fi (Hz)
VDD = 39 V, VSS = 39, fosc = 325 kHz (external 650 kHz oscillator), 2 3 SE configuration.
Channel B S/N (dB).
TDA8954_1
31 of 46
TDA8954
NXP Semiconductors
010aaa606
60
PD
(W)
(1)
40
(2)
20
(3)
0
102
101
102
103
Po (W/channel)
10
Fig 22. Power dissipation as a function of output power per channel, SE configuration
010aaa607
100
(1)
Efficiency
(%)
(2)
(3)
80
60
40
20
0
0
50
100
150
200
250
Po (W/channel)
TDA8954_1
32 of 46
TDA8954
NXP Semiconductors
010aaa608
250
(1)
Po
(W)
(2)
200
(3)
(4)
150
100
50
0
12.5
17.5
22.5
27.5
32.5
37.5
Vp (V)
42.5
010aaa609
500
Po
(W)
400
(1)
300
(2)
200
100
0
12.5
17.5
22.5
27.5
32.5
37.5
Vp (V)
42.5
TDA8954_1
33 of 46
TDA8954
NXP Semiconductors
010aaa610
40
(1)
Gain
(dB)
(2)
30
(3)
20
10
102
10
103
104
105
Fi (Hz)
VDD = 30 V, VSS = 30 V, fosc = 325 kHz (external 650 kHz oscillator), Vi = 100 mV, Ci = 330 pF.
(1) 1 8 configuration; LLC = 15 H, CLC = 680 nF, VDD = 41 V, VSS = 41 V.
(2) 2 4 configuration; LLC = 15 H, CLC = 680 nF, VDD = 41 V, VSS = 41 V.
(3) 2 3 configuration; LLC = 15 H, CLC = 680 nF, VDD = 39 V; VSS = 39 V.
010aaa611
0
SVRR
(dB)
20
40
60
(1)
80
(2)
100
102
10
103
104
105
Fi (Hz)
TDA8954_1
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TDA8954
NXP Semiconductors
010aaa612
0
SVRR
(dB)
20
40
60
(1)
80
(2)
100
102
10
103
104
105
Fi (Hz)
010aaa657
10
VOut
(V)
1
101
102
103
104
105
0
8
VMODE (V)
VDD = 41 V, VSS = 41 V, Vi = 100 mV, fosc = 325 kHz (external 650 kHz oscillator), fi = 1 kHz
(1) Mode voltage down.
(2) Mode voltage up.
TDA8954_1
35 of 46
TDA8954
NXP Semiconductors
010aaa614
0
Mute
Suppression
(dB)
20
40
60
80
100
10
102
103
104
105
Fi (Hz)
VDD = 39 V, VSS = 39 V, fosc = 325 kHz (external 650 kHz oscillator), Vi = 2 V (RMS).
2 3 SE configuration; channel A suppression (dB)
010aaa615
0
Mute
Suppression
(dB)
20
40
60
80
100
10
102
103
104
105
Fi (Hz)
VDD = 41 V, VSS = 41 V, fosc = 325 kHz (external 650 kHz oscillator), Vi = 2 V (RMS).
2 4 SE configuration; channel A suppression (dB)
TDA8954_1
36 of 46
TDA8954
NXP Semiconductors
010aaa630
300
Po
(W)
(3)
200
(1)
100
OTP activated
(2)
(4)
0
0
100
200
300
400
500
600
T (sec)
VDD = 39 V, VSS = 39 V, fosc = 325 kHz (external 650 kHz oscillator), 2 3 SE configuration.
Heat sink: Fisher SK495/50; Sil-Pad: 1500ST. Condition: 30 minutes pre-heated in Mute
(1) Maximum output power; TFB on.
(2) Maximum output power / 8; TFB on.
(3) Maximum output power; TFB off.
(4) Maximum output power / 8; TFB off.
010aaa631
250
Po
(W)
(3)
200
(1)
150
100
50
(4)
(2)
0
0
100
200
300
400
500
600
T (sec)
VDD = 41 V, VSS = 41 V, fosc = 325 kHz (external 650 kHz oscillator), 2 4 SE configuration
Heat sink: Fisher SK495/50; Sil-Pad: 1500ST. Condition: 30 minutes pre-heated in Mute
(1) Maximum output power; TFB on.
(2) Maximum output power / 8; TFB on.
(3) Maximum output power; TFB off.
(4) Maximum output power / 8; TFB off.
TDA8954_1
37 of 46
TDA8954
NXP Semiconductors
SOT411-1
non-concave
Dh
x
D
Eh
A5
A4
E2
B
j
E1
L2
L3
L1
L
1
e1
Z
e
v M
e2
w M
bp
23
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A 2
mm
A4
A5
bp
D (1)
D h E (1)
e1
e2
12.2
4.6 1.15 1.65 0.75 0.55 30.4 28.0
12
2.54 1.27 5.08
11.8
4.3 0.85 1.35 0.60 0.35 29.9 27.5
Eh
E1
E2
L1
L2
L3
Z (1)
14 10.7 2.4
1.43
2.1
4.3
0.6 0.25 0.03 45
13 9.9 1.6
0.78
1.8
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
98-02-20
02-04-24
SOT411-1
38 of 46
TDA8954
NXP Semiconductors
HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height
SOT566-3
E
D
c
E2
HE
v M A
D1
D2
12
pin 1 index
Q
A
A2
E1
(A3)
A4
Lp
detail X
24
13
w M
bp
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
A2
max.
3.5
3.5
3.2
A3
0.35
A4(1)
D1
D2
E(2)
E1
E2
HE
Lp
1.1
0.9
11.1
10.9
6.2
5.8
2.9
2.5
14.5
13.9
1.1
0.8
1.7
1.5
bp
D(2)
2.7
2.2
8
0
Notes
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
03-02-18
03-07-23
SOT566-3
39 of 46
TDA8954
NXP Semiconductors
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
40 of 46
TDA8954
NXP Semiconductors
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 36) than a SnPb process, thus
reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 13 and 14
Table 13.
350
< 2.5
235
220
2.5
220
220
Table 14.
350 to 2 000
> 2 000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
TDA8954_1
41 of 46
TDA8954
NXP Semiconductors
temperature
peak
temperature
time
001aac844
42 of 46
TDA8954
NXP Semiconductors
Package
Soldering method
Dipping
Wave
CPGA, HCPGA
suitable
suitable
suitable[1]
PMFP[2]
not suitable
[1]
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
[2]
TDA8954_1
43 of 46
TDA8954
NXP Semiconductors
Revision history
Document ID
Release date
Change notice
Supersedes
TDA8954_1
20091224
TDA8954_1
44 of 46
TDA8954
NXP Semiconductors
Product status[3]
Definition
Development
This document contains data from the objective specification for product development.
Qualification
Production
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
19.3 Disclaimers
General Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TDA8954_1
45 of 46
TDA8954
NXP Semiconductors
21. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.4
8.4.1
8.4.1.1
8.4.1.2
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.5
9
10
11
12
13
13.1
13.2
13.3
14
14.1
14.2
14.3
14.3.1
14.3.2
14.4
14.5
14.6
14.7
14.8
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 5
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pulse-width modulation frequency . . . . . . . . . . 8
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal protection . . . . . . . . . . . . . . . . . . . . . . 9
Thermal FoldBack (TFB) . . . . . . . . . . . . . . . . . 9
OverTemperature Protection (OTP) . . . . . . . . 10
OverCurrent Protection (OCP) . . . . . . . . . . . . 11
Window Protection (WP). . . . . . . . . . . . . . . . . 13
Supply voltage protection . . . . . . . . . . . . . . . . 13
Clock protection (CP) . . . . . . . . . . . . . . . . . . . 14
Overview of protection functions . . . . . . . . . . 14
Differential audio inputs . . . . . . . . . . . . . . . . . 14
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 16
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal characteristics . . . . . . . . . . . . . . . . . 18
Static characteristics. . . . . . . . . . . . . . . . . . . . 18
Dynamic characteristics . . . . . . . . . . . . . . . . . 20
Switching characteristics . . . . . . . . . . . . . . . . 20
Stereo SE configuration characteristics . . . . . 21
Mono BTL application characteristics . . . . . . . 22
Application information. . . . . . . . . . . . . . . . . . 23
Mono BTL application . . . . . . . . . . . . . . . . . . . 23
Pin MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Estimating the output power . . . . . . . . . . . . . . 23
Single-Ended (SE) . . . . . . . . . . . . . . . . . . . . . 23
Bridge-Tied Load (BTL) . . . . . . . . . . . . . . . . . 24
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 24
Heatsink requirements . . . . . . . . . . . . . . . . . . 24
Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 26
Application schematic . . . . . . . . . . . . . . . . . . . 26
Curves measured in reference design
(demo board TDA8954J) . . . . . . . . . . . . . . . . 28
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 38
Soldering of SMD packages . . . . . . . . . . . . . . 40
16.1
16.2
16.3
16.4
17
17.1
17.2
17.3
17.4
18
19
19.1
19.2
19.3
19.4
20
21
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Soldering of through-hole mount packages.
Introduction to soldering through-hole mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soldering by dipping or by solder wave . . . . .
Manual soldering . . . . . . . . . . . . . . . . . . . . . .
Package related soldering information. . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
40
40
41
42
42
42
42
43
44
45
45
45
45
45
45
46
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.