VALLIAMMAI ENGINEERING COLLEGE

SRM Nagar, Kattankulathur 603 203.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
QUESTION BANK
SUBJECT

: CS6303 / COMPUTER ARCHITECTURE

SEM / YEAR : VI / III year B.E.

Q.No
Define Amdahls law.
1.

Unit I
OVERVIEW AND INSTRUCTIONS
Part A
Questions

BT Level
BTL 1

Domain
Remembering

2.

Identify general characteristics of Relative addressing mode with an

example.

BTL 4

Analyzing

3.

Discuss the eight great ideas in computer architecture.

BTL 2

Understanding

4.

List the five classic components of a computer.

BTL 1

Remembering

5.

BTL 2

Understanding

6.

How would you summarize the function of data path and control
path?
How do you interpret the instruction set Architecture?

BTL 2

Understanding

7.

Differentiate DRAM and SRAM.

BTL 4

Analyzing

8.

Compare and contrast volatile and nonvolatile memory.

BTL 2

Understanding

9.

Define VLSI.

BTL 1

Remembering

10.

What facts would you select to show throughput and response time?

BTL 3

Applying

11.

Can you elaborate the CPU performance equation?

BTL 5

Evaluating

12.

BTL 5

Evaluating

13.

If computer A runs a program in 10 seconds, and computer B runs

the same program in 15 seconds, how much faster is A over B?
Justify your answer.
Construct the formula for CPU execution time for a program.

BTL 6

Creating

14.

List the data transfer instructions.

BTL 1

Remembering

15.

Build the formula for CPU clock cycles required for a program.

BTL 3

Applying

16.

Define Stored Program Concept.

BTL 1

Remembering

17.

What are the fields in an MIPS instruction?

BTL 1

Remembering

Prepared by S.Suma (A.P(S.G)), S.Benila A.P(OG),V.Prema A.P(O.G) 1

18.
19.
20.

Can you make a distinction between multiprocessor over

uniprocessor?
What examples can you give to relative and indirect addressing
mode?
Consider the following performance measurements for a program
Measurement
Computer A
Instruction
10 billion
Count
Clock rate
4GHz
CPI
1.0
Which computer has the higher MIPS rating?

1.(i)
(ii)
2.
3.
4.
5.

6.

7.

8.

BTL 4

Analyzing

BTL 3

Applying

BTL 6

Creating

BTL 5
BTL 2
BTL 1
BTL 1

Evaluating
Understanding
Remembering
Remembering

BTL 1

Remembering

BTL 2
BTL 5

Understanding
Evaluating

BTL 4

Analyzing

BTL 3

Applying

Computer B
8 billion
4GHz
1.1

Part B
Summarize the eight great ideas of computer Architecture.(8)
Describe the technologies for Building Processors and Memory. (8)
List the various components of computer system with neat diagram.
Define addressing mode. Describe the basic addressing modes with an
example for each.
What are the operations and operands of computer Hardware? Explain
in detail .
Discuss the logical operations and control operations of computer .(8)
Explain the concept of Powerwall processor . (8)

Consider three different processors P1, P2, and P3 executing the

same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2
has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock
rate and has a CPI of 2.2.
a) Which processor has the highest performance expressed in
instructions per second?
b) If the processors each execute a program in 10 seconds, find
the number of cycles and the number of instructions?
c) We are trying to reduce the execution time by 30% but this
leads to an increase of 20% in the CPI. What clock rate should
we have to get this time reduction?
Assume a program requires the execution of 50 106 FP
istructions,110 106 INT instructions, 80 106 L/S instructions,
and 16 106 branch instructions The CPI for each type of
instruction is 1, 1, 4, and 2, respectively. Assume that the processor
has a 2 GHz clock rate.
a) By how much must we improve the CPI of FP instructions if
we want the program to run two times faster?
b) By how much must we improve the CPI of L/S instructions
if we want the program to run two times faster?
c) By how much is the execution time of the program improved if
the CPI of INT and FP Instructions are reduced by 40% and the
CPI of L/S and Branch is reduced by 30%?
Describe the branching operations with suitable example.

BTL 2

Understanding

Prepared by S.Suma (A.P(S.G)), S.Benila A.P(OG),V.Prema A.P(O.G) 2

How would you formulate the performance of CPU and compose the
factors that affect performance?
10.(i) Assume a two address format specified as source, destination. Examine
the following sequence of instructions and identy the addressing modes
used and the operation done in
every instruction
(1) Move (R5)+, R0
(2) Add(R5)+, R0
(3) Move R0, (R5)
(4) Move 16(R5),R3
(5) Add #40, R5
9.

(ii)

Consider the computer with three instruction classes and CPI

measurements as given below and instruction counts for each
instruction class for the same program from two different compilers are
given. Assume that the computers clock rate is 1GHZ which code
sequence will execute faster according to execution time?
Code from
CPI for the instruction class
A
B
C
CPI
1
2
3
Code from
CPI for the instruction class
A
B
C
Compiler1
2
1
2
Compiler2
2
1
1

BTL 6

Creating

BTL 3

Applying

BTL 4

Analyzing

BT Level

Competence

BTL 4

Analyzing

UNIT II
ARITHMETIC OPERATIONS
PART A
Q.No

Questions

1.

Add 510 to 610 in binary and Subtract -610 from 710 in binary )

2.

How would you examine the overflow conditions for addition and
subtraction?
Construct the Multiplication hardware diagram.
List the steps of multiplication algorithm.
What is fast multiplication?
List the steps of division algorithm .
Illustrate scientific notation and normalization with example.
What approach would you use to interpret single precision floating
point number?

BTL 3

Applying

BTL 3
BTL 1
BTL 1
BTL 1
BTL 3
BTL 2

Applying

Contrast overflow and underflow with examples.

Give the representation of double precision floating point number.
What are the floating point instructions in MIPS?
Can you formulate the steps of floating point addition?

BTL 2
BTL 2
BTL 1
BTL 6

3.
4.
5.
6.
7.
8.
9.
10.
11.
12.

Remembering
Remembering
Remembering
Applying

Understanding
Understanding
Understanding
Remembering
Creating

Prepared by S.Suma (A.P(S.G)), S.Benila A.P(OG),V.Prema A.P(O.G) 3

Evaluate the sequence of floating point multiplication.

Define Guard and Round bit.
Write the IEEE 754 floating point format.
What is meant by sub-word parallelism?
Multiply 100011 * 100010.
Divide 1,001,010 by 1000.
For the following C statement, what is the corresponding MIPS
assembly code?
f = g + (h 5)
For the following MIPS assembly instructions above, what is a
corresponding C statement?
add f, g, h
add f, i, f
PART B

BTL 5
BTL 1
BTL 2
BTL 1
BTL 4
BTL 4
BTL 6

Evaluating
Remembering
Understanding
Remembering
Analyzing
Analyzing
Creating

BTL 5

Evaluating

Discuss the multiplication algorithm in detail with diagram and

examples .
How would you describ the division algorithm with diagram?
How floating point addition is carried out in a computer system? Give
an example for a binary floating point addition.
Summarize in detail the floating point multiplication algorithm.
How would you solve the multiplication of signed 2s complement
numbers? Give algorithm and example

BTL 2

Understanding

BTL 1
BTL 1

Remembering
Remembering

BTL 2
BTL 3

Understanding

6.

Assume A and B for a pair of signed 2s complement numbers with

values : A = 010111, B = 101100. Develop algorithm to implement
A*B.

BTL 6

Creating

7.

How would you estimate the result of the numbers 0.510 +( 0.437510) using binary Floating point Addition algorithm?

BTL 5

Evaluating

8.

Multiply 1.10 10X 1010and 9.200X10-5 using binary Floating point

multiplication .

BTL 4

Analyzing

9.

Calculate the division of A and B

BTL 4

Analyzing

BTL 1

Remembering

13.
14.
15.
16.
17.
18.
19.

20.

1.
2.
3.
4.
5.

A=3.264 X 103 and B= 6.52 X 102

10. Tabulate the IEEE 754 binary representation of the number
- 0.75 10 in single and double precision.

Applying

UNIT III
PROCESSOR AND CONTROL UNIT
PART A
Q.No
1.

Questions
What is meant by data path element?

BT
Level
BTL 2

Competence

Understanding

Prepared by S.Suma (A.P(S.G)), S.Benila A.P(OG),V.Prema A.P(O.G) 4

2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.

Summarize the use of PC register.

Define register file.
List the state elements needed to store and access an instruction.
Draw the diagram of portion of datapath used for fetching instruction.
Compare Sign Extend and Vector interupts .
What is meant by branch target address?
How would you evaluate branch taken and branch not taken in
instruction execution?
How would you examine delayed branching?
Design the instruction format for the jump instruction.
Classify the different types of hazards with examples.
How would you apply data forwarding to avoid data hazards?
How could you determine the pipeline stall?
What is meant by branch prediction?
Construct the 5 stages pipeline.
What motive is there in using exceptions and interrupts?
What is pipelining?
Illustrate the five steps used in MIPS instruction execution.
Classify the types of instruction classes and their instruction formats.
Formulate the calculating time between instructions in a
pipelined processor.

BTL 2
BTL 1
BTL 1
BTL 2
BTL 2
BTL 1
BTL 5

Understanding
Remembering
Remembering
Understanding
Understanding
Remembering
Evaluating

BTL 1
BTL 6
BTL 4
BTL 3
BTL 5
BTL 1
BTL 3
BTL 4
BTL 1
BTL 3
BTL 4
BTL6

Remembering
Creating
Analyzing

Discuss the basic MIPS implementation of instruction set .

Describe MIPS implementation with necessary multiplexers and
control lines.
What are control hazards? Describe the methods for dealing with the
control hazards.
Design and develop an instruction pipeline working under various
situations of pipeline stall.

BTL 2
BTL 1

Understanding
Remembering

BTL 1

Remembering

BTL 6

Creating

What is data hazard? How do you overcome it? What are its side
effects?
Compare the data and control path methods in pipelining.
(i)Can you make the distinction between sequential execution and
pipelining?(8)
(ii)Construct the model for building a datapath. (8)
Recommend the techniques for dynamic branch prediction.
Examine the approaches would you use to handle exceptions in MIPS.
What motive is there in using control path implementation in
pipelining?

BTL 1

Remembering

BTL 2
BTL
4&3

Understanding
Analyzing

BTL 5
BTL 3
BTL 4

Evaluating
Applying
Analyzing

Applying
Evaluating
Remembering
Applying
Analyzing
Remembering
Applying
Analyzing
Creating

PART B
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

Applying

UNIT IV
PARALLELISM
PART A

Prepared by S.Suma (A.P(S.G)), S.Benila A.P(OG),V.Prema A.P(O.G) 5

Q.No

Questions
What is the main idea of ILP?
What approach would you use to organize a multiple issue processor?
Can you list the three important properties of vector instructions?
List the main characteristics of SMT processor.

BT
Level
BTL 2
BTL 3
BTL 1
BTL 4

1.
2.
3.
4.

Understanding
Applying
Remembering
Analyzing

5.

What inference can you make from loop unrolling technique?

BTL1

Remembering

6.

Define VLIW processor.

BTL1

Remembering

7.

What is meant by anti-dependence? How is it removed?

BTL 2

Understanding

8.

How would you examine the efficiency of superscalar processor?

BTL 1

Remembering

9.

Will you state the need of speculation?

BTL 2

Understanding

10.

Show the performance of cluster organization.

BTL 3

Applying

11.
12.
13.

What is the relationship between SMT and hardware multithreading?

Define the Flynn classification.
How do you integrate the ideas of in-order execution and out-of-order
execution?
Can you make the distinction between UMA and NUMA?
Identify the use of hardware in multithreading option.
What can you say about sub-word parallelism ?
How would you formulate the various approaches to hardware
multithreading?
Categorize the various multithreading options.
What ideas justify a multicore processor?
What approaches would you use to improve performance of a
processor?
PART B

BTL 5
BTL 1
BTL 6

Evaluating
Remembering
Creating

BTL 5
BTL 1
BTL 2
BTL 6

Evaluating
Remembering
Understanding
Creating

BTL 4
BTL 4
BTL 3

Analyzing
Analyzing
Applying

List the main characteristics of Instruction level parallelism.

What are the facts or challenges faced by parallel processing
programs? Summarize.
What is the main idea of using message passing in multiprocessor?
How would you show your understanding of using hardware in
multithreading ?
Describe data level parallelism in SIMD and MISD machine .
a) How would you use shared memory concept in multi-processor?(8)
b)Compare and contrast Fine grained and Coarse grained
multithreading.(8)
What are the features of Multicore processors?
How would you classify the types of multithreading?
How would you formulate the ideas of Flynns classification?
a) Define vector processor.
b) Describe SPMD processor.

BTL 1
BTL 2

Remembering
Understanding

BTL 2
BTL 3

Understanding

BTL 1
BTL
3&4

Remembering
Applying
Analyzing

BTL 5
BTL 4
BTL 6
BTL 1

Evaluating
Analyzing
Creating
Remembering

14.
15.
16.
17.
18.
19.
20.

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

Competence

Applying

Prepared by S.Suma (A.P(S.G)), S.Benila A.P(OG),V.Prema A.P(O.G) 6

UNIT V

MEMORY AND I/O SYSTEM

PART A
Q.No

Questions

BT Level

Competence

1.
2.
3.
4.
5.
6.
7.
8.

Distinguish the types of locality of references.

Define the structure of memory hierarchy.
How would you summarize the various memory technologies?
Compare and contrast SRAM and DRAM.
What is flash memory?
Define Rotational Latency.
What is direct-mapped cache?
Evaluate the following instance wherein the cache size is 64 blocks
and block size is 16 bytes. What block number does byte address
1200 map?
How many total bits are required for a direct-mapped cache
with 16 KB of data and 4-word blocks, assuming a 32-bit
address?
How would you analyze the writing strategies in cache memory?
What are the functional steps required in an instruction cache miss?
Define hit rate and miss rate.
Summarize the various block placement schemes in cache memory.
Define Mean Time to Failure rate.
Compare the three ways to improve MTTF.
How would you show your understanding of the role of TLB in
virtual memory?
Can you make use of virtual memory concept in memory
management?
What is the relationship between physical address and logical
address?
What is main idea of address mapping?
How would you use interrupts in cases of exceptions?
PART B
List the various memory technologies and examine its relevance in
architecture design.
Describe in detail the memory hierarchy with neat diagram.
Summarize the basic operations of cache in detail with diagram.
Distinguish the various mapping schemes used in cache design.
a) A byte addressable computer has a small data cache capable of
holding eight 32-bit words. Each cache block contains 132-bit word.
When a given program is executed, the processor reads data from the
following sequence of hex addresses 200, 204, 208, 20C, 2F4, 2F0,

BTL 2
BTL 1
BTL 2
BTL 4
BTL 1
BTL 1
BTL 1
BTL 5

Understanding
Remembering
Understanding
Analyzing
Remembering
Remembering
Remembering
Evaluating

BTL 6

Creating

BTL 4
BTL 6
BTL 1
BTL 2
BTL 1
BTL 4
BTL 3

Analyzing
Creating
Remembering
Understanding
Remembering
Analyzing
Applying

BTL 3

Applying

BTL 5

Evaluating

BTL 2
BTL 3

Understanding
Applying

BTL 1

Remembering

BTL 1
BTL 2
BTL 2
BTL 3

Remembering
Understanding
Understanding

9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
1.
2.
3.
4.
5.

Applying

Prepared by S.Suma (A.P(S.G)), S.Benila A.P(OG),V.Prema A.P(O.G) 7

200,204,218, 21C, 24C, 2F4. The pattern is repeated four times.

Assuming that the cache is initially empty, show the contents of the
cache at the end of each pass, and compute the hit rate for a direct
mapped cache. (8)
b) What are the methods used to measure and improve the
performance of the cache. (8)
6. Describe the virtual memory address translation and TLB with
necessary diagram.
7. How would you demonstrate the DMA controller for data transfer
between memory and peripherals?
8. Can you summarize the concept of interrupts with neat diagrams?
9. What choice in design would you have made for standard input and
output interfaces required to connect the I/O device to the bus?
10. How would you classify the bus arbitration techniques in DMA?

BTL 4

Analyzing

BTL 1

Remembering

BTL 3

Applying

BTL 5
BTL 6

Evaluating
Creating

BTL 4

Analyzing

Prepared by S.Suma (A.P(S.G)), S.Benila A.P(OG),V.Prema A.P(O.G) 8