DLD Manual (Jib)

QURTUBA UNIVERSITY OF SCIENCE & IT
ENGINEERING
DEPARTMENT OF ELECTRICAL
Table of Contents
Lab 2 Number Systems............................................................................................ 1
LAB 3 Verification of Truth Table, Become Familiar with Different ICs.....................8
Lab 5................................................................................................................. 19
Boolean Laws and DeMorgan's Theorem
........................................................................................................................... 19
EE xxxL DIGITAL LOGIC DESIGN LAB
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ENGINEERING
Lab 2 Number Systems
2.1
OBJECTIVES
Convert between binary, BCD, octal, hexadecimal, and base ten number systems.
Construct a circuit that demonstrates conversions between number systems.
2.2
REFERENCE READING
Floyd, Digital Fundamentals, Chapter 2; Section 2-1 to 2-9.
2.3
MATERIALS NEEDED
Four LEDs
7447A BCD/decimal decoder
MAN1 seven-segment display
Four-position DIP switch
Resistors:
2.4
SUMMARY OF THEORY
The number of symbols in a number system is called die base or radix of that system. The decimal
number system uses ten counting symbols the digits 0 through 9 to represent quantities. Thus it is a base
ten system. In this system, we represent quantities larger than 9 by using positional weighting of the
digits. The position, or column, that a digit occupies indicates the weight of that digit in determining the
value of the number. The base ten number system is a weighted system because each column has a value
associated with it.
2.4.1 BINARY NUMBERS
Digital systems use two states to represent quantities and thus are binary in nature. The binary counting
system has a radix 2 and uses only the numbers 0 and 1. (These are often called bits, which is a
contraction of Binary digit). It too is a weighted counting system, with each column value worth twice
the value of the column to the immediate right. Because binary numbers have only two digits, large
numbers expressed in binary require a long string of Os and Is. Other systems, which arc related to
binary in a simple way, are often used to simplify these numbers. These systems include octal,
hexadecimal, and BCD.
2.4.2 OCTAL NUMBERS
The octal number system is a weighted number system using the digits 0 through 7. The column values in
octal are worth 8 times that of the column to the immediate right. You convert from binary to octal by
arranging the binary number in groups of 3 bits, starting at the binary point, and writing the octal symbol
for each binary group. You can reverse the procedure to convert from octal to binary. Simply write an
equivalent 3-bit binary number for each octal character.
2.4.3 HEXADECIMAL SYSTEM
The hexadecimal system is a weighted number system using 16 characters. The column values in
hexadecimal (or simply hex) are worth 16 times that of the column to the immediate right. The characters
are the numbers 0 through 9 and the first six letters of the alphabet, A through F. Letters were chosen
because of their sequence, but remember that they are used to indicate numbers, not letters. You convert
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ENGINEERING
binary numbers to hexadecimal numbers by arranging the binary number into 4-bit groups, starting at the
binary point. Then write the hex symbol for each group of four bits. You convert hex numbers to binary
by reversing the procedure. That is, write an equivalent 4-bit binary number for each hexadecimal
character.
The BCD system uses four binary bits to represent each decimal digit. It is a convenient code because it
allows ready conversion from base ten to a code that a machine can understand; however, it is wasteful of
bits. A 4-bit binary number could represent the numbers 0 to 15, but in BCD it represents only the
quantities 0 through 9. The binary representations of the numbers 10 through 15 are not used in BCD and
are invalid.
A simple circuit can illustrate the various number systems discussed above. The circuit in this experiment
uses light-emitting diodes (LEDs) to show the binary or BCD number and a seven-segment display; to
show the equivalent base ten numbers. A seven segment display is a special arrangement of LEDs that
can form the numbers 0 through 9 and some letters. Figure 2-1 illustrates the arrangement of diodes in a
seven-segment display. The circuit uses an IC called a decoder to convert the binary input to a sevensegment value. Decoder circuits will be studied later in the course.
Figure 2-1: MANI seven-segment display
2.5
CONVERSIONS BETWEEN NUMBER SYSTEMS
1. Connect the circuit shown in Figure 2-2. Test each switch to see that it turns on an LED. This portion
of the circuit represents the input binary number. A lighted LED represents a binary one, and an un
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ENGINEERING
lighted LED represents a binary zero. The least significant bit (LSB) is on the right and represents the
1s column. The most significant bit (MSB) is on the left.
Column weight of MSB = ___________
+5.0 V
4-position
DIP switch
Switch
MSB
330
LSB
330
330
330
Figure 2-2
2. Now remove power and add the circuit shown in Figure 2-3. The pin numbers for the MANI display
are shown in Figure 2-1, and 7447A pin numbers are shown in Figure 2-4. Note that the 7447 has 16
pins and the MAN1 seven-segment display has only 14 pins. Both are numbered counterclockwise
starting from the top left.
Connect pins 3,4 and 5 on the 7447 A to a 1 k resistor connected to +5 V. Connect pin 14 of the
MANI to +5 V. Be sure to connect each output from the 7447A through a 330 resistor to the
segment display as shown on the circuit drawing.
3. When you have completed wiring the circuit, test it by checking each switch combination shown in
Table 2-1 on the next page. Set the binary number on the switches by closing a switch for a 1 and
opening a switch for a 0. Complete each column for the table by writing the input numbers as BCD,
octal, and hexadecimal. Show the output from the seven-segment display in the right-hand column.
The last six invalid BCD codes will show a unique code in the seven-segment display.
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ENGINEERING
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ENGINEERING
Figure 2-4
Table 2-1
Input
Binary
Number
BCD
Number
Output
Octal
Number
Hex
Number
Seven-Segment
Display
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
2.5.1
REVIEW QUESTIONS
1. Convert each number shown into the other bases:

Binary
01001100
________
Octal
________
304
________
________
________
________
________
________
Hex
______
__
______
__
E6
Decimal
________
______
__
______
__
57
________
________
________
BCD
_______
_
_______
_
_______
_
_______
_
0100100
1
2. Assume that you set the switches in Figure 2-3 for 1000, but the seven-segment display shows a 0.
What are the possible causes for this malfunction?
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ENGINEERING
3. Look up the 7447A in the data book. Find the maximum available output current for segments a-g.
Note that a positive sign is for conventional current (plus to minus) flowing INTO the IC. A negative
sign is for conventional current flowing OUT of the IC. Note that IOL is several orders of magnitude
greater than IOH. Thus, current into the device can be much larger than the current from the device.
This situation is typical of TTL logic, although the values for the 7447 A are somewhat larger than
most TTL ICs. Fill in the values for IOL and IOH:
7447A IOL = _________
7447A IOH = _________
2.6
ASSESSMENT SHEET
Name: ___________________________
Reg. No. : ________________________
Date of Lab: _____________________
Table 2-1
Problem
Number
Lab
Performance
Review Question
Review Question
Review Question
Working
Viva
Total Score in Lab
Page | 7

ENGINEERING
LAB 3 Verification of Truth Table, Become Familiar with Different

ICs
3.1
3.2
OBJECTIVES
To become familiar with the IC 7400 series NAND gate and its Truth Table.
To become familiar with the IC 7402 series NOR gate and its Truth Table.
To become familiar with the IC 7404 series INVERTER gate and its Truth Table.
MATERIALS NEEDED
7400 IC
7402 IC
7404 IC
7410 IC
7420 IC
Vcc=5volts or DC power supply
Advance logic trainer board
Connecting Wires
3.3
SUMMARY OF THEORY
3.3.1
Use of 7400 IC:

The basic circuit for the 7400 series IC is NAND gate. It provides 4 two inputs NAND gates on a
single chip of 14 pins in which 7 pins is grounded while 14 is connected to V CC. Using one of its
NAND gate make the connections on the advance logic trainer board and write the truth table for
the NAND gate. Supply 5 volts DC and give inputs according to the truth table. The output
observed satisfied the truth table.
BOOLEAN EQUATION:
3.3.2
(A. B) / = C
Use of 7402 IC:

The basic circuit for the 7402 series IC is NOR gate. It provides four, 2 inputs NOR gates of 14
pins in which 7th pin is grounded while 14th pin is connected to VCC. Using one of the NOR gate,
make the connections on the advance logic trainer board and write the truth table for the NOR
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ENGINEERING
gate. Supply 5V DC and give inputs according to the truth table, the output observed should
satisfy the truth table.
BOOLEAN EQUATION:
3.3.3
(A + B) / = C
Use of 7404 IC:

The basic circuit for the 7404 series IC is NOT gate (invertors). It provides 6 NOT gates on a
single chip in which 7th pin is grounded while 14 th pin is connected to VCC. Using one of its NOT
gate make the connections on the advance logic trainer board and write the truth table for the
NOT gate. Supply 5V DC and give inputs according to the truth table the output observed
satisfied the truth table.
BOOLEAN EQUATION:
3.3.4
A=A/
Use of 7410 IC:

The basic circuit for the 7400 series IC is NAND gate. It provides 3 three inputs NAND gates on
a single chip of 14 pins in which 7 pins is grounded while 14 is connected to V CC. Using one of its
BOOLEAN EQUATION:
3.3.5
(A. B. C) / = D
Use of 7420 IC:

The basic circuit for the 7400 series IC is NAND gate. It provides 2 four inputs NAND gates on a
single chip of 14 pins in which 7 pins is grounded while 14 is connected to V CC. Using one of its
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ENGINEERING
(A. B. C. D) / = E
BOOLEAN EQUATION:
The Truth Tables of these ICs along with symbols are shown as under.
INPUTS
OUTPUT
Table 3-1 Truth table and pin diagram of 7400 IC
INPUTS
OUTPUT
INPUT
OUTPUT
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ENGINEERING
INPUTS
A
1
A
OUTPUT
1
INPUTS
1
1
D
1
OUTPUT
0
E
1
1
0
1
1
1
1
0
1
Table 3-4 Truth table and pin
diagram of 7410 IC
1
1
0
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ENGINEERING
7420
3.4
ASSESSMENT SHEET
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ENGINEERING
Name: ___________________________
Reg. No. : ________________________
Date of Lab: _____________________
Table 3-1
Problem
Number
Table 3-2 & 3-3

Table 3-4
Table 3-5
Lab
Performance
Working
Viva
Total Score in Lab
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ENGINEERING
LAB 4 To Test the Versatility of Universal Gates

4.1
4.2
OBJECTIVES
To become familiar with the IC 7402 series NOR gate and its Truth Table.
To become familiar with the IC 7404 series INVERTER gate and its Truth Table.
Use of above ICs in implementation of Boolean algebra.
MATERIALS NEEDED
7400 IC
7402 IC
7404 IC
Connecting Wires
4.3
SUMMARY OF THEORY
A universal gate is a gate which can implement any Boolean function without need to use any other gate
type. The NAND and NOR gates are universal gates. In practice, this is advantageous since NAND and
NOR gates are economical and easier to fabricate and are the basic gates used in all IC digital logic
families. In fact, an AND gate is typically implemented as a NAND gate followed by an inverter not the
other way around!! Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter
not the other way around!!
Verify the gates.

Make the connections as per the circuit diagram.
Switch on VCC and apply various combinations of input according to truth table.
Note down the output readings for full adder Sum carry bit for different
Combinations of inputs verify their truth tables.
All the connections should be made properly.
IC should not be reversed.
4.3.1 USING NAND AS NOT GATE:

A NAND gate is used as NOT gate by circuiting the input terminals of the NAND gate as shown in the
Fig-1.
BOOLEAN EQUATION:
4.3.2
(A. A)/ = A/
USING NAND AS AND GATE:
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ENGINEERING
A NAND gate used as AND gate by the connecting NOT gate at the output of the NAND gate as shown
in the Fig-1.
BOOLEAN EQUATION:
C = (A.B) / = A/ + B/
C/ = (A/ + B/) / = A//.B// = A.B
4.3.3 USING NAND AS OR GATE:

A NAND gate is used as OR gate by connecting NOT gate at the input of the NAND gate as shown in the
Fig-1.
BOOLEAN EQUATION:
C = (A/. B/) / = A//+B// = A+B
4.3.4 USING NAND AS NOR GATE:

A NAND gate is used as NOR gate by connecting NOT gate at the input s and output of the NAND gate
as shown in the Fig-1.
BOOLEAN EQUATION:
C = (A/. B/) / = A//+B// = A+B

C/ = (A+B)/
4.3.5 USING NOR AS NOT GATE:

A NOR gate is used as NOT gate by short circuiting the input terminals of the NOR gate as shown in the
Fig-2.
BOOLEAN EQUATION:
(A+A)/ = A/
4.3.6 USING NOR AS OR GATE:

A NOR gate is used as OR gate by connecting NOT gate the output of the NOR gate as shown in the
Fig-2.
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ENGINEERING
BOOLEAN EQUATION:
C = (A+B) / = A/. B/
C/ = (A/. B/) / = A//+B// = A+B
4.3.7 USING NOR AS AND GATE:

A NOR gate is used as AND gate by connecting NOT gates at the input of the NOR gate as shown in Fig2.
BOOLEAN EQUATION:
C = (A/+ B/) / = A//.B// = A.B
4.3.8 USING NOR AS NAND GATE:

A NOR gate is used as NAND gate by connecting NOT gate at the inputs and output of the NOR gate as
shown in the Fig-2.
BOOLEAN EQUATION:
C = (A/+ B/) / = A//.B// = A.B

C/ = (A.B)/ = A/+B/
Fig1: Implementation using NAND Gate

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ENGINEERING
Fig2: Implementation using NOR Gate
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ENGINEERING
4.4
ASSESSMENT SHEET
Name: ___________________________
Reg. No. : ________________________
Date of Lab: _____________________
Lab
Performance
Working
Viva
Total Score in Lab
P a g e | 18

ENGINEERING
Lab 5
Boolean Laws and DeMorgan's Theorem
5.1
OBJECTIVES
Use CMOS logic to verify experimentally several of the rules for Boolean algebra.
Experimentally determine the truth table for circuit with three input variables, and use DeMorgans theorem to prove algebraically whether they are equivalent.
5.2
REFERENCE READING
Floyd, Digital Fundamentals, Chapter 2; Section 4-1 to 4-5.
5.3
MATERIALS NEEDED
4071 QUAD 2-INPUT OR gate
4069 HEX INVERTER
Four LEDS
4081 QUAD 2-INPUT AND gate
Four position DIP switch
Four 1 K resistors
5.4
SUMMARY OF THEORY
Boolean algebra consists of a set of laws that governs logical relationships. Unlike ordinary algebra
where an unknown can take any value, the elements of Boolean algebra are binary variables and can have
only one of two values: 1 and 0 (also called TRUE or FALSE). Variables are typically letters of the
alphabet.
Symbols used in Boolean algebra include the bar, which is the NOT or complement; the connective +;
which implies logical addition and is read "OR"; and the connective. , which implies logical
multiplication and is read "AND." The dot is frequently eliminated when logical multiplication is shown.
Thus A.B is written AB. The basic rules of Boolean algebra are tabulated in Floyd's text and are repeated
here in Table 5-1 for convenience.
In this experiment you will use CMOS logic to become familiar with this important family. There are
several subfamilies of CMOS which have different specifications. The original CMOS family was the
4000A series. Other families include the 54C/74C family, which is functionally and pin-out
compatible with TTL 54/74 series, and the 54HC/74HC, which is functionally and pin-out-compatible
with TTL 54LS / 74LS logic. The 54C/74C series is faster and can sink 50% more current than the
4000A series. Details of these subfamilies can be found in manufacturers' data books.
The key properties of all CMOS are low power dissipation, noise immunity, high fan-out (to other CMOS
devices), and ability to operate from power supplies from 3 V to 15 V. The legal logic levels depend on
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ENGINEERING
the supply voltage. The supply is called either VDD or Vcc, and ground is labeled VSS or GND. Typically,
the legal input voltage levels for 4000A series CMOS are from ground to 30% of Vcc for V IL and from
70% of Vcc to Vcc for VIH.
Table 5-1: Basic rules of Boolean algebra
One disadvantage of CMOS is that it is damaged more easily than TTL. In addition to static handling
precautions listed in Floyd's text, use following operating precautions:
1. Unused inputs must NOT be left open even on gates that are not being used. They should be tied to
Vcc, ground, or an input signal.
2. Power supply voltages must always be on when signal voltages are present at the inputs. Signal
voltage must never exceed the power supply.
3. CMOS devices must never be inserted into or removed from circuits with power on.
5.5
BOOLEAN RULES
1. Prove rule 1 (see Table 5-1) with the circuit of figure 5-1. Use 5.0 V for the power
supply. Set the Generator for a frequency of 10 KHz with a 0 V to 4V level on the
output. On the plot below the figure, sketch the input signal, V in, and the output
signal, Vout . Label both time and voltage on your sketches. To obtain the proper
time relationship between signals, look at both signals at one time on the scope
while triggering on one channel only. Do not use COMP (composite) triggering.
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ENGINEERING
Figure 5-2
2. Change the circuit to that of Figure 5-2. On the plot below the figure, sketch the input and output
signals. Which rule does this circuit illustrate?
Figure 5-2
3. Connect the circuit of Figure 5-3. On the plot below, sketch the input and output signals. Which rule
does this circuit illustrate?
Figure 5-3
4. Design a circuit that illustrates rule 10. Use the signal generator A for a switch (or wire) for B. Show
your circuit design in the provided space. Build the circuit and sketch the A input and the output
signal. Does B affect the output?
Circuit design:
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ENGINEERING
5.5.1 REVIEW QUESTIONS

1. Apply the distributive law and rule 7 to the equation X= A(A+B) + C. Then apply rule 10 to obtain
the equation X = A+C. In the space provided, draw circuit that illustrate each of these expressions.
Prove that these circuits perform equivalent logic.
A( A + B) + C:
A + C:
2. Rule II states that A + B = A + B. In the space provided, draw a circuit that illustrates these
expressions. Prove that these circuits perform equivalent logic.
A + B:
A + B:
3. Rule 6 illustrates that A+ could be replaced with a wire to Vcc. What does rule 8 illustrate?
P a g e | 22

ENGINEERING
4. You are operating 4000A series CMOS from a 12 V power supply.

(a) What is the maximum VIL? ______________
(b) What is the minimum VIH? ______________
5.6
DEMORGAN'S THEOREM
1. Build the circuit shown in Figure 5-4. Test each combination of input variables by closing the
appropriate switches as listed in truth Table 5-2 (0 = closed and 1 = open). Using the LED as a logic
monitor read the output logic and completes the truth table.
+5.0 V
Rs = 1 k
1
4
4071
1
4
4081
X
B
1
4
4069
1
4
4069
1k
Figure 5-4
Table 5-2: Truth table for Figure 5.4
Inputs
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
I
Output
C
0
1
0
1
0
1
0
1
Write the Boolean expression for this circuit:

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ENGINEERING
2. Construct the circuit shown in Figure 5-5. Again test each combination of inputs and complete truth
table 5-3 as before.
+5.0 V
1 4069
4
Rs = 1 k
1
4
4081
1
4
4071
1 4069
4
X
1k
Figure 5-5
Table 5-3 : Truth table for Figure 5.5
Inputs
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
I
Output
C
0
1
0
1
0
1
0
1
Write the Boolean expression for this circuit.
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ENGINEERING
5.6.1 REVIEW QUESTIONS

Determine whether the circuits in Figures 5-4 and 5-5 are equivalent. Then use DeMorgans theorem to
prove your answer algebraically.
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ENGINEERING
5.7
ASSESSMENT SHEET
Name: ___________________________
Reg. No. : ________________________
Date of Lab: _____________________
Boolean Laws
Problem
Number
Lab
Performance
Review Question
Review Question
Working
Viva
Total Score in Lab
P a g e | 26

ENGINEERING
LAB 6
Design & Implementation of half adder & subtractor using
Universal Gates
6.1
OBJECTIVES
To become familiar with the IC 7400 series XOR gate and its Truth
Table.
Use of above IC in implementation of HALF ADDER.
To become familiar with the IC 7400 series NAND gate and its Truth
Table.
To become familiar with the IC 7404 series INVERTER gate and its Truth
Table.
Use of above ICs in implementation of HALF SUBTRACTOR.
6.2
MATERIALS NEEDED
7400 IC XOR gate
7400 IC NAND gate
7404 IC
Connecting Wires
6.3
SUMMARY OF THEORY
The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The
carry signal represents an overflow into the next digit of a multi-digit addition. The value of the sum
is 2C + S. The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and
an AND gate for C. With the addition of an OR gate to combine their carry outputs, two half adders
can be combined to make a full adder.
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ENGINEERING
The half adder adds two input bits and generates a carry and sum, which are the two outputs of a
half adder. The input variables of a half adder are called the augend and addend bits. The output
variables are the sum and carry.
The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has
two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).
An important point worth mentioning is that the half substractor diagram aside implements (b-a) and
not (a-b) as borrow is calculated from equation
This important difference should be noticed.
Verify the gates.

Switch on VCC and apply various combinations of input according to truth table.
6.3.1 HALF ADDER

A half adder has two inputs for the two bits to be added and two outputs one
from the sum S and other from the carry c into the higher adder position. In
half adder circuit, carry signal from the addition of the less significant bits sum
from the XOR Gate the carry out from the AND gate.
A B = S (For Sum)
BOOLEAN EQUATION:
A .B = C (For Carry)
INPUTS
OUTPUT
S=AB
C = A.B

1
1
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0

ENGINEERING
Table 6-1 Truth Table of Half Adder
Figure 6-1 Implementation of Half Adder
6.3.2 HALF SUBTRACTOR

The half subtractor is constructed using XOR & AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference
can be applied using XOR Gate, borrow output can be implemented using an NAND
Gate and an inverter.
BOOLEAN EQUATIONS:
X Y = S (For Difference) X/. Y = B (For Borrow)
INPUTS
OUTPUT
S=XY
B = X/. Y
Table 6-2 Truth Table of Half Subtractor
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ENGINEERING
Figure 6-2 Implementation of Half Subtractor
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ENGINEERING
6.4
ASSESSMENT SHEET
Name: ___________________________
Reg. No. : ________________________
Date of Lab: _____________________
Lab
Performance
Working
Viva
Total Score in Lab
P a g e | 31

ENGINEERING
LAB 7
Design & Implementation of full adder using Universal Gates
7.1
7.2
OBJECTIVES
To use the IC 7400 series NAND gate and its Truth Table.
Use of above ICs in implementation of HALF ADDER.
The two Half Adders can be used to Implement Full Adder.
MATERIALS NEEDED
7400 IC
Connecting Wires
7.3
SUMMARY OF THEORY
A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder
adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit
carried in from the previous less significant stage.
Verify the gates.

Switch on VCC and apply various combinations of input according to truth
table.
7.3.1 FULL ADDER

A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at
a time but a half adder cannot do so. In full adder sum output will be taken from
XOR Gate, carry output will be taken from OR Gate.
BOOLEAN EQUATIONS:
A B Cin = A/B/C+A/BC/+AB/C/+ABC (For Sum)

(A B. Cin). A.B = A.B+B.C+A.C
(For Carry)
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ENGINEERING
INPUTS
OUTPUT
Cin
S = A B Cin
Cout = (A B. Cin).
AB
Table 7-1 Truth Table of Full Adder
F
igure 7-1 Implementation of Full Adder
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ENGINEERING
7.4
ASSESSMENT SHEET
Name: ___________________________
Reg. No. : ________________________
Date of Lab: _____________________
Lab
Performance
Working
Viva
Total Score in Lab
P a g e | 34

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QURTUBA UNIVERSITY OF SCIENCE & IT

EE xxxL DIGITAL LOGIC DESIGN LAB

QURTUBA UNIVERSITY OF SCIENCE & IT

Lab 2 Number Systems

QURTUBA UNIVERSITY OF SCIENCE & IT

Figure 2-1: MANI seven-segment display

CONVERSIONS BETWEEN NUMBER SYSTEMS

EE xxxL DIGITAL LOGIC DESIGN LAB

QURTUBA UNIVERSITY OF SCIENCE & IT

EE xxxL DIGITAL LOGIC DESIGN LAB

QURTUBA UNIVERSITY OF SCIENCE & IT

EE xxxL DIGITAL LOGIC DESIGN LAB

QURTUBA UNIVERSITY OF SCIENCE & IT

1. Convert each number shown into the other bases:

EE xxxL DIGITAL LOGIC DESIGN LAB

QURTUBA UNIVERSITY OF SCIENCE & IT

Total Score in Lab

EE xxxL DIGITAL LOGIC DESIGN LAB

QURTUBA UNIVERSITY OF SCIENCE & IT

LAB 3 Verification of Truth Table, Become Familiar with Different

Vcc=5volts or DC power supply

Advance logic trainer board

Use of 7400 IC:

Use of 7402 IC:

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Use of 7404 IC:

Use of 7410 IC:

Use of 7420 IC:

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Table 3-1 Truth table and pin diagram of 7400 IC

Table 3-2 Truth table and pin diagram of 7402 IC

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Table 3-3 Truth table and pin diagram of 7404 IC

Table 3-4 Truth table and pin

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Table 3-5 Truth table and pin diagram of 7420 IC

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Table 3-2 & 3-3

Total Score in Lab

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LAB 4 To Test the Versatility of Universal Gates

Vcc=5volts or DC power supply

Advance logic trainer board

Verify the gates.

4.3.1 USING NAND AS NOT GATE:

USING NAND AS AND GATE:

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4.3.3 USING NAND AS OR GATE:

C = (A/. B/) / = A//+B// = A+B

4.3.4 USING NAND AS NOR GATE:

C = (A/. B/) / = A//+B// = A+B

4.3.5 USING NOR AS NOT GATE:

4.3.6 USING NOR AS OR GATE:

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4.3.7 USING NOR AS AND GATE:

C = (A/+ B/) / = A//.B// = A.B

4.3.8 USING NOR AS NAND GATE:

C = (A/+ B/) / = A//.B// = A.B