Vijayamangalam 638 056

Subject code/Title: EC6302/ Digital Electronics

UNIT-I
MINIMIZATION TECHNIQUES AND LOGIC GATES
Minimization Techniques: Boolean postulates and laws De-Morgans Theorem
Principle of Duality - Boolean expression - Minimization of Boolean expressions Minterm
Maxterm - Sum of Products (SOP) Product of Sums (POS) Karnaugh map
Minimization Dont care conditions Quine - Mc Cluskey method of minimization.
Logic Gates: AND, OR, NOT, NAND, NOR, ExclusiveOR and ExclusiveNOR
Implementations of Logic Functions using gates, NANDNOR implementations Multi
level gate implementations- Multi output gate implementations. TTL and CMOS Logic and
their Characteristics Tristate gates
PART-A
1. Prove the Boolean theorems X+X=X, X+XY=X ? [may/june 2016]
Proof: x + x = (x + x) 1
1 is the identity for AND
= (x + x) (x + x')
Complement, x + x' = 1
= x + (x x')
OR distributes over AND
=x+0
Complement, x x' = 0
=x
0 is the identity for OR (P2)
Proof: x+xy =(x.1)+xy
=x(1+y)
=x.1
=x
2. Define Noise margin? [may/June 2016]
Noise margin is the maximum external noise voltage added to an input signal that does not cause
an undesirable change in the circuit output.
3. State the advantages of CMOS logic? [April/may 2015]
High input impedance. ...
The outputs actively drive both ways.
The outputs are pretty much rail-to-rail.
CMOS logic takes very little power when held in a fixed state. ...
CMOS gates are very simple.
4. State De Morgans theorems? [May 2012] [April 2010]
De Morgan has suggested two theorems which are extremely useful in Boolean Algebra. The two
theorems are discussed below.
Theorem 1

The left hand side (LHS) of this theorem represents a NAND gate with inputs A and B,
whereas the right hand side (RHS) of the theorem represents an OR gate with inverted inputs.

This OR gate is called as Bubbled OR.

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Table showing verification of the De Morgan's first theorem

Theorem 2

The LHS of this theorem represents a NOR gate with inputs A and B, whereas the RHS
represents an AND gate with inverted inputs.

This AND gate is called as Bubbled AND.

Table showing verification of the De Morgan's second theorem

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5. Application of Gray code? May 2012

1.glitch free circuit
2.asynchronous fifo pointer
3.high speed decode circuit
6. Draw the logic diagram of OR gate using universal gates? Nov 2011

7. What is the complement of F = (A+ BC+ AB) ? (Nov / Dec 08)

F = (A+ BC+ AB)
F = (A+ BC+ AB)' = A'. (BC)'. (AB)'
F = A'. (B'+ C'). (A'+ B')
8. Simplify: Z= X + X'Y [Apr. /May 10]
Z= X + X'Y = X + XY + XY
since X + XY = X
Z= X + Y (X + X')
since X + X' = 1
Z=X+Y
9. State the two canonical forms of Boolean algebra. [Apr. / May 07]
The two canonical forms of Boolean algebra are:
i. Sum of products
ii. Products of Sum
10. Define noise margin?
It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an
undesirable change in the output. It is expressed in milli volts(mV).
11. What is propagation delay?
Propagation delay is the average transition delay time for the signal to propagate from input to
output when the signals change in value. It is expressed in nano seconds(ns).
12. Show that a positive logic NAND gate is a negative logic NOR gate.
Logic expression for NAND gate is F=(X.Y)
F= (X.Y)= X' + Y' DeMorgans theorem
F= X' + Y' is the logic expression for negative logic NOR gate
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13.

Draw the TTL Inverter (NOT) Circuit. [April/May-2012]

14. Mention the important characteristics of digital ICs?

The important characteristics of digital ICs are
1. Fan out
2. Fan In
3. Power dissipation
4. Propagation Delay
5. Noise Margin
6. Operating temperature
7. Power supply requirements
15. Which gates are called as universal gates? What are its advantages?
The NAND and NOR gates are called as the universal gates. These gates are used to perform all
logic operations. (i.e. AND, OR, NOT, EX-OR & EX NOR etc operations. The advantages are:
1. Only one type of gate is required to implement the functions.
2. Minimum number of ICs required.
3. Reduces the printed board size, reduction in costs.
4. As number of ICs reduced the probability of occurrence of troubles becomes less.
16. What is meant by propagation delay? [Apr /May 09]
The propagation delay, or gate delay, is the length of time which starts when the input to a logic
gate becomes stable and valid, to the time that the output of that logic gate is table and valid.
Often this refers to the time required for the output to reach from 10% to 90% of its final output
level when the input changes. Reducing gate delays in digital circuits allows them to process data
at a faster rate and improve overall performance.
17. What are called dont care conditions?
In some logic circuits certain input conditions never occur, therefore the corresponding output
never appears. In such cases the output level is not defined, it can be either high or low. These
output levels are indicated by X or d in the truth tables and are called dont care conditions or
incompletely specified functions.
18. Draw an active-high tri-state buffer and write its truth table. [April/May-2010]
Enable
0
1
1
19.

Input
X
0
1

Output
Z
0
1

What is a totem pole output? [April/May-2011]

Totem pole output is a standard output of a TTL gate. It is specifically designed to reduce the
propagation delay in the circuit and to provide sufficient output power for high fan-out.
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PART-B
1. Express the Boolean function as
1) POS form
2) SOP form
D=(A+B)(B+C)[April/May-2010]
POS form:
Given
D=(A+B)(B+C)
=AB+AC+BB+BC
= AB+AC+BC
= A+B+ AC+BC
= A(1+C)+B+BC
= A+B+BC
D= AB+BC
Using missed terms formulae;
= AB(C+C)+(A+A)BC
= ABC+ ABC+ABC+ABC
D(A,B,C)= m(1,0,7,3)

(4)

D= AB+BC
SOP form:
D(A,B,C)= M(1,0,7,3)

D=(A+B)(B+C)
2. Minimize the given terms M (0, 1, 4, 11, 13, 15) + d (5, 7, 8) using QuineMcClusky methods and verify the results using K-map methods.[April/May2010]
(12)

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Step:1
MINTERM
M0
M1
M4
M11
M13
M15
MD5
MD7
MD8

BINARY NUMBER
0000
0001
0100
1011
1101
1111
0101
0111
1000

MINTERM
0
1
4
D8
D5
11
13
D7
15

BINARY REPRESENTATION
0000
0001
0100
1000
0101
1011
1101
0111
1111

Prime Implicant
0,1
0,4
0,d8
1,d5
4,d5
d5,d7
11,15
13,15
D7,15

Binary representation
0000-00
- 000
001
010-101
01-1
1-11
-111

Prime Implicant
0,1,4,d5
0,4,1,d5
D5,7,d13,15
D5, d7

Binary Representation
0-00-0-1-1

Step:2

Step:3

Step:4

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Step:5

Y=AC+BCD+ABCD+ABCD
3. Implement the following function using NOR gates. [April/May-2010]
Output = 1 when the inputs are m(0,1,2,3,4)
= 0 when the inputs are m(5,6,7) .
Given
F= m(0,1,2,3,4)

Y=A+BC

Given
F= m(0,1,2,3,4)

Y=AC+AB

(8)

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4. Discuss the general characteristic of TTL and CMOS logic families. [April/May2010]
(8)
Characteristic of TTL:
In the input can be left open. It is treated as high input. It is constant, does not depend
on switching speed.
Iron out of TTL is 10.
Less susceptible to noise.
The propagation delay is ions 74 and 74LS.
The power per gate 10mw in 74;2 mw in 74 LS and 4mw in 74 ALS.
Speed power product of figure of fact is 1 in 74 ALS.
Characteristic of TTL:
Input cannot be left open. It has to be connected to 0 or to VDD or to the another input.
Very less, but increase with increase in switching speed.
More susceptible to voice.
The propagation delay is 8ns in silicon gate and 105 min metal gate.
The power per gate is 0.17 mw in silicon gate and 0.1mw in metal gate.
Unique of merit is 1.4 PJ in silicon gate and 10.5 PJ in metal gate.
5. Express the Boolean function F=A+BC in sum of min terms[April/May-2011] (6)
Given
F=A+BC
=A(B+ B)(C+C)+ BC(A+A)
=(AB+A B)(C+C)+BC(A+A)
=ABC+ABC+ABC+ABC+ABC+ABC
= ABC+ABC+ABC+ABC+ABC
F=m1+m4+m5+m6+m7
6. Simplify the Boolean function using K-map. F (w, x , y, z ) = (0, 1, 2, 4, 5, 6, 8, 9,
12, 13, 14 ) [April/May-2011]
(10)

F=Y+WZ+XZ
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7. Draw the schematic and explain the operation of a CMOS inverter. Also explain
its characteristics. [April/May-2011]
(8)

When the input is low, both gates are at zero potential.

The input is at VDD Relative to the source of the P-channel device and at 0v relative
to the source of the n-channel device.
The result is that the P-channel device is turned on and n-channel is turned off.
Under these conditions, there is a low impedance path from VDD to the output and a
very high- impedance path from output to sound.
Therefore, the output voltage approaches the high level VDD under normal learning
conditions.
When the input is high both the gates are at VDD and the situation is reversed.
The P-channel device is off and the n-channel device is on.
the result is that the output approaches the low level of 0v.
8. State and verify DeMorgans Law. [April/May-2012]
(3)
De Morgan suggested two theorems that form important part of Boolean algebra.
They are,
1) The complement of a product is equal to the sum of the complements.
(AB)' = A' + B'
A
0
0
1
1

AB
1
1
1
0

B
0
1
0
1

A+B
1
1
1
0

2) The complement of a sum term is equal to the product of the complements.

(A + B)' = A'B'

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A
0
0
1
1

A+B
1
0
0
0

B
0
1
1
1

A.B
1
0
0
0

9. Simplify the Boolean expression

F=xyz+xyz+xyz+xyz[April/May-2012]
Given
F=xyz+xyz+xyz+xyz
=xyz+xyz+xz(y+y)
=xyz+xyz+xz
=xyz+ z(xy+x)
= xyz+z(x+x)(y+x)
F=xyz+xz+zy
10. Minimize the Function, F using Quine Mcclusky Method.
F= (0,1,2,8,10,11,14,15) [April/May-2012,2013]
Step:1
Group
0
1

2
3
4

Minterm
0
1
2
8
10
11
15

Step:2

10

(5)

(8)

A
0
0
0
1
1
1
1

B
0
0
0
0
0
0
1

C
0
0
1
0
1
1
1

D
0
1
0
0
0
1
1

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Step:3

Step:4

F(A,B,C,D)=ABC+BD+AC
11. Differentiate between Min Term and Max Term.[April/May-2012]
(4)
A product term containing all the variables of the function in either complemented
or uncomplemented form is called a min term.
Y=ABC+BD
A sum term containing all the variables of the function in either complemented or
uncomplemented form is called a max term.
Y=(A+B+C)(B+D)
12. Using Karnaugh map simplify the following expressions and implement using
basic gates. [April/May-2012]
(12)
1) F= (1,3,4,6)
2) F= (1,3,7,11,15)+d(0,2,5)
Given F= (1,3,4,6)

F=AC+AC
Given F= (1,3,7,11,15)+d(0,2,5)
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F=AB+CD
13. Simplify the Boolean function into[April/May-2013]
(i) Sum of product form.
(ii) Product of sum form.
F(A,B,C,D)= (0,1,2,5,8,9,10)
Given F(A,B,C,D)= (0,1,2,5,8,9,10)
(i)
Sum of product form.

F=ABC+ACD+ABC+BCD
(ii)

Product of sum form.

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(8)
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F=(A+B)(C+D)(B+D)
14. Express the Boolean function F=XY+XZ in product of Maxterm.[Nov/Dec-2009]
Given
(6)
F=XY+XZ
=XY(Z+Z)+XZ(X+X)
=XYZ+XYZ+XYZ+XYZ
= m(7,6,3,1)
= m(0,2,4,5)
F=(X+Y+Z)(X+Y+Z)(X+Y+Z)(X+Y+Z)
15. Reduce the following function using K-map technique. [Nov/Dec-2009]
F(A,B,C,D)= (0,3,4,7,8,10,12,14)+d(2,6)
Given F(A,B,C,D)= (0,3,4,7,8,10,12,14)+d(2,6)

(10)

F(A,B,C,D)=D(A+C)
16. Simplify the following Boolean function by using a Quine-McCluskey method.
F (A, B, C, D) = m(0, 2, 3, 6, 7, 8, 10, 12, 13 ) [Nov/Dec-2009]
(16)
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Step:1

Step:2

Step:3

Step:4

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F(A,B,C,D)=ABC+BD+AC
17. Simplify the following Boolean function using 4-variable map
F (w,x,y,z) = ( 2, 3, 10,11,12, 13,14,15) [Nov/Dec-2010]

(8)

Given F (w,x,y,z) = ( 2, 3, 10,11,12, 13,14,15)

F(w,x,y,z)=wx+xy
18. Draw a NAND logic diagram that implements the complement of the following
function.
F (A, B, C, D) = (0,1,2, 3,4,8,9,12) [Nov/Dec-2010]
(8)
Given F (A, B, C, D) = (0,1,2, 3,4,8,9,12)

F=AB+BC+CD
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19. Draw and explain Tri-state TTL inverter circuit diagram and explain its
operation. [Nov/Dec-2014]
(12)
The basic data needed in the analysis of digital circuits may be obtained by inspection
of the typical characteristic curves of a common-emitter npn silicon transistor, shown
in Fig. The circuit is a simple inverter with two resistors and a transistor.
The current marked Ie flows through resistor Rc and the collector of the transistor.
Current Is flows through resistor RB and the base of the transistor.
The emitter is connected to ground. and its current 1 = Ie + te- The supply voltage is
between Vee and ground. The input is between V; and ground, and the output is
between Vo and ground.
We have assumed positive directions for the currents as indicated. These are the
directions in which the currents normally flow in an npn transistor.
Collector and base currents are positive when they flow into the transistor. Emitter
current IE is positive when it flows out of the transistor. as indicated by the arrow in
the emitter terminal.
The symbol Ve stands for the voltage drop from collector to emitter and is always
positive. Correspondingly. VB is the voltage drop across the base-to-emitter junction.
This junction is forward biased when VB is positive and reverse biased when Vs is
negative.

The base-emitter graphical characteristic is shown in Fig (b). Which is a plot of VBE
versus lB' If the base-emitter voltage is less than 0.6 Y, the transistor is said to be cut
off and no base current flows.
When the base-emitter junction is forward biased with a voltage greater than 0.6 V.
the transistor conducts and Ie starts rising very fast where a s VBE changes very little.
The voltage VBE across a conducting transistor seldom exceeds 0.8V.
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UNIT-II
COMBINATIONAL CIRCUITS
Design procedure Half adder Full Adder Half subtractor Full subtractor Parallel
binary adder, parallel binary Subtractor Fast Adder - Carry Look Ahead adder Serial
Adder/Subtractor - BCD adder Binary Multiplier Binary Divider - Multiplexer/
Demultiplexer decoder - encoder parity checker parity generators code converters Magnitude Comparator.
PART-A
1 Write an expression for borrow and difference in a full subtractor circuit.
[April/May-2010]
Difference=AB+AB=AB
Borrow=AB
2 Draw the circuits diagram for 4-bit odd parity generator.[April/May-2010]

Design a single bit magnitude comparator to compare two words A and B.

[April/May-2011]

4 What is an encoder?[May/June-2012]
An encoder has 2n input lines and n output lines. In encoder the output lines generate the
binary code corresponding to the input value.
5 List few applications of multiplexer.[May/June-2012, Nov/Dec-2013]
Data Selector.
Implement combinational logic circuit.
Time multiplexing systems
Frequency multiplexing systems.
D/A and A/D converter
Data acquisition systems.
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6 Design a half subtractor using basic gates.[May/June-2013, Nov/Dec-2010]

Difference=AB+AB=AB
Borrow=AB
7 Draw the logic diagram of a 4 line to 1 line multiplexer. [May/June-2013]

8 What is priority Encoder?[May/June-2014]

A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if 2 or more inputs are equal to 1 at the same time, the input having the
highest priority will take precedence.

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9 Write down the difference between demultiplexer and decoder.[April/May-2015]

Definition

Demultiplexer
1 data input
2^n outputs

Decoder

It has n inputs
2^n outputs
It has n control inputs
Characteristic Connects the data input to Selects one of the 2^n outputs by
the data output
decoding the binary value on the basis of
n inputs
Reverse of
Multiplexer
Encoder

10 Give the logic expression for sum and carry in full adder circuit.[April/May2015]
Sum= (AB)Cin
Carry=AB+BCin+A Cin
11 Give examples for combinational circuit.[April/May-2015, Nov/Dec-2013]
i. Adders
ii. Subtractors
iii. Multiplexers
iv. Demultiplexers
v. Encoders
vi. Decoders
12 Draw the logic circuit of a 2-bit comparator.[April/May-2015,2014]

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13 Suggest a solution to overcome the limitation on the speed of an adder.[Nov/Dec2009]

It is possible to increase speed of adder by eliminating inter-stage carry delay. This
method utilizes logic gates to look at the lower-order bits of the augend and addend to
see if a higher-order carry is to be generated.
14 Relate carry generate, Carry propagate, Sum and Carry-out of a Carry look a
head adder.[Nov/Dec-2010]

15 Realize the Boolean function using appropriate multiplexer F(A,B,C)= (0,1,3,7)

[Nov/Dec-2010]

16 Compare the performance of binary serial and parallel adders.[Nov/Dec-2011]

Serial Adder:
Serial adder uses shift registers
The serial adder requires only one full adder circuit
The serial adder is a sequential circuit
Time required for addition depends on the number of bits
It is slower
parallel adder:
Parallel adder uses registers with parallel load capacity
It is faster
Time required for addition does not depend on number of bits
Excluding the registers, the parallel adder is a purely combinational circuit

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17 Design of three bit parity generator.[Nov/Dec-2012]

Odd parity generator:

Even Parity generator:

18 Draw the logic diagram of serial adder.[Nov/Dec-2012]

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19 Construct a two-4-bit parallel adder/subtractor using Full Adders and XOR

gates. [Nov/Dec-2014]

20 Convert a two-to-four line decoder with enable input to 1X4

Demultiplexer.[Nov/Dec-2014]

PART-B
1. Derive the equation for a 4-bit look ahead carry adder circuit.[April/May2010,2014,2015, Nov/Dec-2009,2010]
Simplest Carry-Lookahead System Recall the following equations from the section on
Adder Circuits:
gi = xiyi
pi = xi yi ti = ai = xi + yi
The transfer signal ti can be used in preference to pi since it is easier and quicker to
generate. Although we will use the signal ti in practice, we shall use pi in the
following since it makes the derivation easier to understand. The carry-lookahead
system is obtained by unwinding the recurrence relation for ci+1:
ci = gi1 + ci1
pi1 = gi1 + (gi2 + ci2pi2)
pi1 = gi1 + gi2pi1 + ci2pi2pi1 ...
= gi1 + gi2pi1 + gi3pi2pi1 + gi4pi3pi2pi1 + ci4pi4pi3pi2pi1 We
could continue unrolling until the entire adder length is covered, i.e. until we reach
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cin, but the fan-in of the gates grows linearly with the number of stages covered by
them. Fan-in much greater than 4 is impractical for single CMOS gates because of
poor noise immunity, poor rise and fall times, and therefore poor delay. For most
implementations, we stop at carry-lookahead blocks of size 4. Recall, in the
following, ti can be used in place of pi.
c4 = g3 + g2p3 + g1p2p3 + g0p1p2p3 + c0p0p1p2p3
c3 = g2 + g1p2 + g0p1p2 + c0p0p1p2
c2 = g1 + g0p1 + c0p0p1
c1 = g0 + c0p0
The carry propagate (Pi) and carry generate (Gi) variables are shown on the full adder
logic circuit.
The carries C1, C2, and C3 can be expressed in SOP form as functions of C0 and the
different (Pi) and (Gi) as follows: complete 4-bit CLA adder.
On the right of the drawing are the logic diagrams of the two blocks that generate the
p, t and sum signals. Each lower block combines the ci signal with ti and gi to give the
sum output.
zi = xi yi ci
= pi ci
= giti ci x1 y1 z1 t 1 g1 x0 y0 z0 t 0 g0 x2 y2 z2 t 2 g2 x3 y3 z3 t 3 g3
cin c0 = cin c1 c2 c3
cout = c4 CLA-4
If implemented strictly as implied, the delay through the carry-lookahead block will
be just 2D, but note that the AND gate in two of the equations has a fan-in of 4, and
there are OR gates with fan-ins of 2,3,4, and 5.
Fortunately we dont need the carry-out signal c4. If CLA blocks larger than size 4 are
needed, then the 2 levels of the CLA become 4 levels or more in order to preserve the
fain-in of 4.
We shall need two additional signals, the block propagate signal P and the block
generate signal G. Think of these as the result of combining 4 neighboring bits of the
adder into one HEX digit. Each HEX digit can generate or propagate a carry
G = g3 + g2p3 + g1p2p3 + g0p1p2p3
P = p3p2p1p0
These block propagate and generate signals can be combined in groups of four by
using a second level CLA-4 block.

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2. Draw and explain the block diagram of a 4-bit serial adder to add the contents of
two registers. [April/May-2010]

A and B are the two different digit which is added with carry Cin.
A3A2A1A0 and B3B2B1B0, we add two figures at a time starting with the least
significant pair, and so on.
First, we do A0 + B0 = S0. Second, we do A1 + B1 + carry = S1, and so on; where the S
figures represent the sum: A + B = S.
Notice that in the operation A1 + B1 + carry = S1, carry is not one of the inputs being
added; the inputs being added are A1 and B1.
Furthermore, the value of carry does not depend on the inputs A1 and B1. Carry is
simply a given condition, the consequence of something that happened in the past;
namely, A0 + B0.

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The sum is given by S and carry is given by c. This addition method is shifting and
adding with the values.
Then the shifted and added values are given to the next input as C1.

3. Multiply(1011)2 by (1101)2 using addition and shifting operation also draw the
block diagram of the 4-bit by 4-bit parallel multiplier. [April/May-2010]
2BINARY MULTIPLIER:
Multiplication of binary numbers is performed in the same way as in decimal numbers
partial product: the multiplicand is multiplied by each bit of the multiplier starting
from the least significant bit

Multiplication of two bits = A * B (AND)

0*0=00*1=01*0=01*1=1
2-BIT BY 2-BIT BINARY MULTIPLIER:

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4-BIT BY 3-BIT BINARY MULTIPLIER:

1 0 1 1
1 1 0 1
1 0 1 1
0 0 0
1 0 1 1
1 0 1 1
10 0 0 1 1 11

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4. Design and implement the conversion circuits for binary code to gray code.
[April/May-2010,2014,2015]
Binary Coded Decimal (BCD) is a way to store the decimal numbers in binary form.
The number representation requires 4 bits to store every decimal digit (from 0 to 9).
Since there are 10 different combinations of BCD, we need at least a 4-bit Gray
Code to create sufficient number of these combinations.

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5. Design a full adder using two half adders and an OR gate. [April/May-2011]
Sum= ABC
Carry= AB+BC+CA

6. Explain the operation of a BCD adder. [April/May-2011,2012,2013,2015,

Nov/Dec-2012]
BCD or BINARYCoded Decimal is that number system or code which has
theBINARY numbers or digits to represent a decimal number.
A decimal number contains 10 digits (0-9). Now the equivalentBINARY numbers can
be found out of these 10 decimal numbers. In case of BCD theBINARY number
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formed by fourBINARY digits, will be the equivalent code for the given decimal
digits. In BCD we can use the binary number from 0000-1001 only, which are the
decimal equivalent from 0-9 respectively. Suppose if a number have single decimal
digit then its equivalent Binary Coded Decimal will be the respective four binary
digits of that decimal number and if the number contains two decimal digits then its
equivalent BCD will be the respective eight binary of the given decimal number. Four
for the first decimal digit and next four for the second decimal digit. It may be cleared
from an example.
Let, (12)10 be the decimal number whose equivalent Binary coded decimal will be
00010010. Four bits from L.S.B is binary equivalent of 2 and next four is the binary
equivalent of 1.
Table given below shows the binary and BCD codes for the decimal numbers 0 to 15.
From the table below, we can conclude that after 9 the decimal equivalent binary
number is of four bit but in case of BCD it is an eight bit number. This is the main
difference between Binary number and binary coded decimal. For 0 to 9 decimal
numbers both binary and BCD is equal but when decimal number is more than one bit
BCD differs from binary.

Decimal number

BINARYnumber

BINARYCoded Decimal(BCD)

0000

0000

0001

0001

0010

0010

0011

0011

0100

0100
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0101

0101

0110

0110

0111

0111

1000

1000

1001

1001

10

1010

0001 0000

11

1011

0001 0001

12

1100

0001 0010

13

1101

0001 0011

14

1110

0001 0100

15

1111

0001 0101

BCD Addition
Like other number system in BCD arithmetical operation may be required. BCD is a
numerical code which has several rules for addition. The rules are given below in
three steps with an example to make the idea of BCD Addition clear.
a) At first the given number are to be added using the rule ofBINARY. For example,

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b) In second step we have to judge the result of addition. Here two cases are
shown to describe the rules of BCD Addition. In case 1 the result of addition
of twoBINARY number is greater than 9, which is not valid for BCD
number. But the result of addition in case 2 is less than 9, which is valid for
BCD numbers.
c) If the four bit result of addition is greater than 9 and if a carry bit is
present in the result then it is invalid and we have to add 6 whoseBINARY
equivalent is (0110)2 to the result of addition. Then the resultant that we
would get will be a validBINARY coded number. In case 1 the result was
(1111)2, which is greater than 9 so we have to add 6 or (0110)2 to it.(1111)2
+ (0110)2 = 0001 0101 = 15. As you can see the result is valid in BCD.But in
case 2 the result was already valid BCD, so there is no need to add 6. This is
how BCD Addition could be.
Now a question may arrive that why 6 is being added to the addition result in
case BCD Addition instead of any other numbers. It is done to skip the six
invalid states ofBINARY coded decimal i.e from 10 to 15 and again return
to the BCD codes.
Now the idea of BCD Addition can be cleared from two more examples.
Example:1 Let 0101 is added with 0110.

7. Draw the logic diagram of a 2-bit by 2-bit binary multiplier and explain its
operation. [April/May-2011,Nov/Dec-2010]
2-BIT BY 2-BIT BINARY MULTIPLIER:

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2BINARY MULTIPLIER:
Multiplication of binary numbers is performed in the same way as in decimal numbers
partial product: the multiplicand is multiplied by each bit of the multiplier starting
from the least significant bit.
8. Implement the following function using suitable multiplexer. [April/May2011,2015]
F(A,B,C,D)= (1,3,4,11,12,13,14,15)

9. Design a 4-bit word comparator, so that the output follows the table 1.
[April/May-2011,2013,2015, Nov/Dec-2011,2013]
Table 1
Word Output
A=B
100
A>B
010
A<B
001

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10. Design a 3:8 decoder using basic gates. [April/May-2014, Nov/Dec-2011]

11. Design a full subtractor using demultiplexer. [April/May-2014,Nov/Dec-2009]

12. Implement the given Boolean function using 8:1 multiplexer

F(A,B,C)= (1,3,5,6)

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13. Define Fan-in, Fan-out and Noise margin.[Nov/Dec-2010]

Noise Margin.
The voltage difference between the lowest possible HIGH output, VOH

(min)

and the

minimum input voltage, VIH (min) required for a HIGH input is called High-state noise
margin.

The voltage difference between the largest possible LOW output, VOL (max) and

the maximum voltage, VIL

(max)

required for a LOW input is called Low-state noise

margin.

The noise margin allows the digital circuit to function properly if noise voltages

are within the noise margin.

Fan-out of a gate
It is the maximum number of inputs of the same family that the gate can drive
maintaining its output levels within the specified limits.
For example: If an inverters output can drive maximum 10 inputs of any logic gates from
same family, the fan-out of the inverter is 10.
Fan-in of a gate
Fan-in of a gate is said to be the number of inputs in a digital logic gate.
For example: 2 input NOR has Fan-in of 2.
14. Design 4:1 Encoder using basic gates.[Nov/Dec-2011]

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UNIT-III
SEQUENTIAL CIRCUITS
Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation
Application table Edge triggering Level Triggering Realization of one flip flop using
other flip flops serial adder/subtractor- Asynchronous Ripple or serial counter
Asynchronous Up/Down counter - Synchronous counters Synchronous Up/Down counters
Programmable counters Design of Synchronous counters: state diagram- State table
State minimization State assignment Excitation table and maps-Circuit implementation Modulon counter, Registers shift registers - Universal shift registers Shift register
counters Ring counter Shift counters - Sequence generators.
PART-A
1. Mention any two differences between the edge triggering and level triggering.
[April/May-2010]
Level Triggering:
1) The input signal is sampled when the clock signal is either HIGH or LOW.
2) It is sensitive to Glitches.
Example: Latch.
Edge Triggering:
1) The input signal is sampled at the RISING EDGE or FALLING EDGE of the clock
signal.
2) It is not-sensitive to Glitches.
Example: Flipflop.
2. What is meant by programmable counter? Mention its application. [April/May-2010]
A counter that divides an input frequency by a number which can be programmed into de
cades of synchronous down counters.
Decades, with additional decoding and control logic, give the equivalent of a divide-by
N counter system, where N can be made equal to any number.
Appication:
Microprocessor.
Traffic light controller.
Street light controller.
3. Write the characteristic equation of a JK flip-flop. [April/May-2011, Nov/Dec-2009]
The characteristic equation of a JK flip-flop is given by
Q(next) = JQ' + K'Q
4. State the differences between Moore and mealy state machine. [April/May2011,Nov/Dec-2010,2011]
1)Mealy Machines tend to have less states
a) Different outputs on arcs (n^2) rather than states (n).
2) Moore Machines are safer to use
a) Outputs change at clock edge (always one cycle later).
b) In Mealy machines, input change can cause output change as soon as logic is done a big
problem when two machines are interconnected asynchronous feedback.
3) Mealy Machines react faster to inputs
b) React in same cycle don't need to wait for clock.
c) In Moore machines, more logic may be necessary to decode state into outputs more gate
delays after.

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5. Realise T-FF from JK-FF. [April/May-2012]

6. Convert JK flip-flop to T flip-flop. [April/May-2013, 2012]

7. How many flip-flops are required to build a binary counter that counts from 0 to
1023? [April/May-2013]
If the number of flip-flops required is n, then
2n-1=1023 n=10 since 210=1024
8. Compare the logics of synchronous counter and ripple counter. [April/May-2014,
Nov/Dec-2009]
Asynchronous counter:
1. In this type of counter flipflop are connected in such a way that output of first
flip-flop drives the clock for next flip-flop.
2. All the flip-flop are not clocked simultaneously.
3. Logic circuit is very simple even for more number of states.
synchronous counter:
1. In this type there is no connection between output of first flip-flop and clock
input of the next flip-flop.
2. All the flip-flop are clocked simultaneously.
3. Design involves complex logic circuit as number of states increases.
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4.
9. Sketch the logic diagram of a clocked SR flip-flop. [April/May-2014]

10. How do you eliminate the race around condition in a JK flip-flop?[Nov/Dec2010]

When the input to the JK flip-flop is j=1 and k=1, the race around condition occurs, i.e
it occurs when the time period of the clock pulse is greater than the propagation delay
of the flip flop.
the output changes or toggles in a single clock period. If it toggles even number of
times the output is same but if it toggles odd number of times then the output is
complimented.
To avoid race around condition we cant make the clock pulse smaller than the
propagation delay so we use
1. Master slave JK flip flop
2. Positive or negative edge triggering
11. Draw the state table and excitation table of T flip-flop. [Nov/Dec-2010]

12. A 4-bit binary ripple counter is operated with clock frequency of 1KHz. What is
the output frequency of its third Flip flop? [Nov/Dec-2011]
The output frequency of third flip-flop is:
3=1/8KHz.
13. Realize JK flip-flop using D flip-flop. [Nov/Dec-2011]

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14. Design a 3-bit ring counter and find the mod of the designed counter. [Nov/Dec2012]

15. Define latches. [Nov/Dec-2013]

Latch is a simple memory element, which consists of a pair of logic gates with their
inputs and outputs inter connected in a feedback arrangement, which permits a single
bit to be stored.
16. Write short notes on Digital Clock. [Nov/Dec-2013]
A digital clock is a simplified logic diagram of a digital clock that displays seconds,
minutes, and hours. First, a 60 Hz sinusoidal ac voltage is converted to a 60 Hz pulse
waveform and divided own to a 1Hz pulse waveform by a divide-by-60 counter
formed by a divide-by-10 counter allowed by a divide-by-6 counter. Both the seconds
and minutes counts are also produced by divide-by-60 counters.

PART-B
1.

Construct a clocked JK flip-flop which is triggered at the positive edge of the

clock pulse from a clocked SR flip-flop consisting of NOR gates.[April/May-2010,
Nov/Dec-2013]

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2.

Write down the characteristic table for the JK flip-flop with NOR gates.
[April/May-2010]

3.

What is meant by universal counter? Explain the principles of operation of 4-bit

universal shift register. [April/May-2011]
A unidirectional shift register is a register that can capable of transferring data in only
one direction. Whereas the register that is capable of transferring data in both left and
right direction is called a bidirectional shift register. Now let we have a register
which can capable to transfer data in both the shift-right and shift-left, along with the
necessary input and output terminals for parallel transfer, then it is called a shift
register with parallel load or universal shift register.
4-Bit Bidirectional Universal Shift Registers (74HC194):
The 74HC194 is a universal bi-directional shift register. It has both serial and parallel
input and output capability.

Operating Mode

S1

S0

Locked

Shift-Right

Shift-Left

Parallel Loading

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A universal shift register is an integrated logic circuit that can transfer data in three
different modes. Like a parallel register it can load and transmit data in parallel. Like
shift registers it can load and transmit data in serial fashions, through left shifts or
right shifts.
In addition, the universal shift register can combine the capabilities of both parallel
and shift registers to accomplish tasks that neither basic type of register can perform
on its own. For instance, on a particular job a universal register can load data in series
(e.g. through a sequence of left shifts) and then transmit/output data in parallel.
Universal shift registers, as all other types of registers, are used in computers as
memory elements. Although other types of memory devices are used for the efficient
storage of very large volume of data, from a digital system perspective when we say
computer memory we mean registers. In fact, all the operations in a digital system are
performed on registers. Examples of such operations include multiplication, division,
and data transfer.
In order for the universal shift register to operate in a specific mode, it must first
select the mode. To accomplish mode selection the universal register uses a set of two
selector switches, S1 and S0. As shown in Table 1, each permutation of the switches
corresponds to a loading/input mode.
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4.

Convert D flip-flop to T flip-flop. [April/May-2011]

5.

Design serial binary adder. [April/May-2011]

The serial
binary
adder or bit-serial
adder is
a digital
circuit that
performs binary addition bit by bit. The serial full adder has three single-bit inputs
for the numbers to be added and the carry in.
There are two single-bit outputs for the sum and carry out. The carry-in signal is the
previously calculated carry-out signal.
The addition is performed by adding each bit, lowest to highest, one per clock cycle.
A two bit serial binary adder is shown in figure,

It has X and Y two digits binary values. It produces sum and Cout as output.
If speed is not of great importance, a cost-effective option is to use a serial adder
Serial adder: bits are added a pair at a time (in one clock cycle)
A=an-1an-2a0, B=bn-1bn-2b0

In serial binary adder shifting and adding is the main operation for adding two binary
numbers.
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6.

Explain the operation of a BCD ripple counter with JK flip-flops. [April/May2011,2012,April/May-2013,Nov/Dec-2009]

Synchronous counter: The CP signals of all flipflops are from the common clock.
Ripple counter: the CP of some flip-flops are from other flip-flops.
Ripple counter is asynchronous
Binary ripple (up) counter
Binary ripple down counter
BCD Ripple Counter
Verify the following circuit is a BCD Ripple counter triggered by negative edge.

Consist of a series of connection of negative edge triggering complementing flip-flops

with the output of each flip-flop connected to the C input of the next high order flip
flop.
The flip flop holding the LSB receives the input pulses.
The count starts with binary 0 and increments by one with each count pulse input
After the count 15 the counter goes back to binary 0 to repeat the count
For positive edge triggered flip-flops the counter count down:
e.g start from15 to 14 to 13 to.
The diagram is same as the count up binary counter except that the flip-flop trigger
on the positive edge of the clock.
If negative edge triggered flip-flops are used then the C input of each flip-flop must
be connected to the complement output of the previous flip-flop. So, when the true
output goes from 0 to 1, the complement will go from 1 to o and complement the next
flip flop as required.

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This counter counts upwards on each negative edge of the input clock signal starting
from "0000" until it reaches an output "1001. Both outputs Q A and Q D are now
equal to logic "1" and the output from the NAND gate changes state from logic "1" to
a logic "0" level when the clock goes to level one and whose output is also connected
to the CLEAR (CLR) inputs of all the J-K Flip-flops.

7.

Explain the operation of shift and ring counters. [April/May-2012]

If the output of a shift register is fed back to the input. a ring counter results. The data
pattern contained within the shift register will recirculate as long as clock pulses are
applied. For example, the data pattern will repeat every four clock pulses in the figure
below. However, we must load a data pattern. All 0s or all 1s doesnt count.

We make provisions for loading data into the parallel-in/ serial-out shift register
configured as a ring counter below. Any random pattern may be loaded. The most
generally useful pattern is a single 1.

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LoadingBINARY 1000 into the ring counter, above, prior to shifting yields a
viewable pattern. The data pattern for a single stage repeats every four clock pulses
in our 4-stage example. The waveforms for all four stages look the same, except for
the one clock time delay from one stage to the next. See figure below.

The circuit above is a divide by 4 counter. Comparing the clock input to any one of
the outputs, shows a frequency ratio of 4:1. How may stages would we need for a
divide by 10 ring counter? Ten stages would recirculate the 1 every 10 clock
pulses.

An alternate method of initializing the ring counter to 1000 is shown above. The
shift waveforms are identical to those above, repeating every fourth clock pulse.
The requirement for initialization is a disadvantage of the ring counter over a
conventional counter. At a minimum, it must be initialized at power-up since there
is no way to predict what state flip-flops will power up in. In theory, initialization
should never be required again. In actual practice, the flip-flops could eventually be
corrupted by noise, destroying the data pattern. A self correcting counter, like a
conventional synchronous BINARY counter would be more reliable.
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The above BINARY synchronous counter needs only two stages, but requires
decoder gates. The ring counter had more stages, but was self decoding, saving the
decode gates above. Another disadvantage of the ring counter is that it is not self
starting. If we need the decoded outputs, the ring counter looks attractive, in
particular, if most of the logic is in a single shift register package. If not, the
conventional BINARY counter is less complex without the decoder.

8.

The waveforms decoded from the synchronous binary counter are identical to the
previous ring counter waveforms. The counter sequence is (QA QB) = (00 01 10
11).
Draw the Schematic diagram of up/down counter and explain its operations.
[April/May-2013]
A circuit of a 3-bit synchronous up-down counter and a table of its sequence. Similar
to an asynchronous up-down counter, a synchronous up-down counter also has an updown control input. It is used to control the direction of the counter through a certain
sequence.

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An examination of the sequence table shows:

for both the UP and DOWN sequences, Q0 toggles on each clock pulse.
for the UP sequence, Q1 changes state on the next clock pulse when Q0=1.
for the DOWN sequence, Q1 changes state on the next clock pulse when Q0=0.
for the UP sequence, Q2 changes state on the next clock pulse when Q0=Q1=1.
for the DOWN sequence, Q2 changes state on the next clock pulse when Q0=Q1=0

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UNIT-IV
MEMORY DEVICES
PART-A
1. What is meant by memory Expansion? Mention its limit. [April/May-2010]
The memory expansion can be achieved in two ways: by expanding word size and
expanding memory capacity.
Limitations:
1. Memory capacity upto 16Mbytes.
2. 24 address lines and 16 data lines.
2. What are the advantages of static RAM and Dynamic Ram? [April/May2010,Nov/Dec-2009]
Static RAM:
Access time is less.
Fast operation.
Dynamic Ram
It consumes less power.
Cost is low.
3. What is difference between PAL and PLA? [April/May-2011, 2013, Nov/Dec2010]
PLA:
Both AND and OR arrays are programmable and Complex
Costlier than PAL
PAL:
AND arrays are programmable OR arrays are fixed
Cheaper and Simpler
4. Implement the exclusive or function using ROM. [April/May-2011]
Can implement multi-input/multi-output logic functions inside of ROM.
Data outputs are the logic functions and the address lines are the logic function
inputs.
We create a ROM Table to store the logic functions.
When an input (or address) is presented, the value stored in the specified memory
location appears at the data outputs.
Each data output represents the correct value for its logic function

5. Compare Dynamic RAM with Static RAM. [April/May-2012]

Static Ram is very costly.
Dynamic Ram is cheaper.
Static Ram contains Transistors.
Dynamic Ram contains Capacitors.
Static Ram is used in L1 and L2 cache.
Dynamic Ram is used in system RAM.
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6. Mention few applications of PLA and PAL. [April/May-2012]

Implement combinational circuits
Implement sequential circuits
Code converters
Microprocessor based systems
7. What are the different types of programmable logic devices? [April/May-2013]
PROM
PLA
PAL
GAL
8. Draw the structure of a static RAM cell. [April/May-2014]

9. List the advantages of PLDs. [April/May-2014, Nov/Dec-2010]

low and fixed (two gate) propagation delays (typically down to 5 ns),
simple,
low-cost (free),
design tools.
10. What is PAL? [Nov/Dec-2009]
PAL is programmable array logic, PAL consists of a programmable AND array and a
fixed OR array with output logic.
11. What is access time and cycle time of a memory? [Nov/Dec-2010]
Access time is the maximum specified time within which a valid new data is put on
the data bus after an address is applied.
Cycle time is the minimum time for which an address must be held stable on the
address bus in read cycle.
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12. Implement a 2-bit multiplier using ROM. [Nov/Dec-2010]

13. How the memories are classified?

It is classified into two types:
volatile
non-volatile memory
14. Draw the logic diagram of a static RAM cell and Bipolar cell. [Nov/Dec-2012]

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15. What is volatile and non-volatile memory? [Nov/Dec-2013]

The memory which cannot hold the data when power is turned off is known as
volatile memory.
The memory which can hold the data when power is turned off is known as nonvolatile memory
16. Give the advantages of RAM. [Nov/Dec-2013]
Read and write the data.
Data is accessed by using address of the memory location.
Higher speed.
PART-B
1. Explain the principle of operation of bipolar SRAM cell. [April/May-2010]
SRAM Basics The memory circuit is said to be static if the stored data can be retained
indefinitely, as long as the power supply is on, without any need for periodic refresh
operation.

The data storage cell, i.e., the one-bit memory cell in the static RAM arrays,
invariably consists of a simple latch circuit with two stable operating points.
Depending on the preserved state of the two inverter latch circuit, the data being held
in the memory cell will be interpreted either as logic '0' or as logic '1'.
To access the data contained in the memory cell via a bit line, we need atleast one
switch, which is controlled by the corresponding word line.
CMOS SRAM Cell
A low power SRAM cell may be designed by using cross-coupled CMOS inverters.
The most important advantage of this circuit topology is that the static power
dissipation is very small; essentially, it is limited by small leakage current.
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Other advantages of this design are high noise immunity due to larger noise margins,
and the ability to operate at lower power supply voltage. The major disadvantage of
this topology is larger cell size.
The memory cell consists of simple CMOS inverters connected back to back, and two
access transistors. The access transistors are turned on whenever a word line is
activated for read or write operation, connecting the cell to the complementary bit line
columns.

READ Operation:
Consider a data read operation, assuming that logic '0' is stored in the cell.
The transistors M2 and M5 are turned off, while the transistors M1 and M6
operate in linear mode. Thus internal node voltages are V1 = 0 and V2 = VDD
before the cell access transistors are turned on.
WRITE Operation:
Consider the write '0' operation assuming that logic '1' is stored in the SRAM cell
initially.
The voltage levels in the CMOS SRAM cell at the beginning of the data write
operation. The transistors M1 and M6 are turned off, while M2 and M5 are
operating in the linear mode.
Thus the internal node voltage V1 = VDD and V2 = 0 before the access
transistors are turned on. The column voltage Vb is forced to '0' by the write
circuitry. Once M3 and M4 are turned on, we expect the nodal voltage V2 to
remain below the threshold voltage of M1.
2. Write a note on SRAM based FPGA. [April/May-2010]

Static memory is the most widely used method of configuring FPGAs. In this section
we will look at the elements of an FPGA: logic, interconnect, and I/O.

In doing so we will consider both general principles and specific commercial FPGAs.

SRAM-based FPGAs hold their configurations in static memory (though as we will

see in Section 3.6 they dont use the same circuits as are used in commodity SRAMs).

The output of the memory cell is directly connected to another circuit and the state of
the memory cell continuously controls the circuit being configured.

Using static memory has several advantages:

The FPGA can be easily reprogrammed. Because the chips can be reused, and
generally reprogrammed without removing them from the circuit, SRAM-based FPGAs are
the generally accepted choice for system prototyping.
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The FPGA can be reprogrammed during system operation, providing dynamically

reconfigurable systems.

The circuits used in the FPGA can be fabricated with standard VLSI processes.

Dynamic RAM, although more dense, needs to be refreshed, which would make the
configuration circuitry much more cumbersome. SRAM-based FPGAs also have some
disadvantages:

The SRAM configuration memory burns a noticeable amount of power, even when
the program is not changed.

The bits in the SRAM configuration are susceptible to theft. A large number of bits
must be set in order to program an FPGA. Each combinational logic element requires many
programming bits and each programmable interconnection point requires its own bit.
3. Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and
generates an output binary number equal to the square of the input number.
[April/May-2011]

3. Briefly explain the EPROM and EEPROM technology. [April/May-2011]

An EEPROM or EPROM transistor is used as a programmable switch for CPLDs (and
also for many SPLDs) by placing the transistor between two wires in a way that
facilitates implementation of wired-AND functions.
This is illustrated in Figure 4, which shows EPROM transistors as they might be
connected in an AND-plane of a CPLD.
An input to the AND-plane can drive a product wire to logic level 0 through an
EPROM transistor, if that input is part of the corresponding product term. For inputs
that are not involved for a product term, the appropriate EPROM transistors are
programmed to be permanently turned off.
A diagram for an EEPROM based device would look similar. Although there is no
technical reason why EPROM or EEPROM could not be applied to FPGAs, current
commercial FPGA products are based either on SRAM or anti-fuse technologies, as
discussed below.

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An example of usage of SRAM-controlled switches is illustrated in Figure 5, showing

two applications of SRAM cells: for controlling the gate nodes of pass-transistor
switches and to control the select lines of multiplexers that drive logic block inputs.

The figures gives an example of the connection of one logic block (represented by the
AND-gate in the upper left corner) to another through two pass-transistor switches,
and then a multiplexer, all controlled by SRAM cells.
Whether an FPGA uses pass-transistors or multiplexers or both depends on the
particular product. The other type of programmable switch used in FPGAs is the
antifuse. Antifuses are originally open-circuits and take on low resistance only when
programmed.

Antifuses are suitable for FPGAs because they can be built using modified CMOS
technology. As an example, Actels antifuse structure, known as PLICE [Ham88]..
The figure shows that an antifuse is positioned between two interconnect wires and
physically consists of three sandwiched layers:

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The top and bottom layers are conductors, and the middle layer is an insulator. When
unprogrammed, the insulator isolates the top and bottom layers, but when
programmed the insulator changes to become a low-resistance link.
EPROM (Erasable Programmable Read Only Memory) was a great invention that
allowed hardware programmers to make changes to their code without buying new
chips.
The technology that preceded EPROM did not allow the data to be changed.
EPROMS allow them to fully deploy their program on the chip then test it, once
bugs are found they can erase the EPROM then load a modified version for further
testing.
Erasure of data is done by exposing the little window on its top side to ultraviolet
light.
Although EPROM was a great advancement in technology, the erasure method still
left some people wanting more.
Exposing the window to light for a period of time meant that you would have to
remove the chip and it would not be usable until the data is fully erased. There is
also no possibility of having the data replaced by the end user.
These problems led to the development of a version of EPROM that is much easier
to use.
4. With the logic diagram explain the basic macrocell. [April/May-2012]
A macrocell array is an approach to the design and manufacture of ASICs.
Essentially, it is a small step up from the otherwise similargate array, but rather than
being a prefabricated array of simple logic gates, the macrocell array is a prefabricated
array of higher-level logic functions such as flip-flops, ALU functions, registers, and
the like. These logic functions are simply placed at regular predefined positions and
manufactured on a wafer, usually called master slice. Creation of a circuit with a
specified function is accomplished by adding metal interconnects to the chips on the
master slice late in the manufacturing process, allowing the function of the chip to be
customised as desired.
Macrocell array master slices are usually prefabricated and stockpiled in large
quantities regardless of customer orders. The fabrication according to the individual
customer specifications may be finished in a shorter time compared with standard cell
or full custom design. The macrocell array approach reduces themask costs since fewer
custom masks need to be produced. In addition manufacturing test tooling lead time
and costs are reduced since the same test fixtures may be used for all macrocell array
products manufactured on the same die size.
Drawbacks are somewhat low density and performance than other approaches to
ASIC design. However this style is often a viable approach for low production
volumes.
A standard cell library is sometimes called a "macrocell library".
Each section of an SPLD is called a macrocell. A macrocell is a circuit that contains a
sum-ofproducts combinational logic function and an optional flip-flop.

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5. Design 32X8 ROM. [April/May-2013]

6. Discuss the classification of memories. [April/May-,2012,2013,2015]

Random Access Memory (RAM)
Read Only Memory (ROM)
Random Access Memory (RAM)
Can be written to or read from.
Read/Write memory
Reading from RAM is non-destructive.
Access time to read from any memory location is the same.
As compared to serial access memory.
Volatile
Information is lost when power is removed.
Static Random Access Memory (SRAM)
Based on the Flip-Flop
Requires a large number of transistors
Fast
Dynamic Random Access Memory (DRAM)
Uses a single transistor to store charge
Requires very few transistors
Must be periodically refreshed
Slow(er)
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Read Only Memory (ROM)

Can only be read from.
Memory is written (or programmed) once
Reading from ROM is non-destructive.
Access time to read from any memory location is the same.
As compared to serial access memory.
Non-Volatile
Information is retained even after power is removed.
Programmable Read Only Memory (PROM)
Can be programmed
Erasable PROM (EPROM)
Can be programmed and erased
Electrically Erasable PROM (EEPROM)
Can be erased using an electrical signal
UV Erasable PROM (UVEPROM)
Can be erased using Ultraviolet light
Address
Location in memory of the binary information
Must be decoded to select the appropriate location and read/write the
associated data
k-bit address 2k memory locations
Data
Binary information of interest
Stored in a specific location in the memory
Typically organized into words
Each word has n bits

Read
Indicates that the memory is to be read
Write
Indicates that the memory is to be written
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Rather than use the Read and Write signals, most commercially available RAM chips
use Enable and Read/Write'
Enable
Used to enable the selected RAM chip
Aka. chip select

Read/Write'
RAM is read when Read/Write' = 1
RAM is written when Read/Write' = 0
7. Discuss in detail about the FPGA with suitable diagrams. [April/May-2013,2015]

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In an FPGA logic blocks are implemented using multiple level low fan-in gates,
which gives it a more compact design compared to an implementation with two-level
AND-OR logic. FPGA provides its user a way to configure:
1. The intersection between the logic blocks and
2. The function of each logic block. Logic block of an FPGA can be configured in
such a way that it can provide functionality as simple as that of transistor or as
complex as that of a microprocessor. It can used to implement different combinations
of combinational and sequential logic functions.
Logic blocks of an FPGA can be implemented by any of the following:
1. Transistor pairs
2. combinational gates like basic NAND gates or XOR gates
3. n-input Lookup tables
4. Multiplexers
5. Wide fan-in And-OR structure. Routing in FPGAs consists of wire segments of
varying lengths which can be interconnected via electrically programmable switches.
Density of logic block used in an FPGA depends on length and number of wire
segments used for routing. Number of segments used for interconnection typically is a
trade-offs between density of logic blocks used and amount of area used up for
routing.

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UNIT-V
SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS
PART-A
1. Draw the block diagram for Moore model. [April/May-2010, 2012]

2. What are hazard free digital circuits? [April/May-2010]

A circuit which has no hazard like static-0-hazard and static-1-hazard is called hazard
free digital circuit.
3. What are the basic building blocks of a algorithmic state machine chart?
[April/May-2011]

4. What are the two types of asynchronous sequential circuits? [April/May-2011]

Fundamental mode circuit
Pulse mode circuit
5. What is state table? [April/May-2012]
The state table representation of a sequential circuit consists of three sections
labelled present state, next state and output. The present state designates the state of
flip-flops before the occurrence of a clock pulse. The next state shows the states of
flip-flops after the clock pulse, and the output section lists the value of the output
variables during the present state.
6. What are Hazards? [April/May-2013, Nov/Dec-2009]
The unwanted switching transients (glitches) that may appear at the output of a circuit
are called Hazards.
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7. Distinguish between a flowchart and an ASM chart. [April/May-2013, Nov/Dec2009]

A conventional flow chart describes the square of procedural steps and decision
paths for an algorithm without concern for their time relationship.
The ASM chart describes the sequence of event as well as timing relationship
between the states of a sequential controller and the events that occur while going
from one state to the next.
8. What is a state diagram? Give an example. [April/May-2014]
A state diagram is a type of diagram used in computer science and related fields to
describe the behaviour of systems. State diagrams require that the system described is
composed of a finite number of states; sometimes, this is indeed the case, while at
other times this is a reasonable abstraction. Many forms of state diagrams exist,
which differ slightly and have different semantics.
9. Write the VHDL code for a half adder. [April/May-2014]
HALF ADDER
Entity entity
HALFADD is port ( A,B : in bit; S,C : out bit );
end HALFADD; -Architecture
Architecture struct of HALFADD is
begin S <= A xor B;
C <= A and B;
end struct;
10. Write a verilog model of a full subtractor circuit. [Nov/Dec-2010]
module full_subtractor ( a ,b ,c ,diff ,borrow );
output diff ;
output borrow ;
input a ;
input b ;
input c ;
assign diff = a ^ b ^ c;
assign borrow = ((~a) & b) | (b & c) | (c & (~a));
endmodule
11. Under what circumstances asynchronous circuits are prepared. [Nov/Dec-2011]
(i) Fundamental mode asynchronous circuits
(ii) Pulse mode asynchronous circuits
12. Differentiate fundamental mode and pulse mode asynchronous sequential
circuits. [Nov/Dec-2012]
Fundamental mode sequential circuits

Pulse mode sequential circuits.

(i)Memory elements are clocked flip-flops

(i) Memory elements are either unlocked flip flops or time delay elements.

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(ii)Easier to design

(ii)More difficult to design

13. Design a 3 input AND gate using verilog. [Nov/Dec-2012]

module and ( a ,b ,c ,f);
output diff ;
input a ;
input b ;
input c ;
assign f = a &b & c;
endmodule
14. What is synchronous sequential circuit? [Nov/Dec-2013]

In synchronous circuits the input are pulses (or levels and pulses) with
certain restrictions on pulse width and circuit propagation delay. Therefore
synchronous circuits can be divided into clockedsequential circuits
and uncklocked or pulsed sequential circuits.
In a clocked sequential circuit which has flip-flops or, in some instances,
gated latches, for its memory elements there is a (synchronizing) periodic
clock connected to the clock inputs of all the memory elements of the
circuit, to synchronize all internal changes of state
15. Write short notes on Hazards. [Nov/Dec-2013]
The unwanted switching transients (glitches) that may appear at the output of a circuit
are called Hazards.
Static-0-Hazard
Static-1-Hazard

PART-B
1. What are called as essential hazards? How does the hazard occur in sequential
circuits? How can the same be eliminated using SR latches? Give an example.
[April/May-2010,2011,2012, Nov/Dec-2012,2013]
Unwanted switching appears at the output of a circuit
Due to different propagation delay in different paths
May cause the circuit to mal-function
Cause temporary false-output values in combinational circuits
Cause a transition to a wrong state in asynchronous circuits
Not a concern to synchronous sequential circuits
Three types of hazards:

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Circuits with Hazards

Static hazard: a momentary output change when no output change should occur
If implemented in sum of products:
no static 1-hazard-> no static 0-hazard or dynamic hazard
Two examples for static 1-hazard:

Implementation with SR Latches

Given: S = AB + CD R = AC
For NAND latch, use complemented inputs
S = (AB + CD) = (AB)(CD) R = (AC) Q = (QS) = [Q(AB)(CD)] >Two-level circuits

2. Write short notes on Hazard free switching circuits. [April/May-2010,2012,

2013]
Hazard-Free Circuit
Hazard can be detected by inspecting the map
The change of input results in a change of covered product term-> Hazard exists
Ex: 111-> 101 in (a)
To eliminate the hazard, enclose the two minterms in another product term Results
in redundant gates
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Remove Hazard with Latches:

Implement the asynchronous circuit with SR latches can also remove static hazards
A momentary 0 has no effects to the S and R inputs of a NOR latch
A momentary 1 has no effects to the S and R inputs of a NAND latch

3. With an example, explain the use of algorithmic state machines. [April/May2012,2013]

Algorithmic State Machine An approach of digital design is to partition the system
into a controller and a controlled architecture also called data processor.
Partition of digital system Data processor is a hardware required for data
manipulation that may consist of adder, subtractor, shift register, and etc and output
the results.

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In addition to this function, the data processor also provides status of the data
manipulation to the controller.
The controller, which is also termed as ASM, provides sequence of command to data
processor. It is called ASM because it consists of well defined finite number of step
to the solution of a process.
The external input is used to provide the task required to be carried out by the
controller. The input data is used in the manipulation.
Algorithmic State Machine - 148 - The model of algorithmic state machine. The
machine is viewed as the combination of Mealy and Moore machines.
Next state and memory blocks are similar for both Mealy and Moore machines.
Conditional output function block is similar to that of a Mealy machine, whilst state
output function block is similar to that of a Moore machine.

Algorithmic State Machine Chart The algorithmic state machine SM chart can be
divided into three blocks namely the state box, the decision box, and the conditional
output box.

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The state box contains an output list, state name, and optional state code. The
decision box is a usual diamond shaped symbol with true and false evaluate to decide
the branches.
The conditional output box contains conditional output list. The conditional outputs
depend on both the state of system and the inputs.

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When state S1 entered, output Y1 and Y2 become 1. If inputs X1 and X2 are both
equal to 0, Y3 and Y4 are also 1, and at the end of state time the machine goes to
the next state via exit path 1.
If inputs X1 = 0 and X2 = 1, Y3 and Y4 are 1, the exit to next state is via
path.
On the other hand, if X1 = 1 and X3 = 0, the output Y5 is 1 and exit to the
next state will occur via exit path
If X1 = 1 and X3 = 1, the exit to the next state will occur via path 4.
4. Design a full adder using two half adders by writing Verilog program.
[April/May-2013,2015]

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// Full Adder rtl

module full_adder
(in_x, in_y, carry_in, sum_out,
carry_out);
input in_x;
input in_y;
input carry_in;
output sum_out;
output carry_out;
wire w_sum1;
wire w_carry1;
wire w_carry2;
assign carry_out = w_carry1 | w_carry2
half_adder u1_half_adder
(
.in_x(in_x),
.in_y(in_y),
.out_sum(w_sum1),
.out_carry(w_carry1)
);
half_adder u2_half_adder
(
.in_x(w_sum1),
.in_y(carry_in),
.out_sum(sum_out),
.out_carry(w_carry2)
);
endmodule
5. Derive the ASM chart for binary multiplier. [April/May-2015]
An algorithmic state machine (ASM) is a Finite State Machine that uses a sequential
circuit (the Controller) to coordinates a series of operations among other functional
units such as counters, registers, adders etc. (the Data path).
The series of operations implement an algorithm. The Controller passes control
signals which can be Moore or Mealy outputs from the Controller, to the Data path.
The Data path returns information to the Controller in the form of status
information that can then be used to determine the sequence of states in the
Controller.
Both the Controller and the Data path may each have external inputs and outputs and
are clocked simultaneously as shown in the following figure:

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Design of the Binary Multiplier Controller

An ASM chart that implements the binary multiply algorithm is given below. Note
that << indicates an assignment, for example, C<
The process is achieved with 3 states (IDLE, MUL0 and MUL1).
Each state will provide control signals to the Data path to perform the multiplication
sequence. The process is started with an input G. As long as G remains LO, the
ASM remains in state IDLE. When G=1, the multiplication process is started.
As the ASM moves to state MUL0, the carry flip flop is cleared (C<<<< n-1) and
Register Q is loaded with the Multiplier. In state MUL0, the value of each bit of the
multiplier (available on Q0) determines if the multiplicand is added (Q0 = 1) or not
(Q0=0).
For the case Q0=0, the Carry flipflop is cleared ; for the case Q0=1, the Cout from
the adder is stored in the carry flipflop. The next state is always MUL1. In MUL1,
the Carry flipflop, Reg A and Reg Q are treated as a (1 + n + n)-bit register and
shifted one position to the right, together.
This is indicated with the notation C|A|Q << shr (C|A|Q) in the ASM chart. The
counter is also decremented (P << P 1). The value of Z then determines whether
to: return to state MUL0 (Z=0) to continue iteration OR return to state IDLE (Z=1)
thus completing the process.
Remember that Z=1 means that the counter has counted down from n-1 to 0 and
therefore n iterations have been completed. State IDLE=0 therefore indicates that the
Multiplier is currently multiplying and when the ASM returns to state IDLE
(IDLE=1), it indicates that multiplication is completed

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6. Differentiate critical races from non-critical races. [Nov/Dec-2010]

A critical race occurs when the order in which internal variables are changed
determines the eventual state that the state machine will end up in.
A non-critical race occurs when the order in which internal variables are changed
does not alter the eventual state. In other words, a non-critical race occurs when
moving to a desired state means that more than one internal state variable must be
changed at once, but no matter in what order these internal state variables change,
the resultant state will be the same.
7. Explain the steps involved in the reduction of state table. [Nov/Dec-2010]
Construct implication chart, one square for each combination of states taken two at a
time
Square labeled Si, Sj, if outputs differ then the square gets an 'X'. Otherwise, write
down implied state pairs for all input combinations.
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Advance through chart top-to-bottom and left-to-right. If square Si, Sj contains next
state pair Sm, Sn and that pair labels a square already labeled 'X' then Si, Sj is
labeled 'X' .
Continue executing Step 3 until no new squares are marked with 'X'.
For each remaining unmarked square Si, Sj, then Si and Sj are equivalent.

8. Design a JK flip-flop by writing Verilog program. [April/May-2015]

module jk(q,q1,j,k,c);
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output q,q1;
input j,k,c;
reg q,q1;
initial begin q=1'b0; q1=1'b1; end
always @ (posedge c)
begin
case({j,k})
{1'b0,1'b0}:begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=~q; q1=~q1; end
endcase
end
endmodule

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