Fig. 5-1 4-Bit Register: Logic and Computer Design Fundamentals, 2E, Updated

5-1
D0
Clock
Q0
C
REG
Clear
D1
Q1
D2
Q2
Clear
D0
Q0
D1
Q1
D2
Q2
D3
Q3
(b) Symbol
D3
Q3
C
Load
Clock
C inputs (clock inputs

of flip-flops)
(c) Load control input
(a) Logic diagram
Clock
Load
C inputs
(d) Timing diagram
Fig. 5-1 4-Bit Register

2001 Prentice Hall, Inc.
M. Morris Mano & Charles R. Kime
LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
5-2
Load
D0
Q0
Q1
Q2
Q3
D
D1
D
D2
D
D3
Clock
Fig. 5-2 4-Bit Register with Parallel Load

5-3
Serial
input SI
D
C
Clock
D
C
(a) Logic diagram
SRG 4
Clock
SO
Sl
Serial
input S0
(b) Symbol
Fig. 5-3 4-Bit Shift Register

5-4
Shift
Clock
Register A
C
Register B
SRG 4
SO
Sl
SRG 4
SO
Sl
(a) Block diagram
Clock
Shift
C Input
T1
T2
(b) Timing diagram
Fig. 5-4 Serial Transfer

T3
T4
5-5
TABLE 5-1
Example of Serial Transfer
Timing
pulse
Shift Register A
Shift Register B
Initial value
After T1
After T2
After T3
After T4
1
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
1
1
0
1
0
0
0
1
1
0
Table 5-1 Example of Serial Transfer

1
0
0
1
1
0
1
0
0
1
5-6
Register A
C
SRG 4
Clear
Reset
FA
SO
Sl
X
Y
Z
Shift
Clock
Full Adder
(Figure 3-27)
Register B
C
Reset
Serial
input
SRG 4
Carry
Clear
Sl
SO
C
R
Reset
Fig. 5-5 Serial Addition

5-7
Shift
Load
Serial
input
D0
Q0
Q1
SHR 4
D1
Shift
Load
Sl
D2
D
C
Q2
Clock
Fig. 5-6 Shift Register with Parallel Load

Q0
D1
Q1
D2
Q2
D3
Q3
(b) Symbol
D3
D0
Q3
5-8
TABLE 5-2
Function Table for the Register of Figure 5-6
Shift
Load
Operation
0
0
1
0
1
No change
Load parallel data
Shift down from Q0 to Q3
Table 5-2 Function Table for the Register of Figure 5-6

5-9
Qi 1
SHR 4
Clock
MUX
S1
S1
S0
S0
Mode S1
S1
Mode S0
S0
Left serial input
Qi
Right serial input
2
Di
LSI
D0
Q0
D1
Q1
D2
Q2
D3
Q3
RSI
(b) Symbol
Qi + 1
Clock
(a) Logic diagram of one typical stage
Fig. 5-7 Bidirectional Shift Register with Parallel Load

5-10
TABLE 5-3
Function Table for the Register of Figure 5-7
Mode control
S1
S0
Register
Operation
0
0
1
1
0
1
0
1
No change
Shift down
Shift up
Parallel load
Table 5-3 Function Table for the Register of Figure 5-7

5-11
J
Clock pulses
Q0
Q1
Q2
C
K
R
C
K
R
C
K
R
Q3
C
K
R
Clear
Logic 1
Fig. 5-8 4-Bit Ripple Counter

5-12
TABLE 5-4
Counting Sequence of Binary Counter
Upward Counting Sequence
Downward Counting Sequence
Q3
Q2
Q1
Q0
Q3
Q2
Q1
Q0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Table 5-4 Counting Sequence of Binary Counter

5-13
TABLE 5-5
State Table and Flip-Flop Inputs for Binary Counter
Present
state
Next
state
Flip-flop inputs
Q3
Q2
Q1
Q0
Q3
Q2
Q1
Q0
JQ3
KQ3
JQ2
KQ2
JQ1
KQ1
JQ0
KQ0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 5-5 State Table and Flip-Flop Inputs for Binary Counter
5-14
Q1Q0
00
Q3 Q2
Q1
01
11
10
00
01
Q3
Q2
11
10
Q0
JQ3 = Q0 Q1 Q2
KQ3 = Q0 Q1 Q2
1
X
1
1
X
JQ2 = Q0 Q1
KQ2 = Q0 Q1
JQ1 = Q0
KQ1 = Q0
Fig. 5-9 Maps for Input Equations of a Binary Counter

5-15
Q0
Q1
C
Count enable EN
CTR 4
EN
Q0
Q1
Q2
Q2
Q3
CO
C
K
(b) Symbol
Q3
C
K
Carry
output CO
Clock
(a) Logic diagram
Fig. 5-10 4-Bit Synchronous Binary Counter

5-16
Q0
EN
Count enable EN
Q0
C
Q1
C1
Q1
C
Q2
Q2
C2
C
Q3
Q3
C3
Carry
output CO
CO
Clock
(a) Serial gating
Fig. 5-11 4-Bit Binary Counter with D Flip-Flops

(b) Parallel gating
5-17
Count
Load
D0
Q0
Q1
D1
Load
K
Count
D2
D0
Q0
D1
Q1
D2
Q2
D3
Q3
Q2
CTR 4
(b) Symbol
D3
Q3
CO
Carry
Output CO
Clock
(a) Logic diagram
Fig. 5-12 4-Bit Binary Counter with Parallel Load

5-18
TABLE 5-6
State Table and Flip-Flop Inputs for BCD Counter
Present State
Next State
Output
Flip-Flop Inputs
Q8
Q4
Q2
Q1
Q8
Q4
Q2
Q1
TQ8
TQ4
TQ2
TQ1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
Table 5-6 State Table and Flip-Flop Inputs for BCD Counter

5-19
CTR 4
Clock
Load
1
(Logic 0)
Count
D0
Q0
D1
Q1
Q1
D2
Q2
Q2
D3
Q3
CO
Fig. 5-13 BCD Counter

Q0
Q3
5-20
TABLE 5-7
State Table and Flip-Flop Inputs for BCD Counter
Present State
Next State
Output
Flip-Flop Inputs
Q8
Q4
Q2
Q1
Q8
Q4
Q2
Q1
TQ8
TQ4
TQ2
TQ1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
Table 5-7 State Table and Flip-Flop Inputs for BCD Counter

5-21
C
J
Clock
C
K
Logic-1
(a) Logic diagram
111
000
001
110
010
101
100
011
(b) State diagram
Fig. 5-14 Counter with Arbitrary Count

5-22
TABLE 5-8
State Table and Flip-Flop Inputs for Counter
Present
State
Next State
Flip-Flop Inputs
JA
KA
JB
KB
JC
KC
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
Table 5-8 State Table and Flip-Flop Inputs for Counter

5-23
-- 4-bit Shift Register with Reset

-- (See Figure 5-3)
library ieee;
use ieee.std_logic_1164.all;
entity srg_4_r is
port(CLK, RESET, SI : in std_logic;
Q : out std_logic_vector(3 downto 0);
SO : out std_logic);
end srg_4_r;
architecture behavioral of srg_4_r is
signal shift : std_logic_vector(3 downto 0);
begin
process (RESET, CLK)
begin
if (RESET = '1') then
shift <= "0000";
elsif (CLKevent and (CLK = '1')) then
shift <= shift(2 downto 0) & SI;
end if;
end process;
Q <= shift;
SO <= shift(3);
end behavioral;
Fig. 5-15 Behavioral VHDL Description of 4-bit Left Shift Register with Direct Reset

5-24
-- 4-bit Binary Counter with Reset

-- (See Figure 5-10)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count_4_r is
port(CLK, RESET, EN : in std_logic;
Q : out std_logic_vector(3 downto 0);
CO : out std_logic);
end count_4_r;
architecture behavioral of count_4_r is
signal count : std_logic_vector(3 downto 0);
begin
process (RESET, CLK)
begin
if (RESET = '1') then
count <= "0000";
elsif (CLKevent and (CLK = '1') and (EN = '1')) then
count <= count + "0001";
end if;
end process;
Q <= count;
CO <= '1' when count = "1111" and EN = '1' else '0';
end behavioral;
Fig. 5-16 Behavioral VHDL Description of 4-bit Binary Counter with Direct Reset

5-25
// 4-bit Shift Register with Reset

// (See Figure 5-3)
module srg_4_r_v (CLK, RESET, SI, Q,SO);
input CLK, RESET, SI;
output [3:0] Q;
output SO;
reg [3:0] Q;
assign SO = Q[3];
always@(posedge CLK or posedge RESET)
begin
if (RESET)
Q <= 4'b0000;
else
Q <= {Q[2:0], SI};
end
endmodule
Fig. 5-17 Behavioral Verilog Description of 4-bit Left Shift Register with Direct Reset

5-26
// 4-bit Binary Counter with Reset

// (See Figure 5-10)
module count_4_r_v (CLK, RESET, EN, Q, CO);
input CLK, RESET, EN;
output [3:0] Q;
output CO;
reg [3:0] Q;
assign CO = (count == 4'b1111 && EN == 1b1) ? 1 : 0;
always@(posedge CLK or posedge RESET)
begin
if (RESET)
Q <= 4'b0000;
else if (EN)
Q <= Q + 4'b0001;
end
endmodule
Fig. 5-18 Behavioral Verilog Description of 4-bit Binary Counter with Direct Reset


Fig. 5-1 4-Bit Register: Logic and Computer Design Fundamentals, 2E, Updated

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Fig. 5-1 4-Bit Register: Logic and Computer Design Fundamentals, 2E, Updated

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5-1

C inputs (clock inputs

(c) Load control input

(a) Logic diagram

(d) Timing diagram

Fig. 5-1 4-Bit Register

Fig. 5-2 4-Bit Register with Parallel Load

(a) Logic diagram

Fig. 5-3 4-Bit Shift Register

2001 Prentice Hall, Inc.

(a) Block diagram

Fig. 5-4 Serial Transfer

2001 Prentice Hall, Inc.

Table 5-1 Example of Serial Transfer

2001 Prentice Hall, Inc.

Fig. 5-5 Serial Addition

2001 Prentice Hall, Inc.

Fig. 5-6 Shift Register with Parallel Load

Table 5-2 Function Table for the Register of Figure 5-6

2001 Prentice Hall, Inc.

Left serial input

Right serial input

(a) Logic diagram of one typical stage

Fig. 5-7 Bidirectional Shift Register with Parallel Load

2001 Prentice Hall, Inc.

Table 5-3 Function Table for the Register of Figure 5-7

2001 Prentice Hall, Inc.

Fig. 5-8 4-Bit Ripple Counter

Downward Counting Sequence

Table 5-4 Counting Sequence of Binary Counter

Fig. 5-9 Maps for Input Equations of a Binary Counter

Fig. 5-10 4-Bit Synchronous Binary Counter

Fig. 5-11 4-Bit Binary Counter with D Flip-Flops

(b) Parallel gating

Fig. 5-12 4-Bit Binary Counter with Parallel Load

2001 Prentice Hall, Inc.

Fig. 5-13 BCD Counter

2001 Prentice Hall, Inc.

2001 Prentice Hall, Inc.

(b) State diagram

Fig. 5-14 Counter with Arbitrary Count

2001 Prentice Hall, Inc.

Table 5-8 State Table and Flip-Flop Inputs for Counter

2001 Prentice Hall, Inc.

-- 4-bit Shift Register with Reset

2001 Prentice Hall, Inc.

-- 4-bit Binary Counter with Reset

2001 Prentice Hall, Inc.

// 4-bit Shift Register with Reset

2001 Prentice Hall, Inc.

// 4-bit Binary Counter with Reset

2001 Prentice Hall, Inc.

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