Simulation and implementation of synchronous reference frame

phase lock loop techniques.

Sajitha Amashan Sovis - 3315989, School of Electrical and Computer Engineering - RMIT University
Abstract The analysis, simulation and
experimental validation of existing Phase Lock Loop
designs for three phase applications have been
presented in this paper. Theoretical and experimental
investigations of the dynamic behaviour of these
techniques are conducted. The performance of the
system is analysed in realistic utility conditions such
as unbalanced voltages, voltage sags and swells,
frequency and phase angle variations, single phase
and two phase faults, random noise and harmonics.
The experimental results are compared with the
simulation results for any discrepancies and this is
then used to provide any design considerations for
future work.

1.

Introduction

This is a draft of the introduction. This will be

improved with more content from more references.
There has never been a greater demand for cleaner
electric power with higher reliability and power
quality. One of the greatest contributions to this
demand is the recent growth in renewable energy
systems in response to global warming and climate
change. Another factor is the evolution towards
smart-grids. The synchronization and control
techniques offered by PLLs are a key component in
grid connected power electronic converters used in
various applications. Such applications may be in
uninterruptible power supplies, active power filters,
grid connected renewable energy power systems
and other grid connected distribution generators.
[2] This is because proper synchronization is vital
in such applications for the purpose of operation
and control.
2.

Literature Review

This is a draft of the literature review. This will be

improved with more content from more references.
A great deal of literature to gain a basic
understanding of the operation of an elementary
PLL can be obtained from [][][][] . A phase lock
loop (PLL) is a closed-loop feedback control
system with the objective of generating a signal
whose phase angle is tracking the variations in a
reference signal. The reference signal in the case of
this literature would be the grid voltage. Most PLL
schemes consist of three main parts. These are i) a
phase detector, ii) a loop filter, and iii) a voltage
controlled oscillator as shown in Figure xx below.
Xxxxx

The strategy used by the PLL to track the phase of

the reference signal is to estimate the error between
the phase angle of the generated output signal and
that of the reference signal and regulate this error to
zero through the means of a control system.
The phase detector (PD) is usually a simple
multiplier and it generates an output signal
proportional to the error between the output signal
of the PLL and the reference signal.
The loop filter (LF) presents low pass filtering
characteristics, which allows high frequency
components of the PD to be reduced. A low pass
filter or a PI controller generally represents this.
The LF outputs an error signal that is proportional
to the phase difference between the input and
output signals.
The voltage controlled oscillator (VCO) generates a
signal which is a function of the phase error from
the LF and this signal is shifted with respect to a
given feed forward frequency ff. A detailed
explanation on the equations and the small signal
models governing the operation of the PLL can be
obtained from [1].
The main challenge of PLL design for grid
connection application is the need to perform with
nil steady state error for utility conditions such as
unbalanced voltages, line notches, frequency
variations and harmonics. Numerous schemes with
different approaches have been presented to meet
this requirement. However, most of these
approaches have limitations to a certain extent.
2.1 Single phase PLL methods
This is a draft of this section. This will be improved
with more content from more references. Each of
the techniques discussed will also be reviewed in
detail.
References [][][] propose phase lock loop schemes
for single phase systems. It needs to be noted that
the elementary model shown in Fig x above is only
correct under the assumption that the frequency of
the signal to be phase locked is much greater than
the bandwidth of the PLL. This assumption allows
the high frequency term of the phase error
generated by the multiplier PD to be neglected. In
real life applications though, the grid frequency is
very close to the PLL cut off frequency and the

high frequency term in the error signal output from

the PD is only twice that of the grid frequency.
With such close frequencies, complete cancellation
of the high frequency component is not possible,
therefore a new PD different to the simple
multiplier has to be used in the PLL design.

In order to mimic all these conditions together,

simulation models for each of the conditions were
built in PSIM software before being compiled into
one model. The methodology followed in building
this model is as presented in following section.
4.1 Modelling of frequency variations in the grid

Several improvements to this elementary model

have been proposed in the literature with a lot of
importance being placed on alternative ways of
constructing the PD. Some notable techniques are
discussed below.

Enhanced PLL (EPLL):

Adaptive PLL:
Quadrature signal based PLL:
More single phase PLL methods to be
added to this section

2.2 Three phase PLL methods

In order to model a 3-phase grid with varying

frequency, A DC source behind a resetting
integrator was used. This is shown in Fig x. The
resetting integrator generates the phase angle
corresponding to the required frequency of the
2
2
three voltages. A phase shift of and
is added
3
3
on to two of the phase angles using DC sources.
These three phase angles are then fed into a sine
function block to generate the required waveforms.
Since these waves will have a magnitude of 1, a
proportional gain with the value corresponding to
the amplitude is added to each of the waves.

Three phase PLL methods from literature will be

discussed in this section and an overview of the
state of the art will be presented. From the
techniques that are presented, a detailed review will
be conducted on the SRF PLL, DDSRF PLL, and
two other PLL techniques in the section that
follows.
3.

Review of the PLL techniques that will be

implemented

3.1 Synchronous Reference Frame PLL

This section is yet to be completed.
3.2 Decoupled Double Synchronous Reference
Frame PLL
This section is yet to be completed.

Fig x. shows the waveform generated by the model

and its instantaneous frequency. The model can be
manipulated by setting various points with different
values within the piecewise DC source to change
the frequency as desired. It can be seen that the
frequency of the waveforms shown in Fig x slew
from 45Hz to 65Hz from t = 0ms to t = 200ms.

3.3 3rd PLL technique to be reviewed here after it

has been determined.
This section is yet to be completed.
3.4 4th PLL technique to be reviewed here after it
has been determined.
This section is yet to be completed.
4.

Modelling of utility conditions

In order to run accurate simulations on how the

different PLL topologies behave in a real grid,
accurate grid conditions have to be modelled and
simulated as well. In this paper, we will be
focusing on the dynamic behaviour of the PLLs
when subjected to unbalanced voltages, line
notches, frequency variations and harmonics.

4.2 Modelling of unbalanced voltages

The same model from section 4.1 can be used to
model unbalanced voltages as well. The
proportional gain in front of the sine function
generator allows the amplitude to be changed as
desired to reflect an unbalance in voltage. Fig x.
shows the simulation of the model altered to cause
an unbalance in voltage.

This section will present the methodology followed

in developing the model for the SRF PLL. It will
show how the simulation model relates to the
model presented in the literature. The schematic of
the model developed in PSIM so far is as shown
below.

4.3 Modelling of harmonics in the grid

Harmonics in the grid are modelled by simply
injecting harmonic components into the output of
the 3-phase sine wave generator developed in the
previous sections. The alteration is as shown in Fig.
x below and the distorted waveforms generated by
the model is shown in Fig. x.

5.2 Decoupled Double Synchronous Reference

Frame PLL
The simulation model for the DDSRF PLL will be
presented here with details on how it matches up
with the model presented in the literature. The
schematic of the model developed in PSIM so far is
as shown below. However, this model is not
operational yet.

4.4 Modelling of voltage sags and swells

This section is yet to be completed.
4.5 Modelling of single phase and two phase faults
This section is yet to be completed.
4.6 Combination of all the condition models into a
testing framework
This section is yet to be completed.
5.

SIMULATION MODELLING OF PLL

TECHNIQUES

5.1 Synchronous Reference Frame PLL

5.3 Simulation model of the 3rd PLL technique that

was reviewed.
This section is yet to be completed.
5.4 Simulation model of the 4th PLL technique that
was reviewed.
This section is yet to be completed.
6.

SIMULATION RESULTS

The four models presented in the previous section

will be run simultaneously on the testing
framework presented in section 4.6. The simulation
results from this test will be presented in this

section. These results will then be compared with

the results presented in the literature to see if there
are any discrepancies.

The experimental results from all will be presented

in this section for the same tests that were done on
the simulation model. A discussion

7.

9.

EXPERIMENTAL MODELLING

This section is to be added once building and

testing of the experimental model of one of the
PLL techniques presented in section 3 is
completed. It will contain an introduction to the
building of the experimental model, which will be
explored in detail in the following sub sections.

COMPARISON OF SIMULATION AND

EXPERIMENTAL RESULTS

A comparative analysis will be done to see there

are any inconsistencies between the experimental
results and the simulation results. A detailed
10. DESIGN
CONSIDERATIONS
FUTURE WORK

AND

7.1 Experimental Modelling of utility conditions

This section will discuss on what laboratory
equipment will be used and how they will be used
to model the grid conditions presented in section 4.
7.2 Experimental modelling of selected PLL
technique

This section will contain a detailed description on

any design consideration that may arise from the
comparative analysis conducted in section 8. This
will allow definition of any future work that may
need to be carried out in order to improve on the
work presented in this paper.
11. CONCLUSION

This section will contain a detailed methodology of

the setting up of the experimental model and an
explanation on how the experimental model relates
to the simulation model and the mathematical
model.
8.

EXPERIMENTAL RESULTS

12. APPENDIX
13. REFERENCES
[1] Grid Converters for Photovoltaic and Wind
power systems.
[2] Reference 3 from a phase tracking system for
three phase utility interface inverters