Analog Digital VLSI Design

Lecture 3
layouts, design rules, mismatch

CMOS LAYOUTS

Organisation
Design rules, Schematic to layout, vice
versa,
cross-sectional diagram, big layouts
Matched components
Over-etching errors
unit components design
design using non unit component
Boundary condition matching
Common centroid layout, parasitic cap
estimation

 Scalable design rules-----same set can be

used for next tech generation by changing
. Worst case values of spacings, widths
etc. are used , so cant be an optimized
set. e. g. MOSIS design rules
Absolute design rules----optimized set but
same set cant be used for next tech gen.
Entire new set is to be created.

TANNER

4 NAND GATES

CADENCE

MOS LAYOUT

2
2

Junction cap-single transistor

Other layouts of MOS

Annular transistor

Elongated annular
transistor

Dense MOS layouts

metal1

metal2

Waffle transistor

Compute w/L?

Bent transistor

CIRCUIT AND LAYOUT

Try more examples

How to reduce parasitic

capacitances?
Careful layout by junction sharing

CAPACITOR LAYOUTS

RESISTOR LAYOUT

Matching Issues
Large device => many small unit devices
Same boundary conditions for devices

Overetching MOS dimensions

L
Poly layer
e

Over etched Poly layer

(W/L)u = 8um/2um= 4 desired

After over etching --0.5um= e
(W/L)u = 7um/1um= 7;

Absolute dimension of MOS

Remedy---use Unit components w=L
(W/L)u = 10um/10um, RATIO=1
After fab. (W/L)u 8um/8um, RATIO=1
ConclusionAbs. dimensions change,
ratio does not change

Ratio of matched devices

(W/L)1 = 2, (W/L)2 = 8, ratio= 4
We take unit device (W/L)u = 10um/10um
After fab. (W/L)u 8um/8um
(W/L)2
(W/L)1

8(W/L)u
=4
2(W/L)u

Thus, ratio remains same, if same unit

device is used

Application of technique

Layout of CAPACITORS

CAPACITOR LAYOUTS

Over-Etching

 Let
C1/ C2 = 3.4 = 2+1.4
= [6/3] + [1.4/1]
[6/3]---can be implemented by using unit
capacitors
[1.4/1]---we require non unit capacitor
Mismatch can occur due to second term

No mismatch condition
We should design non unit cap. Such that
ratio (1.4) remains constant even after
overetching
How to design?
What is the condition?

Condition
= c1
c2

r1= r2

Non unit sized cap

= 1.4

Boundary condition matching

Common centroid layout

What if unit devices change

randomly?

Since one device is facing larger change in dimension,

maintaining constant ratio would be difficult.
So, We should have same change in all unit devices. how?
Inter-digitization

Reduce mismatches

S
S

Bulk (backgate contact)

RESISTOR LAYOUT

Big Resistor

BIG RESISTOR (unit components)

Parasitic cap, calculation of

MOS device
Common Centroid layout

20

Fingered layout

View of fingered layout