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Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
Using single-precision floating-point representations and the procedure described in Section 3.9, determine
the products below. The result should be truncated (and rounded) to 3 fraction bits (if necessary).
a. 8.125 (8)
b. (19) (12.5)
Solution
a. 8.125 (8) = 1.00000123 (123) = 1.00000126. Truncating to 3 fraction bits, 1.00026 results.
Hence, S = '1', F = "000", and E = "10000101" (=133).
b. (19) (12.5) = (1.001124) (1.100123) = 1.1101101127. After truncation, 1.11127 results.
Hence, S = '0', F = "111", and E = "10000110" (=134).
Chapter 4: Introduction to Digital Circuits
Exercise 4.3: Static power consumption #3
a. Consider the CMOS inverter shown in Figure 4.5(a). Assuming that it does not exhibit any current
leakage when in steady state, what is its static power consumption?
b. Suppose that the circuit presents a leakage current from VDD to GND of 1 pA while in steady state and
biased with VDD = 3.3 V. Calculate the corresponding static power consumption.
Solution
a. Pstatic = VDD.ID = 0
b. Pstatic = VDD.ID = 3.3V 1pA = 3.3 pW
Exercise 4.13: OR-NOR timing analysis
Suppose that the OR-NOR circuit of Figure E4.13 is submitted to the stimuli also included in the figure
where every time slot is 10 ns wide. Adopting the simplifi ed timing diagram style of Figure 4.8(b), draw
the corresponding waveforms at nodes x and y for the following two cases:
a. Assuming that the propagation delays through the gates are negligible.
b. Assuming that the propagation delays through the OR and NOR gates are 2 ns and 1 ns, respectively.
a
a
b
y
b
c
c
x
y
Solution
See the figure below.
a
2ns
(a)
2ns
1ns
(b)
1ns
1ns
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
(a)
a
b
c
d
(b)
(c)
(d)
a
b
c
d
a
b
c
d
b
c
a
b
c
d
b
y
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
clock
data
NRZ
Bipolar
RZ (AMI)
(a)
x 1
x 2
x 3
x 4
y1
y
y2
(b)
x 1
x 2
x 3
y
y2
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
TN
H=
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
0
1
0
0
1
1
BN
(a)
(b)
c1
c2
c3
c4
c5
c6
c6
c8
Solution
a. n=8, m=4 (so k=4), wrow=4, and wcol=2.
b. See figure (b) above.
c. See, for example, TN1 BN3 TN4 BN6 TN1 (TN = test-node, BN = bit-node) in the figure
above.
d. The expression HcT produces a zero only for the 1st codeword, so the 2nd codeword does not belong to
this code.
Chapter 8: Bipolar Transistor
Exercise 8.5: DC response #2
The questions below pertain to the circuit of Figure E8.4.
a. Plot VY as a function of VX.
b. Plot IB as a function of VX.
c. Plot IC as a function of VX.
d. Plot VZ as a function of VX.
e. For which values of VX is the transistor (i) cut off, (ii) in the active region, and (iii) saturated?
f. Draw the load line for this circuit and mark on it (i) the cutoff point, (ii) the point where the transistor
enters the saturation region, and (iii) the point where the transistor rests while saturated.
VCC
Figure E8.4.
I1
RC
IB
VY
VX
R1
R2
I2
IC
VZ
VCC=10V
VBB= 10V
=130
VJ=0.7V
VCEsat=0.2V
R1=50k
R2=150k
RC=1k
VBB
Solution
a. to d. See part (a) in the figure below.
e. Cut off for VX<4.27V, in the active region for 4.27VVX8.04V, and saturated for VX>8.04V.
f. See part (b) in the figure below.
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
150
114.7
VY
(V)
12.5
IB
(uA)
0.7
0
IC
(mA)
4.27
10
(ii)
9.8
9.3
0
0
(iii)
10
4.27
VX (V)
7.5
10
VX (V)
12.5
10
Active region
9.8
IC
(mA)
VZ
(V)
2.5
(i)
0
0.2
0
0
0
4.27
8.04
10
VX (V)
4.27
8.04
2
Vj =0.7V
VCE sat=0.2V
10
VX (V)
(a)
10
VCE (V)
(b)
vX
0V
iC
0mA
9.8mA
10V
td tr
vZ
ts
tf
0.2V
VDD
VDD=5V
VT=1V
=1mA/V2
RD=1.8k
VG
RG
RD
+
VGS
ID
+
VDS
2.41
2.0
4
1.75
1.5
1.0
0.5
1
2.87
0
0
(a)
2.5
(b)
Cutoff Saturation
1.85
Triode
(c)
0.66
2.87
0
1
Cutoff Saturation
Triode
Solution
a. According to equation (9.1), the transistor remains OFF while VGS<VT, that is, for VG<1V.
b. According to equation (9.2), the transistor remains in the saturation region while VDSVGSVT. Therefore,
using ID=(/2)(VGSVT)2, combined with VDS=VDDRSID plus the condition VDS=VGSVT, we obtain
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
VGS=2.87V. Hence the transistor operates in the saturation region while VG is in the range 1VVG2.87V.
For VG=2.87V, ID=1.75mA and VDS=1.85V.
c. According to equation (9.3), the transistor operates in the triode (or linear) region when VDS<VGSVT,
which occurs for any VG>2.87V. For VG=5V, we obtain ID=2.41mA and VDS=0.66V.
d. The plot of ID is shown in figure (b) above. From 0V to 1V the transistor is OFF, so ID=0. From 1V to
2.87V it is in the saturation region, so equation (9.2) was employed to sketch the current. Finally, above
2.87V it operates in triode mode, so equation (9.3) was used for ID.
e. The plot of VDS is shown in figure (c) above, determined by VDS=VDDRDID.
Exercise 9.15: CMOS inverter #2
Consider the CMOS inverter shown in figure E9.15. Say that Mn was designed with minimum size, that is,
(W/L)n=3/2, and that the pMOS transistor was designed with minimum length, Lp=2.
(a) Assuming that the mobility of electrons in the channel is about 3 times that of holes, what must the
width of the pMOS transistor (Wp) be for the two transistors to exhibit the same transconductance factors
(that is, n=p)?
(b) Intuitively, without inspecting equation (9.7), would you expect the transition voltage to change towards
0V or VDD when (W/L)n is increased with respect to (W/L)p? Explain.
(c) If n>p, assuming that VTn=VTp, do you expect the transition voltage to higher or lower than VDD/2?
Mp
vI
vO
Mn
Figure E9.15.
Solution
a. Since =Cox(W/L), (W/L)p=9/2 is required to obtain for n=p.
b. and c. Assuming that n=p and VTn=VTp, the same drain current (Equation 9.2) is produced by Mn and
Mp if VGSn= |VGSn|, that is, when VI =VDD/2, and the transistors are exactly on the transition point, in which
VOVI. If n is increased, with VI kept at VDD/2, then the drain current of Mn would grow, while that of Mp
would remain the same. This is obviously an impossible situation, because the transistors are connected in
series, so they can only operate with the same ID. The only operating point that satisfies this condition is
with Mn in triode mode (Equation 9.3), because then its VDS voltage will decrease enough to limit its drain
current, such that the drain current defined by Mp will prevail. In summary, to still remain in the transition
region, a lower gate voltage should be applied to Mn and a higher one (magnitude) should be provided for
Mp. Consequently, if Mn is stronger than Mp, it pulls VTR toward GND, while a stronger Mp would pull it
toward VDD.
Chapter 10: Logic Families and I/Os
Exercise 10.13: 2.5V LVCMOS I/O standard
(a) Draw a diagram similar to that in figure 10.7 for the 2.5V LVCMOS I/O standard. Assume that VDD is
exactly 2.5V and that IO=|1mA|.
(b) Calculate this familys noise margin when low and when high.
Solution
The corresponding parameters are given in Figure 10.23, that is, VOH=2.2V (notice that in the test condition
VDD is specified as minimum, that is, VDD=2.3V, with the resulting value of VOH 0.3V below VDD),
VOL=0.4V, VIH=1.7V, and VIL=0.7V. The construction of the diagram is now straightforward, and the
resulting noise margins are NMH=2.21.7V=0.5V and NML=0.70.4V=0.3V. These results are summarized
in the diagram below.
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
2.5V LVCMOS
A
Output
VDD=2.5V
1
VOH=2.2V
NMH
VOL=0.4V
NML
Input
2.5V LVCMOS
VOL (max)
0.4V
VOH (min)
2.2V
VIL (max)
0.7V
VIH (min)
1.7V
VIH=1.7V
Noise margin
VIL=0.7V
0
NML
0.5V
NMH
0.3V
GND
y
(weak)
y
a
b
clock
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
x1
y3
x0
y2
x1
y1
x0
y0
y3
y2
x1
x0
y1
(a)
(b)
y0
x0
x1
x2
x0
x1
x2
x3
0
1
2
3
x3
x4
x5
x6
x7
x7
0
1
sel(2:0)
(a)
(b)
2
0
1
2
3
FA
FA
FA
Figure E12.3.
Exercise 12.13: Incrementer
FA
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
a. Write the Boolean expressions (in SOP format) for the incrementer seen in Figure 12.14(b) (repeated in
the figure below).
b. Suppose that a = "10110" (= 22). Apply it to the circuit and check whether it produces the expected
result (that is, b = 23).
c. Repeat part (b) above for a = "11111" (= 31). What is the expected result in this case?
a1
a0
b1
b0
a2
b2
a3
b3
a4
b4
Solution
a. The circuits equations are listed below.
b0 = a0
b1 = a1 a0 = a1.a0 + a1.a0
b2 = a2 (a1.a0) = a2.a1.a0 + a2.a1 + a2.a0
b3 = a3 (a2.a1.a0) = a3.a2.a1.a0 + a3.a2 + a3.a1 + a3.a0
b4 = a4 (a3.a2.a1.a0) = a4.a3.a2.a1.a0 + a4.a3 + a4.a2 + a4.a1 + a4.a0
b. The expected result indeed occurs (you can confirm this by using either the circuit or the expressions
above).
c. Due to overflow, "00000" (= 0) is expected and indeed occurs.
Chapter 13: Registers
Exercise 13.9: DFF timing analysis
Figure (a) below shows a positive-edge D-type flip-flop (DFF) that receives the signals clk, rst, and d
displayed in figure (b). Assuming that the DFFs propagation delay from clk to q is tpCQ=5ns and from rst to
q is also tpRQ=5ns, draw the resulting waveform for q. Consider that the clock period is 50ns and that the
DFFs initial state is q=0.
Solution
See q figure (b) below. As usual, gray shades are employed to highlight the propagation delays.
clk
d
clk
(a)
rst
rst
rst
(b)
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
1
0
clk
q
1
clk
0
clk
1
1
0
0
q3
q2
q1
q0
Programmable
counter
clk
Solution
One solution is shown in the figure below, which contains an equality comparator (see Figure 12.15(a)) at
the input. When the counter output coincides with the (programmable) value chosen for M, clear=0 is
generated, causing the counter to be synchronously zeroed at the next clock edge. The counter can be that
of Figure 14.11(b).
clk
Counter
q3
1
clr
q2
Programmable
input (M)
1
q1
clear
0
q0
0
q3
q2
q1
q0
Counter
output
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
clk/M
For MC=1
MC
x
d0
q0
d1
q1
q0
q1
For MC=0
clk
q0
clk
q0
q1
q1
clk
(a)
T=3T0
T=2T0
(b)
(c)
four
five
six
(0100)
(0101)
(0110)
y3
three
(0011)
nine
eight
seven
(1001)
(1000)
(0111)
(a)
Truth table for nx_state
pr_state
q2 q1 q0
nx_state
d2 d1 d0
pr_state
q2 q1 q0
output
y3 y2 y1 y0
011
100
101
110
111
000
001
100
101
110
111
000
001
011
011
100
101
110
111
000
001
0011
0100
0101
0110
0111
1000
1001
(b)
y2
q2
d2
q2
y1
q1
d1
q1
y0
(c)
q0
q0
d0
clk
Step 2: The corresponding truth tables, extracted from the state transition diagram, are shown in figure (b).
Note that 3 bits (so 3 DFFs) are needed to encode the 7 machine states. Any encoding can be chosen, so to
avoid a large amount of combinational logic to convert the 3-bit machine output into the actual 4-bit circuit
output the last 3 output bits were employed (see the truth table for y) to represent the machine states.
Consequently, the values for y can be easily determined as y0=q0, y1=q1, and y2=q2, with y3 as the only
output that indeed requires some additional computation.
Step 3: From the truth table, with the help of Karnaugh maps, the following irreducible SOP expressions
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
Debouncer
clk
Solution
a. The formal 5-step design procedure described in Section 15.2 can again be employed. The results are
summarized in the next figure. First, the circuits state transition diagram is presented; since this machine
has 4 states, a minimum of 2 DFFs are necessary. Next, the corresponding truth tables for nx_state and y are
shown, in which sequential binary encoding (Chapter 2) was employed. From the truth tables, with the help
of Karnaugh maps, the following equations result for nx_state (that is, d1 and d0) and y:
d1 = q1.q0 + q1.t + q0.x.t
d0 = q1.q0.x + q1. q0 .x + q1.x .t + q1.x.t
y = q1
were t (=time) represents the status of the counter, that is, t is 1 when time=max or 0 otherwise (note that
the counter, by counting from 0 to max, has max+1 states, so the clock frequency gets divided by max+1).
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
time max
x=0
up
(y=0)
x=1
x=0
x=1
x=1 AND
time=max
one
(y=1)
zero
(y=0)
x=0 AND
time=max
x=0
x=1
down
(y=1)
time max
Truth table for nx_state
pr_state
time
nx_state
zero
0
1
0
1
1
0
1
0
0
1
------ max
= max
---- max
= max
---
zero
up
zero
up
one
down
one
down
zero
one
up
one
down
pr_state
q1 q0
time
(zero) 0 0
0
1
0
1
1
0
1
0
0
1
X
X
X
0
1
X
X
0
1
X
(up)
0 1
(one)
1 0
(down) 1 1
pr_state
q1 q0
(zero) 0 0
(up) 0 1
0
0
(one)
1 0
(down) 1 1
pr_state
zero
y
0
up
one
down
nx_state
d1 d0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
A circuit that implements this FSM is depicted below, where, as usual, the lower section contains only
sequential logic (DFFs), while the upper section contains only the combinational part. The former stores
pr_state, while the latter is responsible for generating nx_state and the actual output, y.
The generation of t (=time) is also depicted in the figure. It consists of a counter that is synchronously
cleared at the next upward clock edge (recall that in our context reset is asynchronous, while clear is
synchronous) when its output value is max, thus resulting for t a waveform that stays low during max clock
pulses and high during one clock period. The counter can be any of those seen in Sections 14.2 and 14.3,
while the comparator can be that seen in Figure 12.15(a) of Section 12.7.
Finally, observe that this FSM resembles the general architecture described in Section 15.4 (see Figure
15.21(c)), which is proper of large state machines. However, for the case of 1kHz clock, it can be modeled
as a small state machine, as described in Section 15.2. Regarding the latter, please see the discussion
proposed at the end of this exercise.
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
y
clk
counter
comparator
clear
max
pr_state
q1
t
nx_state
d1
q1
q0
q0
d0
clk