Kits DLD Lab 8-6-16

LIST OF EXPERIMENTS
1. Verification of basic Logic Gates.

2. Implementing all individual gates with universal gates NAND &
NOR.
3. Design a circuit for the given canonical form, draw the circuit
diagram and verify the demorgan laws.
4. Design a combinational logic circuit for 4x1 MUX and verify the
truth table.
5. Design a combinational logic circuit for 1x4 De-MUX and verify the
truth table.
6. Verify the data read and data write operations for the IC 74189.
7. Design a gray code encoder and interface it to SRAM IC 74189 for
write operation display on seven segment display.
8. Design a gray code decoder and interface it to SRAM IC 74189 for
read operation display on seven segment display.
9. Construct Half Adder and Full Adder using Half Adder and verify
the truth table.
10. Verification
of
truth
tables
of
the
basic
Flip-Flops
with
Synchronous and Asynchronous modes.

11. Implementation of Master-Slave Flip-Flop with JK Flip-Flop and
verify the truth table for race around condition.
12. Design a decade counter and verify the truth table.
13. Design MOD-6 counter using D- Flip-Flop.
14. Construct 4-bit ring counter with T- Flip-Flop and verify the truth
table.
15.Design a 8 bit right shift register using D- Flip-Flop and verify
the truth table.
1.
VERIFICATION OF BASIC LOGIC GATES.
AIM:
To verify the truth tables of AND, OR, NOT, NAND, NOR, EX-OR gates.
APPARATUS:
1. Bread board IC trainer
2. IC 74LS08 (AND)
3. IC 74LS32 (OR)
4. IC 74LS04 (NOT)
5. IC 74LS00 (NAND)
6. IC 74LS02 (NOR)
7. IC 74LS86 (EX-OR)
8. Patch cards.
THEORY:
In digital electronic circuits as two logic levels Logic-I, Logic-O. These are also
known as HIGH and LOW logic levels.
There are two logic circuits.
1. Positive logic: In which 1 corresponding to HIGH, 0 corresponding to LOW.
2. Negative logic: In which 1 corresponding to LOW, 0 corresponding to HIGH.
BASIC OPERATIONS:
AND Gate:
IC 74LS08 is quad 2-i/p AND gate. It requires 5V DC. The o/p of AND
gate is HIGH when both the inputs are HIGH otherwise HIGH.
OR Gate:
IC 74LS32 is quad 2-i/p OR gate. It requires 5V DC. The o/p of OR gate is
LOW when both the inputs are LOW otherwise IIIGH.
NOT Gate:
IC 74LS04 is hex NOT gate. The o/p of NOF gate is always
complementing of i/p.
NAND Gate:
IC 74LS00 is quad 2-i/p NAND gate. It requires 5V DC. The o/p of NAND
gate is LOW when both the inputs are HIGH otherwise I 11GII.
NOR Gate:
IC 74LS02 is quad 2-i/p NOR gate. It requires 5v. The O/p of NOR gate is
HIGH when both e inputs are LOW otherwise LOW.
EX-OR Gate:
IC 74LS86 is quad 2-i/p EX-OR gate. It requires 5V DC. The o/p of EX-OR
gate is HIGH when two different inputs are applied otherwise LOW.
CIRCUIT DIAGRAMS:
AND GATE:
DIGRAM
TRUTH TABLES
0
0
1
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
0
0
1
OR GATE:
NOT GATE:
PIN
NAND GATE:
NOR GATE:
EX-OR GATE:
PROCEDURE:
1.+5V DC is applied at 1cc (pin no 14)of each IC w.r.t ground (pin no7).
2. 1/Ps are applied (at pin nos l&2) and output is taken from (pin no 3).
3. I/Ps are applied from toggle switches and o/p is observed at o/p indicators.
PRECATIONS:
1. Avoid loose connections on bread board.

2. Take care while make connections with NOT and NOR gates.
RESULT:
2.IMPLEMENTATION OF ALL INDIVIDUAL GATES WITH

UNIVERSAL GATES NAND & NOR.
AIM:
To develop the AND, OR, NOT gates using NAND and NOR gates.
APPARATUS:
2. IC 74LS00 (NAND)
3. IC 74LS02 (NOR)
4. Patch cards.
THEORY:
NAND gate:
NAND gate is a combination of AND & NOT gates. Thus NAND gate is
the inverse of AND gate. The output is low when all inputs are high. The
output is high for all the remaining combinations.
Logic equation is:
Digital IC for NAND: IC 7400.
NOR gate:
NOR gate is a combination of OR & NOT gates. Thus NOR gate is the inverse
of OR gate. When all or either of the inputs are high output is low. The
output of NOR gate is high only when all inputs are low.
Logic equation is:
Digital IC for NOR: IC 7402.
In digital electronics, a NAND gate (negative-AND) is a logic gate which

produces an output which is false only if all its inputs are true; thus its output
is complement to that of the AND gate. A LOW (0) output results only if both
the inputs to the gate are HIGH (1); if one or both inputs are LOW (0), a HIGH
(1) output results. It is made using transistors and junction diodes. By De
Morgan's theorem, AB=A+B, and thus a NAND gate is equivalent to inverters
followed by an OR gate.
The NAND gate is significant because any boolean function can be
implemented by using a combination of NAND gates. This property is called
functional completeness.
Digital systems employing certain logic circuits take advantage of NAND's
functional completeness
Like NAND gates, NOR gates are so-called "universal gates" that can be
combined to form any other kind of logic gate. For example, the first
embedded system, Apollo Guidance Computer, was built exclusively from
NOR gates, about 5,600 in total for the later versions. Today, integrated
circuits are not constructed exclusively from a single type of gate. Instead,
EDA tools are used to convert the description of a logical circuit to a netlist of
complex gates (standard cells) or transistors (full custom approach).
CIRCUIT DIAGRAMS:
AND GATE:
0
1
1
0
A
A
0
00
01
11
1
B
B
0
01
10
01
1
Y
Y
0
01
01
01
1
0
1
A
1
0
B
0
0
1
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
PROCEDURE:
1. +5V DC is applied at VCC (pin no 14) of each IC w.r.t ground (pin no7).
2. Connect the circuit as shown in circuit diagram
3. Inputs are applied to toggle switches and outputs are connected to output
LEDs.
4. Verify the truth tables as shown in the truth tables.
PRECATIONS:
2. Take care while make connections with VCC and GND.
3. Dont switch ON the kit till all connections are made.
RESULT:
3.VERIFICATION OF DE-MORGAN LAWS

AIM:
Design a circuit for the given conical form, draw the circuit diagram and verify
De-Morgan laws.
APPARATUS:
2. IC 7404, 7408, 7432
3. Patch cards.
THEORY:
In mathematics and computer science, a canonical, normal, or standard
form of a mathematical object is a standard way of presenting that object as
a mathematical expression. The distinction between "canonical" and "normal"
forms varies by subfield. In most fields, a canonical form specifies a unique

representation for every object, while a normal form simply specifies its form,
without the requirement of uniqueness.The canonical form of a positive
integer in decimal representation is a finite sequence of digits that does not
begin with zero.More generally, for a class of objects on which an equivalence
relation is defined, a canonical form consists in the choice of a specific object
in each class. For example, Jordan normal form is a canonical form for matrix
similarity, and the row echelon form is a canonical form, when one consider
as equivalent a matrix and its left product by an invertible matrix.In computer
science, and more specifically in computer algebra, when representing
mathematical objects in a computer, there are usually many different ways to
represent the same object. In this context, a canonical form is a
representation such that every object has a unique representation. Thus, the
equality of two objects can easily be tested by testing the equality of their
canonical forms. However canonical forms frequently depend on arbitrary
choices (like ordering the variables), and this introduces difficulties for testing
the equality of two objects resulting on independent computations. Therefore,
in computer algebra, normal form is a weaker notion: A normal form is a
representation such that zero is uniquely represented. This allows testing for
equality by putting the difference of two objects in normal form.Canonical
form can also mean a differential form that is defined in a natural (canonical)
way.In computer science, data that has more than one possible
representation can often be canonicalized into a completely unique
representation called its canonical form. Putting something into canonical
form is canonicalization.
CIRCUIT DIAGRAMS:
TRUTH TABLES:
A
A
AB
PROCEDURE:
0
1
1
1. +5V DC is
1
0
1
each
IC w.r.t
2.1 Connect
the
1
0
diagram
3. Inputs are
outputs
are
4. Verify the
tables.
+
B
1
A
B
B
A+
.
B
1
0
A
0
applied at VCC (pin no 14) of

ground (pin no7).
circuit as shown in circuit
applied to toggle switches and
connected to output LEDs.
truth tables as shown in the truth
PRECAUTIONS:
1
1
0
0
1. Avoid loose
connections on bread board.
RESULT:
4.41 MULTIPLEXER
AIM:
Design a Combinational Logic Circuit for 41 MUX and verify the truth
table.
APPARATUS:
2. IC 74153
3. Patch cards.
THEORY:
Multiplexers are very useful components in digital systems. They
transfer a large number of information units over a smaller number of
channels, (usually one channel) under the control of selection signals.
Multiplexer means many to one. A multiplexer is a circuit with many inputs
but only one output. By using control signals (select lines) we can select any
input to the output. Multiplexer is also called as data selector because the
output bit depends on the input data bit that is selected. The general
multiplexer circuit has 2n input signals, n control/select signals and 1 output
signal.
CIRCUIT DIAGRAM:
PIN DIAGRAM:
TRUTH TABLE:
PROCEDURE:
1. +5V DC is applied at VCC (pin no 16) w.r.t ground (pin no 8).
LEDs.
PRECAUTIONS:
RESULT:
5.
14 DE-MULTIPLEXER
AIM:
Design a combinational circuit for 14 De-MUX and verify the truth table.
APPARATUS:
2. IC 74156
3. Patch cards.
THEORY:
De-multiplexers perform the opposite function of multiplexers. They
transfer a small number of information units (usually one unit) over a larger
number of channels under the control of selection signals. The general demultiplexer circuit has 1 input signal, n control/select
signals and 2n output signals. De-multiplexer circuit can also be realized
using a decoder
circuit with enable.
PIN DIAGRAM:
IC
74139
TRUTH TABLE:
PROCEDURE:
1. +5V DC is applied at VCC (pin no 16) w.r.t ground (pin no 8).
LEDs.
PRECAUTIONS:
RESULT:
6.SRAM-74189
AIM:To verify the data read and data write operations for the IC74189
APPARATUS
1. 16X4 SRAM IC 74189
2. Digital IC trainer kit
3. Bread board
4. Patch cords
5. Connecting wires
1 No.
1 No.
1 No.
THEORY
The 74189 is a high speed 64-bit RAM organized as a 16-word by
4-bit array. Address inputs are buffered to minimize loading and are
fully decoded on- chip. The outputs are 3-state and are in high
impedance state whenever the Memory Enable (ME) input is HIGH. The
outputs are active only in the Read mode and the output data is the
complement of the stored data. Here A0-A3 are the address inputs, D1-D4
are data inputs, O1-O4 are inverted data outputs
Fig. 6.1: Logic diagram of SRAM for data read and write
operations
FUNCTION TABLE
OPERATION
H
All data outputs are high

Read mode )date outputs are
compliment of the RAM content)
Write mode(data inputs are

written on the memory; data
L
output are compliment of the
Ram content)
Table 6.1: SRAM Function table.
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Apply logic 0 to the chip select to turn on the IC.
3. Enter the 4-bit address to pins 1,15,14,13 & 4-bit data as input to pins
4,6,10,12 by applying logic 0 to pin-3 for write operation.
4. For read operation apply logic 1 to pin-3 & enter the address input to
pins 1,15,14,13 observe the read data from pins 5,7,9,11
5. Verify the read &write operations as per the truth table.
Truth Table for Write operation:
Truth Table for read operation:
PIN DIAGRAM:
Draw the pin configurations of IC74189 (SRAM)from Annexure-A

here
PRECAUTIONS:
1. Correct ICs should be properly placed on the IC bases using pin
diagrams.
2. The open circuit voltage of the power supply must be stable and close
to 5V.
3. Use multimeter probe tip to gently ease the IC out of breadboard. The
mid-section groove of the breadboard can be used to gently lift the IC.
Using bare hands might cause IC pins to break.
4. Pulse width and voltage level of pulse generator output is crucial for the
operation of the flip-flops.
5. In case the logic gate outputs do not make sense, check your circuit
thoroughly. If the problem is still not resolved, get the IC tested by the
technician.
RESULT: Verified the data read and data write operations for the
IC74189
VIVA
1)
2)
3)
4)
5)
6)
7)
QUESTIONS:
What is the difference between SRAM & DRAM?
What is the function of CS & WE in SRAM IC 74189?
What is meant by high impedance state?
How can you enable the SRAM for read &write operations?
What is 7-segment display?
Differentiate b/w RAM & ROM?
SRAM is volatile or Nonvolatile memory?
9. HALF ADDER AND FULL ADDER USING TWO

HALF ADDERS
AIM:
To construct half-adder and full adder using two half adders and verify
its truth table.
EQUIPMENT REQUIRED:
1. IC trainer kit.
2. ICS 7486, 7408, 7432.
3.Connecting wires/ patch chords
THEORY:
Half adder is a logic circuit that adds two bits. The half adder accepts
two binary digits on its inputs and produces two binary digits on its outputs,
a sum bit and a carry bit.
A Boolean equations for these outputs are
Sum(S)= A B
Carry(C) =AB
The sum output is A XOR B the carry output is A AND B. therefore sum is 1
when A and B are different carry is 1 when A and B are 1s.
Full adder is a logic circuit that adds two bits. The half adder accepts
two binary digits on its inputs and produces two binary digits on its outputs, a
sum bit and a carry bit.
Sum(S)= A B C
Carry(C)=AB+BC+AC
The sum output is A XOR B the carry output is A AND B. therefore sum
is 1 when A and B are different carry is 1 when A and B are 1s.
LOGIC SYMBOL:
CIRCUIT DIAGRAM:
HALF ADDER
FULL ADDER
TRUTH TABLE:
SU
M
0
CARR
Y
0
TRUTH TABLE:
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Su
m
0
1
1
0
1
0
0
1
PROCEDURE:
1. +5V DC is applied at VCC (pin no 14) of each IC
w.r.t ground (pin no7).
3. Inputs are applied to toggle switches and
outputs are connected to output LEDs.
4. Verify the truth tables of half adder as shown in the truth tables.
Carr
y
0
0
0
1
0
1
1
1
PRECATIONS:
RESULT:
The construction of half adder and full adder using half adder and the
verification of truth table is done.
10.BASIC FLIP FLOPS WITH SYNCHRONOUS AND

ASYNCHRONOUS MODES.
AIM:
Verify the truth tables of the basic flip flops with synchronous and
asynchronous modes.
EQUIPMENT REQUIRED:
1. IC trainer kit.
1. ICs 7400,7402
2. Connecting wires/ patch chords.
THEORY:
The Asynchronous RS Flip Flop (Latch):
Latch is a type of bi-stable circuit, similar to a flip-flop, which can reside in either of
two stable states by virtue of feedback arrangement. The main difference between
latches and flip-flops is in the method used for changing their state.
The synchronous RS flip flop:

Synchronous flip flop means that this flip flop is concerned with time. Digital
circuits can have a concept of time using a clock signal. The clock signal
simply goes from low-to-high and high-to-low in a short period time.
Rs flip flop is also called synchronous flip flop. This means that this flip flop is
concern with time. Digital circuits can have a concept of time using a clock
signal. The clock signal simply goes from low to high and high to low in a
short period of time.
CIRCUIT DIAGRAM:
S-R FLIP FLOP:
QN
S
CLK
QN
TRUTH TABLE:
S
0
0
1
1
0
1
0
1
J-K FLIP FLOP:
CL
K
1
1
1
1
Q
N
0
0
1
1
Q
N
1
1
0
1
RESPONSE
PRIVIOUS STATE
QN
~QN
UN DETERMINE
J
K
QN
CLK
QN
TRUTH TABLE
J
0
0
1
1
0
1
0
1
CL
K
1
1
1
1
Q
N
0
0
1
1
Q
N
1
1
0
1
RESPONSE
PRIVIOUS STATE
QN
~QN
TOGGLE
D- FLIP FLOP:
QN
D
CLK
QN
TRUTH TABLE
CL
Q
Q
D
K
N
N
0
1
0
1
1
1
1
0
RESPONSE
QN
~QN
T- FLIP FLOP:
TRUTH TABLE
T
0
1
CL
K
1
1
Q
N
1
0
Q
N
0
1
RESPONSE
~QN
QN
PROCEDURE:
1. +5V DC is applied at VCC (pin no 14)of each IC w.r.t ground (pin no7).
LEDs.
4. Verify the truth tables of NAND and NOR Latches as shown in the truth
tables.
PRECATIONS:
1.Avoid loose connections on bread board.
RESULT:
11.MASTER SLAVE JK FLIP-FLOP
AIM:
Implementations of master slave flip-flop with JK Flip-Flop and verify the truth
table for race around condition.
EQUIPMENT REQUIRED:
1. IC trainer kit.
2. ICs 7476
THEORY:
A master slave flip flop contains two clocked flip flops. The first is called
master and the second slave. When the clock is high the master is active. The
output of the master is set or reset according to the state of the input. As the
slave is inactive during this period its output remains in the previous state.
When clock becomes low the output of the slave flips flop changes because it
become active during low clock period. The final output of master slave flip
flop is the output of the slave flip flop. So the output of master slave flip flop
is available at the end of a clock pulse.
PIN DIAGRAM:
CONNECTION DIAGRAM:
TRUTH TABLE:
PROCEDURE:
1. +5V DC is applied at VCC (pin no 5)of
each IC w.r.t ground (pin no13).
LEDs.
4. Connect the NOT gate input to the pin no.1 and output to the pin no.6.
5. Apply the clock signal to the pin no.1
6. Verify the truth table and of the JK master slave flip-flop.
PRECATIONS:
RESULT:
12.DECADE COUNTER
AIM:
Design a decade counter and verify the truth table.
EQUIPMENT REQUIRED:
1. IC trainer kit.
2. ICs 7490
THEORY:
The decade counter (mod-10 counter) is used most often. In order to count
from 0 through 9, a counter with 3 flip-flops is not sufficient. With 4 flip-flops
one can count from 0 to15 (16 states). Out of these 16 states, we should skip
any 6 states. In the decade counter, when the output is 1010(for the 10th
clock pulse), all the flip-flops should be reset. Thus the outputs Q3 and Q1 are
given directly to the inputs of the AND gate and the outputs Q2 and Q0 are
given through inverters. Therefore, for the 10th clock pulse, the counter
output would be 1010 for a moment. This sends the output of the AND gate to
HIGH clearing all the flip-flops. Thus a decade counter has been developed.
PIN DIAGRAM:
TRUTH TABLE:
PROCEDURE:
1. Connect the circuit as shown in the figure.
2. The clock pulse is given to pin-14 of IC 7490.
3. The Vcc supply is given to pin-5 of IC 7490.
4. Pin-12 and pin-1 to be shorted.
5. Pins-2, 3 are Master Reset (MR) inputs and pins-6, 7 are Master Set (MS)
inputs.
6. Pins-13, 14 has no connections.
7. Pins-2, 3, 6, 7 are inputs and is always 0 so that it is connected to ground.
8. Pins-12, 9,8,11 are outputs.
9. Feed MR terminal with 1 and MS terminals with 0 then the display
shows0.
10.Feed MR terminal with 0 and MS terminals with 1 then the display
shows9.
11.Feed MR terminal with 0 and MS terminals with 0,now apply clock then
the output varies between the values 0 and 9.
PRECAUTIONS:
1. Avoid loose connections on the bread board.
2. No connections are to be given to pins-13, 14.
3. Vcc should not exceed +5v.
RESULT:
13. MOD-6 Counter

AIM:
Design a MOD-6 counter with D Flip-Flop and verify the truth table.
EQUIPMENT REQUIRED:
1. IC trainer kit.
2. ICs 7474 - 2nos
THEORY:
In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has
occurred, often in relationship to a clock signal. The most common type is a
sequential digital logic circuit with an input line called the "clock" and multiple
output lines. The values on the output lines represent a number in the binary
or BCD number system. Each pulse applied to the clock input increments or
decrements the number in the counter.
A counter circuit is usually constructed of a number of flip-flops
connected in cascade. Counters are a very widely-used component in digital
circuits, and are manufactured as separate integrated circuits and also
incorporated as parts of larger integrated circuits.
CIRCUIT DIAGRAM:
Q1
Q2
Q3
PRESET
PR
PR
D PR
D-Q1 D D-Q2 D D-Q3
FF1
FF2
FF3
CLR
CLR
CLR
Q1
Q2
Q3
CLK
CLR
TRUTH TABLE:
Clock
Pulse
0
1
2
3
4
5
Q3
0
1
0
1
0
1
Q2
0
0
1
1
0
0
Q1
0
0
0
0
1
1
PROCEDURE:
2.Apply vcc to pin -14 and gnd to pin-7 for all ICs.
3.Held the preset at high position.
4.Apply the clock pulse and observe the out puts.
PRECAUTIONS:
RESULT:
14. 4-Bit Ring Counter

AIM:
Design a 4-Bit Ring counter with D Flip-Flop and verify the truth table.
EQUIPMENT REQUIRED:
1. IC trainer kit.
2. ICs 7474 - 2nos
THEORY:
In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has
occurred, often in relationship to a clock signal. The most common type is a
sequential digital logic circuit with an input line called the "clock" and multiple
output lines. The values on the output lines represent a number in the binary
or BCD number system. Each pulse applied to the clock input increments or
decrements the number in the counter.
A counter circuit is usually constructed of a number of flip-flops
connected in cascade. Counters are a very widely-used component in digital
circuits, and are manufactured as separate integrated circuits and also

incorporated as parts of larger integrated circuits.
A ring counter is a circular shift register which is initiated such that only one of
its flip-flops is the state one while others are in their zero states.
A ring counter is a Shift Register (a cascade connection of flip-flops) with the
output of the last one connected to the input of the first, that is, in a ring. Typically, a
pattern consisting of a single bit is circulated so the state repeats every n clock
cycles if n flip-flops are used.
CIRCUIT DIAGRAM:
PRESET Q1
Q2
Q3
Q4
PRESET
PR
PR
PR
PR
D Q1 D Q2 D Q3 D Q4
DFF1
DFF2
DFF3
DFF4
CLR
CLR
CLR
CLR
Q1
Q2
Q3
Q4
CLK
CLR
TRUTH TABLE:
Clock
Pulse
0
1
2
3
4
Q4
Q3
1
0
0
0
1
0
1
0
0
0
Q2
0
0
1
0
0
Q1
0
0
0
1
0
PROCEDURE:
3.apply clock pulses to pin 3&11 for all ICs simultaneously.
4.Short t preset of flip-flop from ff2 to ff4and held it in high position .
5. Short t clear i/ps and held it in low position to clear the o/ps.
6.Now the out put of the ff1 held at high using preset at low position. And now
the position of
preset of ff1 is held at high position.
PRECAUTIONS:
RESULT:
15. 8-Bit Shift Register

AIM:
Design a 8-Bit Shift Register using D Flip-Flop and verify the truth table.
EQUIPMENT REQUIRED:
1. IC trainer kit.
2. ICs 7474 - 4nos
THEORY:
In digital circuits, a shift register is a cascade of flip flops, sharing the

same clock, in which the output of each flip-flop is connected to the 'data'
input of the next flip-flop in the chain, resulting in a circuit that shifts by one
position the 'bit array' stored in it, 'shifting in' the data present at its input
and 'shifting out' the last bit in the array, at each transition of the clock input.
More generally, a shift register may be multidimensional, such that its 'data
in' and stage outputs are themselves bit arrays: this is implemented simply
by running several shift registers of the same bit-length in parallel.
This configuration allows conversion from serial to parallel format. Data
is input serially, as described in the SISO section above. Once the data has
been clocked in, it may be either read off at each output simultaneously, or it
can be shifted out
In this configuration, each flip-flop is edge triggered. The initial flip-flop
operates at the given clock frequency. Each subsequent flip-flop halves the
frequency of its predecessor, which doubles its duty cycle. As a result, it takes
twice as long for the rising/falling edge to trigger each subsequent flip-flop;
this staggers the serial input in the time domain, leading to parallel output.
In cases where the parallel outputs should not change during the serial
loading process, it is desirable to use a latched or buffered output. In a
latched shift register (such as the 74595) the serial data is first loaded into an
internal buffer register, then upon receipt of a load signal the state of the
buffer register is copied into a set of output registers. In general, the practical
application of the serial-in/parallel-out shift register is to convert data from
serial format on a single wire to parallel format on multiple wires.
CIRCUIT DIAGRAM:
D
D
D
D
D
D
D
D
-Q1 - Q2- Q3Q4
- Q5- Q6
- Q7
-Q8
PRE
PRE
PR
PR PR PR
F DQ2
F DF Q3
FQ5
FQ6
FQ7
FQ8
DQ1
DF Q4DPR
DPR
DPR
DPR
F
F
F
F
F
F
F
F
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CLR
CLR
1 CLR
2 CLR
3 CLR
4
5 CLR
6 CLR
7 CLR
8
CLK
CLR
TRUTH TABLE:
Cloc
k
Puls
e
0
1
2
3
4
Q8
Q7
1
0
0
0
0
0
1
0
0
0
Q6
0
0
1
0
0
Q5
Q4
Q3
Q2
Q1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
6
7
8
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
PROCEDURE:
3.apply clock pulses to pin 3&11 for all ICs simultaneously.
4.Short t preset of flip-flop from ff2 to ff8and held it in high position .
5. Short t clear i/ps and held it in low position to clear the o/ps.
6.Now the out put of the ff1 held at high using preset at low position. And now
the position of
preset of ff1 is held at high position.
PRECAUTIONS:
RESULT:
1.Draw the circuit diagram and verify the

Commutative law
Design a circuit for the given conical form, draw the circuit diagram and verify
De-Morgan laws.
APPARATUS:
2. IC 7404, 7408, 7432
3. Patch cards.
THEORY:
In mathematics and computer science, a canonical, normal, or standard
form of a mathematical object is a standard way of presenting that object as
a mathematical expression. The distinction between "canonical" and "normal"
forms varies by subfield. In most fields, a canonical form specifies a unique
representation for every object, while a normal form simply specifies its form,
without the requirement of uniqueness. The canonical form of a positive
integer in decimal representation is a finite sequence of digits that does not

begin with zero. More generally, for a class of objects on which an
equivalence relation is defined, a canonical form consists in the choice of a
specific object in each class. For example, Jordan normal form is a canonical
form for matrix similarity, and the row echelon form is a canonical form, when
one consider as equivalent a matrix and its left product by an invertible
matrix. In computer science, and more specifically in computer algebra, when
representing mathematical objects in a computer, there are usually many
different ways to represent the same object. In this context, a canonical form
is a representation such that every object has a unique representation. Thus,
the equality of two objects can easily be tested by testing the equality of their
canonical forms. However canonical forms frequently depend on arbitrary
choices (like ordering the variables), and this introduces difficulties for testing
the equality of two objects resulting on independent computations. Therefore,
in computer algebra, normal form is a weaker notion: A normal form is a
representation such that zero is uniquely represented. This allows testing for
equality by putting the difference of two objects in normal form.Canonical
form can also mean a differential form that is defined in a natural (canonical)
way.In
computer
representation
can
science,
often
data
be
that
has
canonicalized
more
into
than
a
one
completely
possible
unique
representation called its canonical form. Putting something into canonical

form is canonicalization.
CIRCUIT DIAGRAMS:
TRUTH TABLES:
A
A
AB
+
B
PROCEDURE:
0
1
1. +5V DC is
1
0
each
IC w.r.t
2.1 Connect
the
1
diagram
3. Inputs are
outputs
are
4. Verify the
tables.
A
B
A
0
B
A+
.
B
applied at VCC (pin no 14) of

ground (pin no7).
circuit as shown in circuit
applied to toggle switches and
connected to output LEDs.
truth tables as shown in the truth
PRECAUTIONS:
1
1
1. Avoid loose
connections on bread board.
RESULT:
2. Construct Half Adder and using NAND gates

and verify the truth table
AIM:
To construct half-adder and full adder using two half adders and verify
its truth table.
EQUIPMENT REQUIRED:
1. IC trainer kit.
2. ICS 7486, 7408, 7432.
3.Connecting wires/ patch chords
THEORY:
Half adder is a logic circuit that adds two bits. The half adder accepts
Sum(S)= A B
Carry(C) =AB
The sum output is A XOR B the carry output is A AND B. therefore sum is 1
when A and B are different carry is 1 when A and B are 1s.
Full adder is a logic circuit that adds two bits. The half adder accepts
Sum(S)= A B C
Carry(C)=AB+BC+AC
The sum output is A XOR B the carry output is A AND B. therefore sum
is 1 when A and B are different carry is 1 when A and B are 1s.
LOGIC SYMBOL:
CIRCUIT DIAGRAM:
HALF ADDER
TRUTH TABLE:
SU
M
0
CARR
Y
0
Half Adder using NAND Gates:
A
B
SU
M
CARR
Y
PROCEDURE:
LEDs.
4. Verify the truth tables of half adder as shown in the truth tables.
PRECATIONS:
RESULT:
The construction of half adder and full adder using half adder and the
verification of truth table is done.
3.ENCODER
AIM: To design and implement encoder and decoder using logic gates and
study of IC 7445 and IC 74147.
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
2.
3.
COMPONENT
3 I/P NAND GATE
OR GATE
NOT GATE
IC TRAINER KIT
PATCH CORDS
SPECIFICATION
IC 7410
IC 7432
IC 7404
-
QTY.
2
3
1
1
27
THEORY:
ENCODER:
An encoder is a digital circuit that performs inverse operation of a decoder.
n
An encoder has 2 input lines and n output lines. In encoder the output lines
generates the binary code corresponding to the input value. In octal to
binary encoder it has eight inputs, one for each octal digit and three output
that generate the corresponding binary code. In encoder it is assumed that
only one input has a value of one at any given time otherwise the circuit is
meaningless. It has an ambiguila that when all inputs are zero the outputs
are zero. The zero outputs can also be generated when D0 = 1.
LOGIC DIAGRAM FOR ENCODER
Y1
1
0
0
0
0
0
0
Y2
0
1
0
0
0
0
0
PROCEDURE:
Y3
0
0
1
0
0
0
0
INPUT
Y4 Y5
0
0
0
0
0
0
1
0
0
1
0
0
0
0
Y6
0
0
0
0
0
1
0
Y7
0
0
0
0
0
0
1
A
0
0
0
1
1
1
1
OUTPU
T
B
0
1
1
0
0
1
1
C
1
0
1
0
1
0
1
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus the design and implementation of encoder and decoder using logic
gates and study of IC 7445 and IC 74147 were done.
4.Design a logic diagram for Y=(B+C)A using AND

gates.
AIM:
To develop the Logic Diagram for Expression.
APPARATUS:
2. IC 74LS08 (AND)
3. IC 74LS32 (OR)
4. Patch cards.
CIRCUIT DIAGRAMS:
B
A
(B
+C
)A
C
TRUTH TABLE:
A
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Y=A(B
+C)
0
0
0
0
0
1
1
1
PROCEDURE:
LEDs.
PRECATIONS:
RESULT:
5.Design a Logic diagram for J-k flip flop using

AND and NAND Gates.
AIM:
Verify the truth tables of the basic flip flops with synchronous and
asynchronous modes.
EQUIPMENT REQUIRED:
2. IC trainer kit.
3. ICs 7400,7402
THEORY:
Latch is a type of bi-stable circuit, similar to a flip-flop, which can reside in either of
two stable states by virtue of feedback arrangement. The main difference between
latches and flip-flops is in the method used for changing their state.
Synchronous flip flop means that this flip flop is concerned with time. Digital
circuits can have a concept of time using a clock signal. The clock signal
simply goes from low-to-high and high-to-low in a short period time.
Rs flip flop is also called synchronous flip flop. This means that this flip flop is
concern with time. Digital circuits can have a concept of time using a clock
signal. The clock signal simply goes from low to high and high to low in a
short period of time.
CIRCUIT DIAGRAM:
J
K
QN
CLK
QN
TRUTH TABLE:
J
CLK
QN
QN
RESPONSE
0
0
0
1
1
0
0
1
0
1
0
1
1
1
1
0
0
0
1
1
0
1
1
0
0
PRIVIOUS STATE
PRIVIOUS STATE
QN
~QN
TOGGLE
PROCEDURE:
1. +5V DC is applied at VCC (pin no 14)of each IC w.r.t ground (pin no7).
LEDs.
4. Verify the truth tables of NAND and NOR Latches as shown in the truth
tables.
PRECATIONS:
RESULT:
6.DECODER
AIM: To design and implement encoder and decoder using logic gates and
study of IC 7445 and IC 74147
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
2.
3.
COMPONENT
3 I/P NAND GATE
OR GATE
NOT GATE
IC TRAINER KIT
PATCH CORDS
SPECIFICATION
IC 7410
IC 7432
IC 7404
-
QTY.
2
3
1
1
27
THEORY:
DECODER:
A decoder is a multiple input multiple output logic circuit which converts
coded input into coded output where input and output codes are different.
The input code generally has fewer bits than the output code. Each input
code word produces a different output code word i.e there is one to
one mapping can be expressed in truth table. In the block diagram of decoder
circuit the encoded
information is present as n input producing
2n possible outputs. 2n output
values are from 0 through output 2n-1.
TRUTH TABLE:
PROCEDURE:
(iv)
Connections are given as per circuit diagram.
(v) Logical inputs are given as per circuit diagram.
(vi) Observe the output and verify the truth table.
RESULT:
Thus the design and implementation of encoder and decoder using logic
gates and study of IC 7445 and IC 74147 were done.
P a g e | 49
Dept. of Electronics and Communication Engineering

Kits DLD Lab 8-6-16

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LIST OF EXPERIMENTS

1. Verification of basic Logic Gates.

Synchronous and Asynchronous modes.

VERIFICATION OF BASIC LOGIC GATES.

1. Avoid loose connections on bread board.

2.IMPLEMENTATION OF ALL INDIVIDUAL GATES WITH

Digital IC for NAND: IC 7400.

Digital IC for NOR: IC 7402.

In digital electronics, a NAND gate (negative-AND) is a logic gate which

3.VERIFICATION OF DE-MORGAN LAWS

forms varies by subfield. In most fields, a canonical form specifies a unique

applied at VCC (pin no 14) of

All data outputs are high

Write mode(data inputs are

Truth Table for read operation:

Draw the pin configurations of IC74189 (SRAM)from Annexure-A

9. HALF ADDER AND FULL ADDER USING TWO

10.BASIC FLIP FLOPS WITH SYNCHRONOUS AND

The synchronous RS flip flop:

J-K FLIP FLOP:

11.MASTER SLAVE JK FLIP-FLOP

13. MOD-6 Counter

14. 4-Bit Ring Counter

circuits, and are manufactured as separate integrated circuits and also

15. 8-Bit Shift Register

In digital circuits, a shift register is a cascade of flip flops, sharing the

1.Draw the circuit diagram and verify the

integer in decimal representation is a finite sequence of digits that does not

representation called its canonical form. Putting something into canonical

applied at VCC (pin no 14) of

2. Construct Half Adder and using NAND gates

Half Adder using NAND Gates:

LOGIC DIAGRAM FOR ENCODER

(i) Connections are given as per circuit diagram.

4.Design a logic diagram for Y=(B+C)A using AND

To develop the Logic Diagram for Expression.

5.Design a Logic diagram for J-k flip flop using

Dept. of Electronics and Communication Engineering

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