University of California, Irvine

Fall 2016

EECS 119 VLSI Circuit Design

Instructor:
e-mail:
Office:
Office Hours:
Text:.
Reference:

Maqsood A. Chaudhry
mchaudhr@uci.edu; chaudhry@fullerton.edu
MSTB 218
TTh 7:00-8:00 PM
Digital Integrated Circuits A Design Perspective by Rabaey,
Chandrakasan and Nikolic, 2nd edition, Prentice Hall, 2003.
Microelectronic Circuits by Sedra and Smith, 7th edition, Oxford, 2015
Topics to be Covered

Week Topic
1

The Devices

Reading
Assignment
Chapter 3

The CMOS Inverter

Chapter 5

The Manufacturing Process

Chapter 2

4,5
6

Designing Combinational Logic Chapter 6

Gates in CMOS
Mid-Term Exam
Chapter 2,3,5,6

6,7

The Wire

Chapters 4

7,8,9 Designing Sequential Logic

Chapter 7
Circuits
10
Designing Memory and Array Chapter 12
Structures
11
Final Examination
Cumulative
Please Note:
EECS 119 will cover wide range of topics, from the fundamentals of CMOS digital
microelectronic systems all the way to VLSI system design. Although we will cover both
circuit and system aspects of the VLSI design, more emphasis will be placed on the
broader view of the VLSI circuits and system.
Students are expected to have taken all the prerequisites (or equivalent) of the course and
fully understand the structure, operation and characteristics and models for analysis of
MOS transistors. In addition, students are expected to be well versed in the analysis and
design of digital logic circuits.
Prerequisites will be enforced except for graduate students. This is a requirement set by

the department due to accreditation issues.

Add/Drop Procedure: Students are required to use WebReg or equivalent for all
add/drop actions during the first two weeks of class. This is a requirement set by the
department. No adds will be considered after the first two weeks.
Teaching Assistant: Kaveh Shahverdi [kshahver@uci.edu]
Midterm and project information:
One midterm will be given covering the basics of digital CMOS design. The exam will be
a variable mix of short answer questions, with usually a term, definition or an explanatory
sentence required, problems in which a circuit sketch or similar diagram must be drawn
and/or annotated, and analytical problems in which, for example, an equation must be
derived.
No homework problem sets are planned, but a few quizzes may also be given, with the
goal of providing you with feedback on your understanding of the material.
Please note that there will be absolutely NO "make-up" exams or quizzes! In case you
miss a mid-term for reasons beyond your control, weight of the mid-term will be added to
the final examination.
Four projects of increasing complexity will be assigned the details of which will be
provided at the time the projects are assigned.
Final Exam: The final will be comprehensive. A missed final will be dealt with
according to University regulations on incompletes and withdrawals.
Mid-Term Examination
Quizzes
Final Examination
Projects and Quizzes

20%
10%
30%
40%