1.

0 Intel 80486
The Intel 486 ("four-eight-six"), also known as the i486 or 80486 is a higher
performance follow-up to the Intel 80386 microprocessor. The 486 was
introduced in 1989 and was the first tightly pipelined x86 design as well as
the first x86 chip to use more than a million transistors, due to a large onchip cache and an integrated floating-point unit. It represents a fourth
generation of binary compatible CPUs since the original 8086 of 1978.
A 50 MHz 486 executes around 40 million instructions per second on average
and is able to reach 50 MIPS peak performance.
The i486 does not have the usual 80-prefix because of a court ruling that
prohibits trademarking numbers (such as 80486). Later, with the introduction
of the Pentium brand, Intel began branding its chips with words rather than
numbers.
The instruction set of the i486 is very similar to its predecessor, the Intel
80386, with the addition of only a few extra instructions, such as CMPXCHG
which implements a compare-and-swap atomic operation and XADD, a fetchand-add atomic operation returning the original value (unlike a standard ADD
which returns flags only).
From a performance point of view, the architecture of the i486 is a vast
improvement over the 80386. It has an on-chip unified instruction and data
cache, an on-chip floating-point unit (FPU) and an enhanced bus interface
unit. Due to the tight pipelining, sequences of simple instructions (such as
ALU reg,reg and ALU reg,im) could sustain a single clock cycle throughput
(one instruction completed every clock). These improvements yielded a
rough doubling in integer ALU performance over the 386 at the same clock
rate. A 16-MHz 486 therefore had a performance similar to a 33-MHz 386,
and the older design had to reach 50 MHz to be comparable with a 25-MHz
486 part.
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1.1 Architecture of 80486

The 80486 is made up of a complete 32-Bit architecture which includes:
Address and data buses, Registers, 8, 16 and 32-Bit data types. One of the
most obvious feature included in a 80486 is a built in math coprocessor. This
coprocessor is essentially the same as the 80387 processor used with a
80386, but being integrated on the chip allows it to execute math
instructions about three times as fast as a 80386/387 combination.
80486 is an 8Kbyte code and data cache. To make room for the additional
signals, the 80486 is packaged in a 168 pin, pin grid array package instead
of the 132 pin PGA used for the 80386.

1.2 Intel 80486 Buses

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Early 486 machines were equipped with several ISA slots (using an emulated
PC/AT-bus) and sometimes one or two 8-bitonly slots (compatible with the
PC/XT-bus). Many motherboards enabled overclocking of these up from the
default 6 or 8 MHz to perhaps 16.7 or 20 MHz (half the i486 bus clock) in a
number of steps, often from within the BIOS setup. Especially older
peripheral cards normally worked well at such speeds as they often used
standard MSI chips instead of slower (at the time) custom VLSI designs. This
could give significant performance gains (such as for old video cards moved
from a 386 or 286 computer, for example). However, operation beyond 8 or
10 MHz could sometimes lead to stability problems, at least in systems
equipped with SCSI or sound cards.
Some motherboards came equipped with a 32-bit bus called EISA that was
backward compatible with the ISA-standard. EISA offered a number of
attractive features such as increased bandwidth, extended addressing, IRQ
sharing, and card configuration through software (rather than through
jumpers, DIP switches, etc.) However, EISA cards were expensive and
therefore mostly employed in servers and workstations. Consumer desktops
often used the simpler but faster VESA Local Bus (VLB), unfortunately
somewhat prone to electrical and timing-based instability; typical consumer
desktops had ISA slots combined with a single VLB slot for a video card. VLB
was gradually replaced by PCI during the final years of the 486 period. Few
Pentium class motherboards had VLB support as VLB was based directly on
the i486 bus; it was no trivial matter adapting it to the quite different P5
Pentium-bus. ISA persisted through the P5 Pentium generation and was not
completely displaced by PCI until the Pentium III era.
Late 486 boards were normally equipped with both PCI and ISA slots, and
sometimes a single VLB slot as well. In this configuration VLB or PCI
throughput suffered depending on how buses were bridged. Initially, the VLB
slot in these systems was usually fully compatible only with video cards
(quite fitting as "VESA" stands for Video Electronics Standards Association);
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VLB-IDE, multi I/O, or SCSI cards could have problems on motherboards with
PCI slots. The VL-Bus operated at the same clock speed as the i486-bus
(basically being a local 486-bus) while the PCI bus also usually depended on
the i486 clock but sometimes had a divider setting available via the BIOS.
This could be set to 1/1 or 1/2, sometimes even 2/3 (for 50 MHz CPU clocks).
Some motherboards limited the PCI clock to the specified maximum of 33
MHz and certain network cards depended on this frequency for correct bitrates. The ISA clock was typically generated by a divider of the CPU/VLB/PCI
clock (as implied above).
One of the earliest complete systems to use the 486 chip was the Apricot VX
FT, produced by United Kingdom hardware manufacturer Apricot Computers.
Even overseas in the United States it was popularised as "The World's First
486" in the September 1989 issue of Byte magazine (shown right).

Later 486 boards also supported Plug-And-Play, a specification designed by

Microsoft that began as a part of Windows 95 to make component installation
easier for consumers.

The successor to the 80386 processor, Intel 80486 (i486) included many
changes to its microarchitecture that resulted in significant performance
improvements:

8 KB unified level 1 cache for code and data was added to the CPU. In
later versions of the 80486 the size of level 1 cache was increased to

16 KB.
Execution time of instructions was significantly reduced. Many load,
store and arithmetic instructions executed in just one cycle (assuming
that the data was already in the cache).
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Intel 486 featured much faster bus transfers - 1 CPU cycle as opposed

to two or more CPU cycles for the 80386 bus.

Floating-point unit was integrated into 80486DX CPUs. This eliminated
delay in communications between the CPU and FPU. Furthermore, all
floating-point instructions were optimized - they required fewer number

of CPU cycles to execute.

Clock-doubling and clock-tripling technology was introduced in faster
versions of Intel 80486 CPU. These i486 processors could run in
existing motherboards with 20 - 33 MHz bus frequency, while running
internally at two or three times of bus frequency. 80486SX2 and
80486DX2 were clock-doubled version, and 80486DX4 was a clocktripled version. AMD also produced 80486DX5 or X5 - clock-quadrupled

version of the 80486.

Power management features and System Management Mode (SMM)
became a standard feature of the processor.

A few different variations of the 80486 microprocessors were produced. Two

most common versions are 80486DX with integrated FPU and 80486SX
without integrated FPU. There were also low power versions and embedded
80486 microprocessors.

Intel 80486 microprocessor was produced at speeds up to 100 MHz. AMD

produced even faster 120 and 133 MHz versions of the 80486, and
manufactured in small quantities 150 MHz and possibly 166 MHz versions.

2.0 Skylake
Skylake is the codename used by Intel for a processor microarchitecture
which was launched in August 2015 as the successor to the Broadwell
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microarchitecture. Skylake is a microarchitecture redesign using the same 14

nm manufacturing process technology as its predecessor Broadwell, serving
as a "tock" in Intel's "tick-tock" manufacturing and design model. According
to Intel, the redesign brings greater CPU and GPU performance and reduced
power consumption. It will be succeeded by Kaby Lake and Cannonlake.
Like its predecessor, Broadwell, Skylake is available in four variants,
identified by the suffixes "S" (SKL-S), "H" (SKL-H), "U" (SKL-U), and "Y" (SKLY). SKL-S contains an overclockable "K" variant with unlocked multipliers. The
H, U and Y variants are manufactured in ball grid array (BGA) packaging,
while the S variant is manufactured in land grid array (LGA) packaging using
a new socket, LGA 1151. Skylake is used in conjunction with Intel 100 Series
chipsets, also known as Sunrise Point.
The major changes between the Haswell and Skylake architectures include
the removal of the fully integrated voltage regulator (FIVR) introduced with
Haswell. On the variants that will use a discrete Platform Controller Hub
(PCH), Direct Media Interface (DMI) 2.0 is replaced by DMI 3.0, which allows
speeds of up to 8 GT/s.
Skylake's U and Y variants support one DIMM slot per channel, while H and S
variants support two DIMM slots per channel. Skylake's launch and sales
lifespan occur at the same time as the ongoing SDRAM market transition,
with DDR3 SDRAM memory gradually being replaced by DDR4 memory.
Rather than working exclusively with DDR4, the Skylake microarchitecture
remains backward compatible by interoperating with both types of memory.
Accompanying the microarchitecture's support for both memory standards, a
new SO-DIMM type capable of carrying either DDR3 or DDR4 memory chips,
called UniDIMM, was also announced.
Other enhancements include Thunderbolt 3.0, SATA Express, Iris Pro graphics
with Direct3D feature level 12_1 with up to 128 MB of L4 eDRAM cache on
certain SKUs. The Skylake line of processors retires VGA support, while
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supporting up to five monitors connected via HDMI 1.4, DisplayPort 1.2 or

Embedded DisplayPort (eDP) interfaces. HDMI 2.0 (4K@60 Hz) is only
supported on motherboards equipped with Intels Alpine Ridge Thunderbolt
controller.
The Skylake instruction set changes include Intel MPX (Memory Protection
Extensions), Intel SGX (Software Guard Extensions), and Intel ADX (MultiPrecision Add-Carry Instruction Extensions). The Xeon variant also has
Advanced Vector Extensions 3.2 ("AVX-512F").
Skylake-based laptops may use wireless technology called Rezence for
charging,

and

other

wireless

technologies

for

communication

with

peripherals. Many major PC vendors have agreed to use this technology in

Skylake-based laptops, which should be released by the end of 2015.
The integrated GPU of Skylake's S variant supports DirectX 12 Feature Level
12_1, OpenGL 4.4 and OpenCL 2.0 standards, as well as some modern
hardware video encoding/decoding formats such as VP9 (GPU accelerated
decode only), VP8 and HEVC (hardware accelerated 8-bit encode/decode and
GPU accelerated 10-bit decode).
Intel also released unlocked (capable of overclocking) mobile Skylake CPUs.
Unlike previous generations, Skylake-based Xeon E3 no longer works with a
desktop chipset that supports the same socket, and requires either the C232
or the C236 chipset to operate.

2.1 Skylake Architecture

Improved front-end, deeper out-of-order buffers, improved execution units,
more execution units (third vector integer ALU(VALU)), more load/store
bandwidth, improved hyper-threading (wider retirement), speedup of AESGCM and AES-CBC by 17% and 33% accordingly.
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14 nanometer (nm) manufacturing process

LGA 1151 socket for desktop processors
100 Series chipset (Sunrise Point)
Thermal design power (TDP) up to 95 W (LGA 1151)
Support for both DDR3L SDRAM and DDR4 SDRAM in mainstream
variants, using custom UniDIMM SO-DIMM form factor with up to 64 GB
of RAM on LGA 1151 variants. Usual DDR3 memory is also supported
by certain motherboard vendors even though Intel doesn't officially

support it.
Support for 16 PCI Express 3.0 lanes from CPU, 20 PCI Express 3.0

lanes from PCH (LGA 1151)

Support for Thunderbolt 3 (Alpine Ridge)
64 to 128 MB L4 eDRAM cache on certain SKUs
Up to four cores as the default mainstream configuration
AVX-512: F, CDI, VL, BW, and DQ for some future Xeon variants, but not

Xeon E3
Intel MPX (Memory Protection Extensions)
Intel SGX (Software Guard Extensions)
Intel Speed Shift
Skylake's integrated Gen9 GPU supports Direct3D 12 at the feature

level 12_1
Full fixed function HEVC Main/8bit encoding/decoding acceleration.
Hybrid/Partial HEVC Main10/10bit decoding acceleration. JPEG encoding
acceleration for resolutions up to 16,00016,000 pixels. Partial VP9
encoding/decoding acceleration.

3.0 Comparison Between Intel Skylake and Intel 80486

1)

Skylake: have features that enable CPU and graphics overclocking

with finer-grain tuning. In addition, The new processors contain 8 MB of Intel

Smart Cache, allowing customers to gain faster access to their data.
Intel 80486: 8 KB unified level 1 cache for code and data was added to the
CPU. In later versions of the 80486 the size of level 1 cache was increased to
16 KB.
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2)

Skylake: Intel also launched a new Z170 chipset, which allows for CPU

overclocking enablement and graphics overclocking enablement. In addition,

the processors' new overclocking capabilities enable the ability to increase
memory frequency and contain finer-grain increments.
Intel 80486: Clock-doubling and clock-tripling technology was introduced in
faster versions of Intel 80486 CPU. These i486 processors could run in
existing motherboards with 20 - 33 MHz bus frequency, while running
internally at two or three times of bus frequency.
3)

Skylake: The processors include Intel Turbo Boost Technology 2.0,

increasing the processor frequency to up to 4.2 GHz when applications need

more performance, as well as Intel Hyper-Threading Technology to allow
multitasking for processor cores.
Intel 80486: i486 processors could run in existing motherboards with 20 33 MHz bus frequency, while running internally at two or three times of bus
frequency. 80486SX2 and 80486DX2 were clock-doubled version, and
80486DX4 was a clock-tripled version. AMD also produced 80486DX5 or X5 clock-quadrupled version of the 80486.
4)

Skylake: Speed Shift adds new power domains (System Agent and

eDRAM I/O) and gives the hardware more control than ever over power
states and the process of transitioning between them, so the system can
save less energy in the whole process.
Intel 80486: Power management features and System Management
Mode (SMM)

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