International Journal of Advanced Engineering Research and Technology (IJAERT) 164

Volume 4 Issue 5, May 2016, ISSN No.: 2348 8190

SUBSTANTIATION & ANALYSIS OF A MOSFET COMPACT MODEL

USING BSIM3V3.2.2
1

Manjari Sharma, Ajay Kumar Yadav, Dr. Kshitij Shinghal

M.Tech, EC Department, Mewar University Chittorgarh, Rajasthan, INDIA
2
Asst.Professor, College of Engineering and Rural Technology Meerut INDIA
3
Professor, M.I.T. Muradabad

ABSTRACT
This Paper shows a compact model for MOSFET having
some of the important areas such as carrier mobility,
current. A comparison is done between BSIM3v3.2.2
and BSIM3v3.1 emphasizing the domain of mobility and
current.
Since Carrier mobility is one of the most
important parameters affecting the I-V characteristics of
MOSFETs. Hence, accurate mobility models that
account for all the important scattering mechanisms are
an essential requirement for predictive MOS device
simulation. A temperature dependence of current is been
analysed over a temperature range (50C to 150C), and a
Temperature independent MOSFET-current reference
only is designed with MOSFET especially for military
applications. This thesis also includes a method which
converts the NAND and NOR gate to their inverter
equivalent circuit and hence the noise margin for
different CMOS logics (Inverter, NAND, NOR) are
found by simulation using their inverter equivalent
model and the effect of variation of temperature is
observed in the transfer characteristics for each of
inverter equivalent.

I. INTRODUCTION
The industry has
achieved an
outstanding growth
over previous
couple
of decades, principally thanks to the speedy advances in
integration technology and huge scale systems style. The
employment of integrated circuits in superior computing,
telecommunications and shopper physical science has
been growing at a really quick pace.[1]
MOSFET (metal oxide field effect transistor)is a
4 terminal device and is the backbone of electronics
industry. Although MOS technology became practical
much later after their invention in early 1960, with the
first several generation producing only n-type
transistor.[2] It was in the mid-1960s that CMOS
devices (Complementary MOS i.e. both n-type and ptype transistor) were introduced initiating a revolution in
the semiconductor industry.[3] In the present time the
CMOS technology rapidly captured the digital market
and the crucial property of CMOS is that it dissipates
power only during switching.[4]

Furthermore the MOS technologies could also

be scaled down easily than that of other transistors.
However MOS were quite slower than bipolar transistors
but over the past 30 years MOS has acquired an
unbelievable better speed and now MOS became
comparable to bipolar transistors in term of speed. These
entire features make MOS device way apart the Bipolar
devices [5].
As Carrier mobility is one of the most important
parameters which affects the I-V characteristics of
MOSFETs. So the accurate mobility models which
account for all the important scattering mechanisms are
necessary requirement for predictive MOS device
simulations.[6]
After that the temperature dependence of current
is analysed over a range of
27C to 150C, and a
temperature independent MOSFET-current reference
only is designed with MOSFET particularly for military
applications and in wireless sensor node at hill areas.[7]
A MOSFET-current reference circuit should not
use any diodes and bipolar junction transistors (BJTs).
Processes that are developed recently are mostly
MOSFET processes, for the reason that fabrication of
bipolar transistors is complex and they consume more
power and occupy more area than MOSFETs. The low
cost of fabrication and the possibility of placing both
analog and digital circuits on the same chip so as to
improve the overall performance and reduce the cost of
packaging make MOSFET technology attractive.
Although it is possible to use lateral BJTs in some
MOSFET processes, inclusion of BJTs requires a more
complex and costly fabrication process and also these
lateral BJTs are more sensitive to packaging stress and
process variations. Finally, current reference circuits
using BJTs are generally complex and hence occupy a
large area.[8]
This thesis additionally represents the equivalent
inverter circuit for two-input NAND gate and two-input
NOR gate and therefore finds noise margin and parasitic
estimation for various CMOS logics (Inverter, NAND,
NOR, AND) and also the variation of temperature is
seen on the transfer characteristics for each of them.[9]

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International Journal of Advanced Engineering Research and Technology (IJAERT) 165

Volume 4 Issue 5, May 2016, ISSN No.: 2348 8190

II.

DESIGN OF BASIC CURRENT

REFERENCE CIRCUIT

III. SIMULATION RESULTS

(For design of temperature independent MOSFET)

The basic current reference circuit [10-11] consists of
two parts as can be seen in Figure . The two parts are the
bias generation circuit and the current generation circuit.
The current generation circuit generates a reference
current which varies somewhat with temperature. The
bias generation circuit generates the bias voltage
required to bias the current source transistor in the
current generation circuit. The design of each block is
given in detail. Fig. shows the circuit diagram of the
basic MOSFET-only current reference circuit.

Figure 3 Simulation results for Basic Current Reference

circuit

Figure 1 Basic MOSFET Current-Only reference

Circuits Block diagram

NOISE MARGIN
Noise margin does make sure that any signal which is
logic '1' with finite noise added to it, is still recognized
as logic '1' and not logic '0'. The Noise margin is the
amount of noise that a CMOS circuit could withstand
without compromising the operation of circuit. It is
basically the difference between signal value and the
noise value.[12-13]
Consider the following o/p characteristics of a
CMOS inverter. In ideal condition, when i/p voltage is
logic '0', output voltage is supposed to logic '1'. So VIL
(V input low) is '0'V and VOH (V output high) is 'Vdd' V.

Figure 2. Schematic of Basic Current Reference circuit

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Figure 4. Inverters Transfer characteristic

International Journal of Advanced Engineering Research and Technology (IJAERT) 166

Volume 4 Issue 5, May 2016, ISSN No.: 2348 8190

Schematic CMOS inverter (180 nm)

Schematic of CMOS Inverter equivalent NAND

Figure 5. Temperature variations in Transfer curve of

CMOS inverter
Schematic of CMOS NAND (180 nm)

IV. CONCLUSION
The mobility model discussed for the MOSFET in
BSIM3v3.2.2 is exactly accurate & compact and very
highly adaptive to adverse conditions & different effects.
Trans conductance of the MOS at 180 nm for mobility
model 1 & mobility model 2 of BSIM3v3.2.2 is
comparatively very larger than the same of
BSIM3v3.1.So the mobility model taken in
BSIM3v3.2.2 used to implement more efficient and
accurate trans conductance amplifier circuit.[14-15]
It is also seen that the BSIM3v3.1 is designed only for
mobility model 1 and mobility model 2.
The current model discussed is also very compact and
accurate and the analysis is quite accurate subjected to
different effects (such as DIBL, CLM, SCBE etc.).
The current for BSIM3v3.2.2 is found for three different
modes such as Rds=0, Rds>0 and a generalized model is
also given which include all the different effects viz.
DIBL, CLM, SCBE etc. Hence all these current results
that are calculated for BSIM3v3.2.2 are compared with
that of BSIM3v3.1. And it is observed that the two
current differ each other by a quiet a large gap. It also
leads to the conclusion that some different mathematical
model is used for BSIM3v3.1 current model. After this a
current variation with temperature is also been observed.
As a remedy to this, a temperature independent design
for MOSFET is also discussed. And as a concluding
point, I want to propose this MOSFET-current reference
circuit for the temperature independent MOSFETDesign.
Furthermore the noise margin is estimated for inverter,
NAND & NOR. First of all noise margin estimation is
done for a simple inverter case after that inverter
equivalent technique is analyzed and used for the
converting the NAND and NOR gate into their CMOS
inverter equivalent so as to find Noise margin by

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International Journal of Advanced Engineering Research and Technology (IJAERT) 167

Volume 4 Issue 5, May 2016, ISSN No.: 2348 8190

simulation. A mathematical model for NOISE margin

estimation of an inverter for a simple case is also
presented and these results are compared to that of
simulation results of noise margin for each of the logic
gate.
At the last the parasitic capacitance is estimated for
CMOS inverter, NAND & NOR at 50 degree centigrade
and those are compared to that of CMOS inverter
equivalent NAND and NOR. And it is observed that the
Inverter Equivalent technique is quite compact and fairly
accurate for designing of CMOS equivalent logics.

[14] Lu, Darsen. Compact Models for Future

generation CMOS. Electrical Engineering and
Computer Sciences, University of California at
Berkeley, Spring 2011.
[15] Mansun Chan, et al, "A Relaxation time Approach
to Model the Non-Quasi-Static Transient Effects in
MOSFETs," IEDM, 1994 Technical Digest, pp. 169-172,
Dec. 1994.

REFERENCES
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[4] Department of Electrical Engineering and Computer
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