Contador binario contiene relojlento.vhd, cuenta4.vhd, contador4.

vhd
----------------------------------------------------------------relojlento
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
entity relojlento is
port(
clkl: in std_logic;
led: buffer std_logic:= '0' );
end relojlento;

architecture arqrelojlento of relojlento is

signal conteo: integer range 0 to 25000000;
begin
process(clkl)
begin
if(clkl' event and clkl='1') then
conteo<=conteo+1;
if(conteo=25000000) then
conteo<=0;
led<=not(led);
end if;
end if;
end process;
end arqrelojlento;
-------------------------------------cuenta

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cuenta4 is
Port ( divi : in STD_LOGIC;
reset : in STD_LOGIC;
cyout: out std_logic;
salida : out STD_LOGIC_vector(3 downto 0));
end cuenta4;

architecture arqcuenta4 of cuenta4 is

begin
process (reset, divi)
variable cuenta: std_logic_vector ( 3 downto 0):= "0000";
begin
if rising_edge (divi) then
if cuenta= "1001" then
cuenta:= "0000";
cyout<='1';
else
cuenta:= cuenta+1;

end if;
end if;
IF reset = '1' then
cuenta:= "0000";
end if;
SALIDA <= cuenta;
end process;

end arqcuenta4;
--------------------------------------------contador

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador4 is
Port ( clkl: in STD_LOGIC;
reset : in STD_LOGIC;
cyout: out std_logic;
salida : out STD_LOGIC_vector(3 downto 0));
end contador4;

architecture arqcontador4 of contador4 is

signal conector: std_logic;

begin
u1: entity work.RELOJLENTO(ARQRELOJLENTO) port map(clkl,conector);
u2: entity work.cuenta4(arqcuenta4) port map(conector, reset,cyout, salida);

end arqcontador4;
-----------------------------------bcd7seg
library ieee;
use ieee.std_logic_1164.all;
entity bcd7seg is
port(
bcd: in std_logic_vector(3 downto 0);
led: out std_logic_vector(6 downto 0)
);
end bcd7seg ;
architecture arqbcd7seg of bcd7seg is
begin

--LED <= "0100100";

with bcd select
LED <= "1000000" when "0000",
"1111001" when "0001",
"0100100"when "0010",
"0110000" when "0011",
"0011001" when "0100" ,
"0010010" when "0101" ,

"0000010" when "0110" ,

"1111000" when "0111",
"0000000" when "1000" ,
"0011000" when "1001",
"1111111" when others;

end arqbcd7seg ;
--------------------------------conta7seg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity conta7seg is
Port ( clkl: in STD_LOGIC;
reset : in STD_LOGIC;
cyout: out std_logic;
seg7 : out STD_LOGIC_vector(6 downto 0));
end conta7seg;

architecture arq_conta7seg of conta7seg is

signal conector: std_logic;
signal sal4sal7: std_logic_vector(3 downto 0);
begin
u1: entity work.RELOJLENTO(ARQRELOJLENTO) port map(clkl,conector);

u2: entity work.cuenta4(arqcuenta4) port map(conector, reset,cyout, sal4sal7);

u3: entity work.bcd7seg(arqbcd7seg) port map(sal4sal7, seg7);

end arq_conta7seg;