ELE 3230

Microprocessors and Computer

Systems
Chapter 5
8088 Pin Assignment
(*Brey: ch9; Hall: ch7; Triebel: ch7)
ELE 3230 - Chapter 5

Pin Layout of the 8088

Microprocessor
Min Mode
GND
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

8088
CPU

40 LEAD

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

(Max Mode)

Vcc
A15
A16/S3
A17/S4
A18/S5
A19/S6
SS0
MN/MX

RD
HOLD
HLDA
WR
IO/ M
DT/R

DEN
ALE
INTA
TEST
READY
RESET

Nine pins have functions which depend

on the state of MN/MX :

MN/MX =high - 8088 operates in

MINIMUM MODE
(High)

(RQ / GT0)
(RQ / GT1)
(LOCK )
(S2)
(S1 )
(S0 )
(QS0)
(QS1)

MN/MX =low - 8088 operates in

MAXIMUM MODE
minimum mode: - 8088 directly
generates the control signals necessary
for accessing memory and IO ports.
maximum mode:- external support
chips are used to generate control
signals; the processor can work in a
system containing other processors
2

Signals Common to Both Minimum

and Maximum Modes
Name

Common signals
Function

AD7 AD0

Address/data bus

A15 A8

Address bus

A19/S6
A16/S3

Address/status

Type
Bidirectional,
3-state
Output,
3-state
Output,
3-state

Minimum/maximum
Mode control

Input

Read control

Output,
3-state

Wait on test control

Input

READY

Wait state control

Input

RESET

System reset
Nomaskable
Interrupt request
Interrupt request
System clock
+5V
Ground

Input

MN/MX
RD
TEST

NMI
INTR
CLK
VCC
GND

ELE 3230 - Chapter 5

Input
Input
Input
Input
Input
3

Unique Minimum-mode Signals

Minimum mode signals (MN/MX = VCC )
Name
Function
Type
HOLD
Hold request
Input
HLDA
Hold acknowledge
Output

WR

Write control

Output,
3-state

IO/ M

IO/memory control

DT/ R

Data transmit/receive

Output,
3-state
Output,
3-state

DEN

Data enable

SSO

Status line

Output,
3-state
Output,
3-state

ALE

Address latch enable

Output

INTA

Interrupt acknowledge

Output

ELE 3230 - Chapter 5

Unique Maximum-mode Signals

Maximum mode signals (MN/ MX = GND)
Name
Function
Type
RQ/ GT1, 0 Request/grant bus Bidirectional
access control
Bus priority lock Output,
LOCK
control
3-state
Bus cycle status Output,
S2 - S0
3-state
QS1, QS2 Instruction queue Output
status

ELE 3230 - Chapter 5

Maximum-Mode of 8088
INIT

Multibus

S0
S1
S2
CRQLCK
RESB

CLK
Vcc GND
Interrupt
interface
INTR
TEST
NMI
RESET

SYSB/RESB

ANYREQ
AEN

CLK
LOCK
S0
S1
S2

8088
MPU

MN/MX

BUSY
CBRQ
BPRO
BPRN
BREQ
BCLK

8289
LOCK Bus
arbiter
CLK AEN IOB
IOB

CLK AEN IOB

S0
8288
S1
S2 Bus
DEN controller
DT/R
ALE

MRDC
MWTC
AMWC
IORC
IOWC
AIOWC
INTA
MCE/PDEN
ALE
DT/R
DEN
A0-A15,
A16/S3-A19/S6
D0-D7
RD
READY
QS1,QS0

Local bus control

RQ/GT1 RQ/GT0

ELE 3230 - Chapter 5

Maximum-Mode of 8088
a 8288 Bus Controller
`In maximum-mode, the signal to control memory, I/O, and interrupt
interface is produced by 8288.
` WR, IO/ M, DT/R , DEN, ALE, and INTA are no longer produced by
8088, instead 8288 generates
MRDC -- memory read command
MWTC -- memory write command
AMWC -- advanced memory write command
IORC

-- I/O read command

IOWC

-- I/O write command

AIOWC -- advanced I/O write command

INTA

-- interrupt acknowledge command

ELE 3230 - Chapter 5

Bus Status Codes

a 8288 produces the commands according to the output
bits S 2 S1 S 0 from 8088.
Status Inputs
S2 S1 S0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

CPU Cycle

8288 Command

Interrupt Acknowledge
INTA
Read I/O Port
IORC
Write I/O Port
IOWC, AIOWC
Halt
None
Instruction Fetch
MRDC
Read Memory
MRDC
Write Memory
MWTC, AMWC
Passive
None
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Queue Status Codes

a Two new signals are produced by 8088 in maximum-mode : QS0
and QS1. The two-bit code tells the external circuitry what type of
information was removed from the queue in the previous cycle.
QS1
0 (low)

QS0
Queue Status
0
No Operation. During the last
clock cycle, nothing was taken
from the queue.

First Byte. The byte taken

from the queue was the first
byte of the instruction.

1 (high)

Queue Empty. The queue has

been reinitialized as a result of
the execution of a transfer
instruction.

Subsequent Byte. The byte

taken from the queue was a
subsequent byte of the
instruction.
ELE 3230 - Chapter 5

Pin Diagram

386DX processor view from pin side

ELE 3230 - Chapter 5

Top view for 386SX processor

10

8088 Pin Functions

The 8088 pins may be grouped into the following nine categories:
1. Power Supply and Clock (VCC, GND and CLK)
a VCC=5 volts (5 or 10% tolerance)
a Maximum current needed is 340mA (10 mA for CMOS version)
a BOTH ground (GND) pins must be connected to 0V.
a CLK input needs a periodic rectangular waveform with rise and fall times
of less than 10ns. Clock frequency must be between 2 and 5 MHz. (see
ch06, clock chip 8284).
2. Minimum/Maximum Mode pin
a Minimum mode selected when (MN/MX) is connected to +5V

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8088 Pin Functions

3. Status Pins ( S0, S1, and S2 ) - in maximum mode only
The status pins are outputs which are used by the 8288 bus controller to generate
control signals according to the following table:

S2
0
0
0
0
1
1
1
1

S1
0
0
1
1
0
0
1
1

S0
0
1
0
1
0
1
0
1

Meaning
Interrupt acknowledge (INTA)
I/O read
I/O write
HALT
Code access (fetching instruction)
Memory read
Memory write
Passive state (not used)

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8088 Pin Functions

4. Bus Master (HOLD, HLDA, RQ/GT0, RQ/GT1 and LOCK)
Control of the local bus is transferred to other devices with the aid of the
following signals:
Minimum Mode - HOLD and HLDA (hold acknowledge)
Maximum Mode - request/grant (RQ/ GT0 , RQ/ GT1) and LOCK
a HOLD is an input (in minimum mode only) which tells the processor to
suspend operations and allow other devices to access the system bus.
Program execution only resumes when HOLD=0.
a HLDA (hold acknowledge) is an output which informs other devices in the
system that the 8088 is in a HOLD state. When another device wants to
access the bus, it waits for HLDA=1.

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8088 Pin Functions

4. Bus Master (cont.) (HOLD, HLDA, RQ/GT0, RQ/GT1 and LOCK)
a Request and Grant pins (RQ/ GT0 and RQ/ GT1) are used only in maximum
mode and they function both as inputs (to accept requests) and outputs
(to grant requests). When another device wants to become the BUS
MASTER (i.e. take control of the local bus) it issues a request by pulling
one of the request pins to a low logic state for one clock cycle. After a
request is received, the 8088 enters a HOLD state and sends a grant
signal on the same pin. RQ/ GT0 has a higher priority over RQ/ GT1.
a LOCKis an output pin in maximum mode and informs other devices that
they cannot takeover the local bus

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8088 Pin Functions

5. Interrupt pins (NMI, INTR and INTA)
Interrupt acknowledge pin (INTA ) is available only in minimum mode. NMI
(non-maskable interrupt) and INTR (interrupt request) are present in both
modes.
a The NMI (non-maskable interrupt) is an input which accepts a rising edge
to trigger the interrupt. It cannot be disabled by software. Interrupt number
2 is generated by an NMI.
a INTR is an input which accepts a high logic level as an interrupt request.
Provided the interrupt flag in the FLAGS register is enabled, the processor
will respond to the interrupt request in the same way as it processes an
software INT instruction.
a INTA acknowledges an interrupt request and indicates to the interrupting
device that it should place an 8-bit interrupt number on the data bus

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8088 Pin Functions

6. RESET is an input which resets and initializes the processor. After a
RESET the processor reads memory location FFFF0h for an instruction.
7. Bus control pins
A group of 7 pins generate the control signals for data transfer to and from
the data and address bus in minimum mode. In maximum mode only two
(RD and READY) of these 7 functions are available directly (the other bus
protocol signals are generated from the status pins).
The seven pins in this group include:
a READY - an input to tell the processor that the selected memory or I/O
port is ready to complete a read or write operation. If READY is not
asserted, wait states are added (eg. For slow memory).

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8088 Pin Functions

7. Bus control pins (cont.)
a RD(read) - an output indicating when the processor is performing read
operation from memory or an I/O port.
a ALE (addressing latch enable) - an output to demultiplex the address/data
pins. When ALE is high, address information is being sent.
a DEN (data enable) - an output used with an external tristate buffer to disconnect
the processor data pins from the data bus. (When DEN is low the processor
data pins should be connected to the data bus)
a DT/R (data transmit/receive) - an output indicates direction of data flow
a WR(write) - an output to indicate when the processor is putting data into
memory or I/O port
a IO/M - an output indicates whether access is to memory or I/O ports
a The logic is different between 8086 & 8088.

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8088 Pin Functions

8. Address, data pins and address status pins
a AD0-AD7 (address/data bus pins) - these pins output both address and data
information and input data at different times of the bus cycle. Usually an
external latch stores the address information form these pins before the pins
are switched to carry data. Both the low and high order bytes of a 16-bit data
word must be transferred via these pins.
a A8-A15 (address bus pins) - used solely for specifying the address of a
memory location or IO port.
a A16/S3-A19/S6 (address bus or status pins) - these either carry memory
addressing information or status information. S6 is always at logic 0. S5
describes the state of the interrupt flag in the FLAGS register. S4 and S3
describe the segment register being used to generate the physical address
that was output on the address during the current bus cycle.
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8088 Pin Functions

8. Address, data pins and address status pins (cont.)
S4
0
0
1
1

S3
0
1
0
1

Segment register
ES
SS
CS or no segment
DS

a The address pins A0-A15 specify either a 16-bit I/O port number or the
first 16 bits of a 20-bit address of a memory location.

9. Coprocessor interaction pins

Three pins (TEST, QS0 and QS1) are used for interactions between the
8088 and 8087 arithmetic co-processor to synchronize MPU with
external hardware.
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8088 Pin Functions

9. Coprocessor interaction pins (cont.)
a TEST is an input pin that is tested by the WAIT instruction. If TEST is low the
WAIT instruction functions as a NOP. If TEST is at logic 1 then the WAIT
instruction waits until it goes to logic 0 (MPU enters idel state). The TEST pin
is often connected directly to a 8087 coprocessor (it must be connect to logic 0
if the 8087 is not present)
a QS0 and QS1 (queue status) pins provide information on the 8088 internal
instruction queue. The information is used by the 8087 coprocessor. The
queue status bits indicate the contents of the internal instruction queue
according to the following table:
QS1 QS0 instruction queue contents
0
0 No operation (queue is idle)
0
1 First byte of an opcode
1
0 Queue is empty
1
1 Subsequent byte of an opcode
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DC characteristics of Pin
a It is important to know the input and output characteristics
which are required for hardware designer to select proper
components.
a Input characteristics:
Output characteristics:
Logic Level

Voltage

Current

Logic Level

Voltage

Current

0.8 V max

10A max

0.45 V max

2.0mA max

2.0 V min

10A max

2.4 V min

-400A max

Logic 1

Logic 1
VIH(min)

Undetermined
Range
Input voltage
range

VOH(min)

VIL(max)

Logic 0

Disallowed
Range
VOL(max)

Logic 0
ELE 3230 - Chapter 5

Output voltage
range
21

DC characteristics of Pin
a Noise immunity :
VNL [Low-level (Logic 0) noise immunity] = Vin_low (max)- Vout_low(max)
VNH [High-level (Logic 1) noise immunity] = Vout_high(min)-Vin_high(min)

a For 8088, VNL is 350mV (=0.8V-0.45V). Typical logic circuit has noise
immunity 400mV (=0.8V-0.4V).
a Smaller noise immunity means 8088 and 8086 would encounter problem
with longer wire or larger load.
recommendation : no more than 10 loads
Family
Fanout Sink Current
Source Current
a recommended fan out:
TTL (74XX)

-1.6 mA

40 A

TTL (74LSXX)

-0.4 mA

20 A

TTL (74SXX)

-2.0 mA

50 A

TTL (74ALSXX)

10

-0.2 mA

20 A

CMOS (74HCXX)

10

-1.0 A

1.0 A

CMOS (CD4XXX)

10

-1.0 A

1.0 A

10

-10 A

10 A

NMOS

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