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SEQUENTIAL NETWORKS
CANONICAL FORM OF SEQUENTIAL NETWORKS
LATCHES AND EDGE-TRIGGERED CELLS. D FLIP-FLOP
TIMING CHARACTERISTICS
ANALYSIS AND DESIGN OF CANONICAL NETWORKS
SR, JK and T FLIP-FLOP
ANALYSIS OF FLIP-FLOP NETWORKS
DESIGN OF FLIP-FLOP NETWORKS. EXCITATION FUNCTIONS

SPECIAL STATE ASSIGNMENTS: ONE-FLIP-FLOP-PER-STATE AND SHIFTING REGISTER

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CANONICAL FORM OF SEQUENTIAL NETWORKS (Huffman-Moore)

present
input
x(t)

initialize

next
state

State Register

Combinational
Network

State-transition function s(t + 1) = G(s(t), x(t))


Output function
z(t) = H(s(t), x(t))

s(t+1)

present
state

s(t)

Ideal clock pulse

CLK

z(t)
(a)

Ideal
clock

present
output

PRESENT
STATE
s(t)

NEXT
STATE
s(t+1)

t
0

(b)

Figure 8.1: a) CANONICAL IMPLEMENTATION OF SEQUENTIAL NETWORK. b) IDEAL CLOCK SIGNAL AND ITS INTERPRETATION.

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s(t+1)
C1
x(t)

State Register

MEALY AND MOORE MACHINES

z(t)

s(t)
C2

CLK

s(t+1)
C1
x(t)

State Register

(a)

z(t)
C2
s(t)

CLK
(b)
Figure 8.2: CANONICAL IMPLEMENTATIONS: a) MEALY MACHINE. b) MOORE MACHINE.

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Combinational Network

HIGH-LEVEL AND BINARY IMPLEMENTATIONS

x0

Inputs
x m-1

Initialize
z0
Outputs

Y0

Y1

Y k-1

z n-1

0
1

State Register
(binary cells)
k-1

Next state
Present state

CLK

Figure 8.3: CANONICAL IMPLEMENTATION WITH BINARY VARIABLES.

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EXAMPLE 8.1

Input:
Output:
State:
Initial state:

x(t) = (x1, x0), xi {0, 1}


z(t) {0, 1}
y(t) = (y3, y2, y1, y0), yi(t) {0, 1}
y(0) = (0, 0, 0, 0)

Function:

The transition and output functions


Y3
Y2
Y1
Y0
z

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=
=
=
=
=

y2x01x0
(y1 y2)x00 y3x1
(y0 y3)x01x0 (y0 y1)x1
(y0 y3)x00y1x01x0 y2x1
y 3 y2 y1 y0

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EXAMPLE 8.1 (cont.)

Combinational
Network

x0
x1

Initialize
Y0

Y1
Y2
Y3

y
1
y
2
y

CLK
Figure 8.4: CANONICAL NETWORK FOR EXAMPLE 8.1.

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CLOCK
clock period T
clock frequency f = 1/T
(clock) pulse width tw
CLK
t

Clock pulse width


Clock period T
time

Figure 8.5: PULSE WIDTH AND CLOCK PERIOD.

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GATED LATCH - FIRST TRY

D
Q
E

(a)
E

tp
(b)

Figure 8.6: a) GATED-LATCH. b) TIMING BEHAVIOR.

Q(t + tp) = D(t) E(t) Q(t) E 0(t)


LEVEL-SENSITIVE: when E = 1 then Q = D
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nor-nor LATCH

D
(Input)

E
(Enable)

Q
a

(Output)
(a)

E
D
a
b
c
d

+
loop

loop
*

Q
* c kept in 0 even when b=0 + Q kept in 0 even when d=0
(b)

Figure 8.7: a) IMPLEMENTATION OF GATED-LATCH WITH nor GATES. b) TIMING DIAGRAM.

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LATCH WITH TRANSMISSION GATES


TG1
c

D
(Input)

(Output)
e

E
(Enable)

TG2

(a)
E
a
b
on

TG1
TG2

on

off

off

D
c
d

loop

loop

(b)

Figure 8.8: a) IMPLEMENTATION OF GATED-LATCH WITH TRANSMISSION GATES. b) TIMING DIAGRAM.

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LIMITATIONS OF GATED-LATCH

CLK

x
t

XOR

XOR

D
y
Q
CLK

(a)

(b)

z
CLK

x
t

Y t XOR

t
XOR

XOR

(c)

Figure 8.9: a) SEQUENTIAL NETWORK. b) CORRECT TIMING BEHAVIOR. c) INCORRECT TIMING BEHAVIOR.

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A SOLUTION: EDGE-TRIGGERED CELL

Input

Input

12

Output

Output

CLK

CLK
(a)

(b)

Triggering edge

Triggering edge

CLK

CLK

x
tp

tp
y

(c)

(d)

Figure 8.10: EDGE-TRIGGERED CELL: a) LEADING-EDGE-TRIGGERED CELL. b) TRAILING-EDGE-TRIGGERED CELL. c)


LEADING-EDGE-TRIGGERED CELL IN NETWORK OF Figure 8.9. d) TRAILING-EDGE-TRIGGERED CELL IN NETWORK OF
Figure 8.9.

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IMPLEMENTATION: MASTER-SLAVE CELL

CLK

Input

CLK

Master
cell

Output

CLKSlave
E

cell

CLK
(a)
S
t

W latched

S latched

(b)

Figure 8.11: a) MASTER-SLAVE IMPLEMENTATION OF TRAILING-EDGE-TRIGGERED CELL. b) MASTER-SLAVE STATE


CHANGE PROCESS.

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PRACTICAL BASIC CELL: D flip-flop

PR (preset)

D Q

INPUT D(t)

Q(t)
OUTPUTS

CLK

Q=0

Q(t) (optional)

Q=1

CLR (clear)
Figure 8.12: D FLIP-FLOP AND ITS STATE DIAGRAM.

P S = Q(t)
0
1

0
0
0
NS

D(t)
1
1
1
= Q(t + 1)

Q(t + 1) = D(t)

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TIMING PARAMETERS OF A BINARY CELL

tw

CLK
set-up time
Input

t su

th

hold time

D
Q

State

Input

CLK

State

tp

propagation delay

Figure 8.13: TIME BEHAVIOR OF CELL.

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CHARACTERISTICS OF A cmos D flip-flop

Delays

Input Size
factor
tpLH
tpHL
tsu th tw [std. [equiv.
[ns]
[ns]
[ns] [ns] [ns] loads] gates]
0.49 + 0.038L 0.54 + 0.019L 0.30 0.14 0.2
1
6
L: output load of the flip-flop
THIS FLIP-FLOP HAS ONLY THE UNCOMPLEMENTED OUTPUT

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TIMING CHARACTERISTICS OF SEQUENTIAL NETWORKS

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NETWORK SET-UP TIME: txsu(net) = d1x + tsu(cell)


t*
CLK

State Register

delay d1

C1

x
delay d1

z
C2
y

(a)

t su (cell)

Cell input
delay d2

CLK

Network input x

Cell setup
time

C1 delay d1x
(b)

t su (net)

Network
setup time

Figure 8.14: TIMING FACTORS IN SEQUENTIAL NETWORKS: a) THE NETWORK. b) NETWORK SET-UP TIME.

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TIMING FACTORS (cont.)

NETWORK HOLD TIME: th(net) = th(cell)

State Register

delay d1

CLK

C1

x
delay d1

z
C2

Network input x
d1 x

delay d2

Cell input

CLK

(a)

t h (cell)
(c)

Cell hold time

t h (net) Network hold time

Figure 8.14: TIMING FACTORS IN SEQUENTIAL NETWORKS: a) THE NETWORK. c) NETWORK HOLD TIME.

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TIMING FACTORS (Cont.)

NETWORK PROPAGATION DELAY: tp(net) = tp(cell) + d2


CLK

C1

State Register

delay d1 y

delay d1 x

z
C2
y

d2

delay d2
CLK

Network output z
(d)

(a)

t (cell)
p

Cell output

p (net)

Figure 8.14: TIMING FACTORS IN SEQUENTIAL NETWORKS: a) THE NETWORK. d) NETWORK PROPAGATION DELAY.

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MAXIMUM CLOCK FREQUENCY

System S

t in = t p (A)
t

su (cell)

System A

C1

Y
z
t + d2
p

State Register

delay d1y

CLK

delay d1x

tout = tsu (B)

z
C2

System B

delay d2

(a)
CLK

CLK

CLK

(b)

Figure 8.15: MAXIMUM CLOCK FREQUENCY: a) CLOCK PERIOD AND SIGNAL DELAYS. b) THE NETWORK.

tin - TIME BETWEEN TRIGGERING EDGE OF CLOCK AND STABILIZATION OF INPUT x


tout - TIME BETWEEN STABILIZATION OF OUTPUT z AND NEXT CLOCK
TRIGGERING EDGE

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System S

Y
System A

C1

State Register

y
delay d1

z
C2
y

x
delay d1

CLK

System B

delay d2

CLK

CLK

(b)
CLK
x

d1

With respect to
network input x
With respect to
state register output y
With respect to
network output z

tp

d1

su

t in = t p (System A)

su

tout = tsu (System B)


tp

d2

Minimum clock period


(c)
Figure 8.15: MAXIMUM CLOCK FREQUENCY: b) THE NETWORK. c) MINIMUM CLOCK PERIOD.
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MAXIMUM CLOCK FREQUENCY (cont.)

Tmin = 1/fmax
Tmin = max[(tin + txsu(net)), (tp(cell) + tysu(net)), (tp(net) + tout)]
th(cell) tp(cell)
Tmin = max[(tin+d1x+tsu(cell)), (tp(cell)+d1y +tsu(cell)), (tp(cell)+d2+tout)]

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23

EXAMPLE 8.3
DETERMINE THE MAXIMUM CLOCK FREQUENCY
d1x = d1y = 2.5ns
d2 = 3ns
tsu = 0.3ns
tp = 1ns
tin = 2ns
tout = 3ns
THE MINIMUM CLOCK PERIOD
Tmin = max[(2 + 2.5 + 0.3), (1 + 2.5 + 0.3), (1 + 3 + 3)] = 7[ns]
THE MAXIMUM FREQUENCY
fmax =

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1
140(MHz)
9
7 10

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CLOCK SKEW

CLK

x
Q1

CLK

D Q

Q2

Q1

(a)

FF1
CLK

delay
CLK*

Q2
D Q
FF2

x
Q1
CLK*

Q2
clock skew
(b)
Figure 8.16: a) NETWORK BEHAVIOR WITHOUT CLOCK SKEW. b) NETWORK BEHAVIOR WITH INADMISSIBLE CLOCK
SKEW.

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ANALYSIS OF CANONICAL SEQUENTIAL NETWORKS

25

1. ANALYZE COMBINATIONAL NETWORK


DETERMINE THE TRANSITION AND OUTPUT FUNCTIONS
2. DETERMINE HIGH-LEVEL SPECIFICATION OF STATE DESCRIPTION
OUTPUT FUNCTIONS.
3. IF DESIRED (OR REQUIRED), DETERMINE TIME BEHAVIOR

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EXAMPLE 8.4: ANALYSIS

Y0

y 1
y 0

y 1
y1
y1
y 1

D Q

y0 = z1

FF0

y 0

D Q

y1

y 0
y 0

Y1

y0
FF1
y0

y 1 = z0

CLK
Figure 8.17: SEQUENTIAL NETWORK IN Example 8.4.

State transition

Y0 = x0y10 xy00
Y1 = xy00 y10 x0y00 y1 xy0y1 x0y0y10

Output

z0 = y10
z1 = y0

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EXAMPLE 8.4 (cont.)


STATE-TRANSITION AND OUTPUT FUNCTIONS:
PS
Input
y1 y0 x = 0 x = 1
00
01
11
01
01
11
00
11
10
01
00
10
11
00
10
10
Y1 Y0
z1 z0
NS
Output
CODES:
x x
0 a
1 b

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z 1 z0
00
01
10
11

z
c
d
e
f

y 1 y0
00
01
10
11

s
S0
S1
S2
S3
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EXAMPLE 8.4 (cont.)


HIGH-LEVEL SPECIFICATION:
Input:
Output:
State:
Initial state:

x(t) {a, b}
z(t) {c, d, e, f }
s(t) {S0, S1, S2, S3}
s(0) = S2

Functions:

The state-transition and output functions


P S x(t) = a x(t) = b
S0
S1
S3
d
S3
S0
f
S1
S2
S2
S1
c
S3
S0
S2
e
NS
z(t)

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29

a
S0 /d
b
a

S2 /c

S1 /f
a
b

S3 /e

Figure 8.18: a) STATE DIAGRAM FOR SEQUENTIAL NETWORK.

x(t) a a b a b b a b a a b b b a
s(t) S2 S2 S2 S1 S3 S2 S1 S3 S2 S2 S2 S1 S0 S3 S0
z(t) c c c f e c f e c c c f d e d
Figure 8.18: b) A sequence of input-output pairs.

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PROPAGATION DELAY x to z0:


INPUT LOAD FACTORS:
Ix = 4
SET-UP TIME:
tsu(net) = tpHL(not) + tpHL(and3)
+tpHL(or4) + tsu
= (0.05 + 0.017 3) + (0.18 + 0.018)
+(0.45 + 0.025) + 0.3
= 1.07 [ns]
HOLD TIME:
th(net) = 0.14 [ns]
PROPAGATION DELAY:
tp(z0) = tpLH (ff) + tpHL(not)
= (0.49 + 0.038 3)
+(0.05 + 0.017 (L + 3))
= 0.70 + 0.017L [ns]
(load of not is L + 3, load of FF is 3)
SIZE:
= 62+2+3+26+31
= 32 equivalent gates.

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DESIGN OF CANONICAL SEQUENTIAL NETWORKS

31

1. TRANSFORM THE TRANSITION AND OUTPUT FUNCTIONS


2. SPECIFY A STATE REGISTER TO ENCODE THE REQUIRED NUMBER
OF STATES
3. DESIGN THE REQUIRED COMBINATIONAL NETWORK

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EXAMPLE 8.5: DESIGN


Input:
Output:
State:
Initial state:

x(t) {a, b, c}
z(t) {0, 1}
s(t) {A, B, C, D}
s(0) = A

Functions:

The state-transition and output functions


PS
A
B
C
D

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Input
x=a x=b
C,0 B,1
D,0 B,0
A,0 D,1
B,0 A,0
N S, z

x=c
B,0
A,1
D,0
D,1

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EXAMPLE 8.5 (cont.)

33

CODING:
Input code
x x 1 x0
a 0 1
b 1 0
c 1 1

Introduction to Digital Systems

State code
s y 1 y0
A 0 0
B 1 0
C 0 1
D 1 1

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EXAMPLE 8.5 (cont.)


STATE-TRANSITION AND OUTPUT FUNCTIONS
PS
x 1 x0
y1y0 01 10 11
00 01,0 10,1 10,0
10 11,0 10,0 00,1
01 00,0 11,1 11,0
11 10,0 00,0 11,1
Y1 Y0 , z
N S, Output
x0
x0
Y1 :
Y0 :
- 011
- 100
- 0 1 1 y0
- 0 1 1 y0
y1 - 1 1 0
y1 - 0 1 0
- 101
- 100
x1
x1

z:

y1 -

x0
001
0 0 1 y0
010
010
x1

Y1 = y10 x1 y1x01 + y00 x00 y0x1x0


Y0 = y00 x01 y10 y0x1 y0x1x0
z = y10 x00 y1x1x0
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EXAMPLE 8.5 (cont.)

D Q

FF1

D Q

FF0

y
1
x

0
0

CLK

Figure 8.19: SEQUENTIAL NETWORK IN Example 8.5.

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SR FLIP-FLOP

PR (preset)

10

Q(t)
0-

CLK

R Q

Q=0

Q(t) (optional)

Q=1

-0

01

CLR (clear)
Figure 8.20: SR FLIP-FLOP AND ITS STATE DIAGRAM.

P S = Q(t)
0
1

S(t)R(t)
00 01 10 11
0 0 1
1 0 1
N S = Q(t + 1)

Q(t + 1) = Q(t)R0(t) S(t) restriction: R(t) S(t) = 0

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JK FLIP-FLOP

PR (preset)

1-

Q(t)
0-

CLK

K Q

Q=0

Q(t) (optional)

Q=1

-0

-1

CLR (clear)
Figure 8.21: JK FLIP-FLOP AND ITS STATE DIAGRAM.

P S = Q(t)
0
1

J(t)K(t)
00 01 10 11
0 0 1 1
1 0 1 0
N S = Q(t + 1)

Q(t + 1) = Q(t)K 0(t) Q0(t)J(t)

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T (Toggle) FLIP-FLOP

PR (preset)

Q(t)
0

CLK

Q=0

Q(t) (optional)

Q=1

CLR (clear)
Figure 8.22: T FLIP-FLOP AND ITS STATE DIAGRAM.

P S = Q(t)

T (t)

0
1

0
1
0
1
1
0
N S = Q(t + 1)

Q(t + 1) = Q(t) T (t)

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IMPLEMENTING ONE FF TYPE WITH ANOTHER

CLK

39

Q(t)

Figure 8.23: T FLIP-FLOP IMPLEMENTED WITH JK FLIP-FLOP.

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ANALYSIS OF NETWORKS WITH FLIP-FLOPS

1. OBTAIN THE TRANSITION FUNCTION OF THE NETWORK


(a) DETERMINE THE INPUTS TO THE FLIP-FLOPS
(b) USE THE TRANSITION FUNCTION OF THE FLIP-FLOPS TO DETERMINE THE NEXT STATE

2. OBTAIN THE OUTPUT FUNCTION


3. DETERMINE A SUITABLE HIGH-LEVEL SPECIFICATION

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CHARACTERISTICS OF A FAMILY OF cmos FLIP-FLOPS

FF
type

41

Input Size
factor
tpLH
tpHL
tsu th
tw [std. [equiv.
[ns]
[ns]
[ns] [ns] [ns] loads] gates]
D 0.49 + 0.038L 0.54 + 0.019L 0.30 0.14 0.20
1
6
JK 0.45 + 0.038L 0.47 + 0.022L 0.41 0.23 0.20
1
8
L: output load of the flip-flop
These flip-flops have only uncomplemented outputs

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Delays

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EXAMPLE 8.6: ANALYSIS

x1

Q
A
Q

x0

B Q
Q B

CLK

x1
Figure 8.24: SEQUENTIAL NETWORK FOR Example 8.6.

TA = x1QB QA(t + 1) = QA(t) x1QB (t)


TB = x0QA QB (t + 1) = QB (t) x0QA(t)
z(t) = x1(t)Q0B (t)
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EXAMPLE 8.6 (cont.)


STATE-TRANSITION AND OUTPUT FUNCTIONS
PS
QA QB
00
01
10
11

00
00
01
10
11

Input
x1 x0
01 10
00 00
01 11
11 10
10 01
QA QB
NS

11
00
11
11
00

00
0
0
0
0

x1 x0
01 10
0 1
0 0
0 1
0 0
z
Output

11
1
0
1
0

CODING:
QA QB
0 0
0 1
1 0
1 1

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s
S0
S1
S2
S3

x1
0
0
1
1

x0
0
1
0
1

x
a
b
c
d

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EXAMPLE 8.6 (cont.)

HIGH-LEVEL DESCRIPTION:
Input:
Output:
State:
Initial state:

x(t) {a, b, c, d}
z(t) {0, 1}
s(t) {S0, S1, S2, S3}
s(0) = S0

Functions:

The state-transition and output functions


PS
S0
S1
S2
S3

Introduction to Digital Systems

x
a
S0
S1
S2
S3

b c
S0 S0
S1 S3
S3 S2
S2 S1
NS

x
d
S0
S3
S3
S0

a
0
0
0
0

b
0
0
0
0

c
1
0
1
0

d
1
0
1
0

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EXAMPLE 8.7: ANALYSIS

A
Q

K
Q

CLK
Q

B
K

A
Figure 8.25: SEQUENTIAL NETWORK FOR Example 8.7

JA = x0Q0B
JB = Q A

xQA

KA = Q B
KB = x0Q0A

z = QA Q0B

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EXAMPLE 8.7 (cont.)


JA = x0Q0B
JB = Q A

xQA

46

KA = Q B
KB = x0Q0A

z = QA Q0B
QA(t + 1) = QAKA0 + Q0AJA
= QAQ0B + Q0A(x0Q0B + xQA)
= Q0B (QA + x0)
QB (t + 1) = QB KB0 + Q0B JB
= QB (x + QA) + Q0B QA
= QB x + QA

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EXAMPLE 8.7 (cont.)

47

STATE-TRANSITION AND OUTPUT FUNCTIONS


PS
QA QB
00
01
10
11

NS
Output
x=0 x=1
z
QA QB QA QB
10
00
1
00
01
0
11
11
1
01
01
1

STATE CODING
QA QB
0 0
0 1
1 0
1 1

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S
S0
S1
S2
S3

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EXAMPLE 8.7 (cont.)


HIGH-LEVEL DESCRIPTION
Input:
Output:
State:
Initial state:

x(t) {0, 1}
z(t) {0, 1}
s(t) {S0, S1, S2, S3}
s(0) = S0

Functions:

The state-transition and output functions


PS
S0
S1
S2
S3

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Input
x=0 x=1
S2
S0
S0
S1
S3
S3
S1
S1
NS

1
0
1
1
z

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EXAMPLE 8.7 (cont.)

1
0
1

S1 /0

S0 /1

0,1
S2 /1

S3 /1

0,1
Figure 8.26: STATE DIAGRAM IN Example 8.7.

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OTHER CHARACTERISTICS (Example 8.6)

INPUT LOAD FACTOR:


SET-UP TIME:

HOLD TIME:

Ix = 2
tsu(net) = tpLH (not) + tpLH (and) + tpLH (or)
+tsu(F F )
= (0.02 + 0.038 2) + (0.15 + 0.037)
+(0.12 + 0.037) + 0.41
= 0.86 [ns]
th(net) = 0.23 [ns]

PROPAGATION DELAY: tp(net) = tpHL(ff) + tpLH (not) + tpLH (or)


= (0.47 + 0.022 2) + (0.02 + 0.038 2)
+(0.12 + 0.037L)
= 0.73 + 0.037L [ns]
SIZE:

Introduction to Digital Systems

= 3+25+82
= 29 equivalent gates
8 Sequential Networks

DESIGN OF SEQUENTIAL FLIP-FLOP NETWORKS

51

EXCITATION FUNCTION E(Q(t), Q(t + 1))

from
Q(t) = 0
Q(t) = 0
Q(t) = 1
Q(t) = 1

Introduction to Digital Systems

to
Q(t + 1) = 0
Q(t + 1) = 1
Q(t + 1) = 0
Q(t + 1) = 1

inputs should be
S(t) = 0, R(t) = dc
S(t) = 1, R(t) = 0
S(t) = 0, R(t) = 1
S(t) = dc, R(t) = 0

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52

EXCITATION FUNCTIONS
D flip-flop
PS
0
1

0
0
0

SR flip-flop

NS

PS

1
1
1
D(t)

0
1

NS
0
1
0- 10
01 -0
S(t)R(t)

D(t) = Q(t + 1)
JK flip-flop
PS

NS

0
1

0
1
01-1
-0
J(t)K(t)

T flip-flop
PS
0
1

NS
0
0
1

1
1
0
T (t)

T (t) = Q(t) Q(t + 1)


Introduction to Digital Systems

8 Sequential Networks

THE DESIGN PROCEDURE

53

1. OBTAIN A BINARY DESCRIPTION OF THE SYSTEM


2. SELECT THE TYPE OF FLIP-FLOP
3. DETERMINE THE INPUTS TO THE FLIP-FLOPS (use the excitation function)
4. DESIGN A COMBINATIONAL NETWORK

Introduction to Digital Systems

8 Sequential Networks

EXAMPLE 8.8: DESIGN MODULO-5 COUNTER

54

USE T FLIP-FLOPS
Input:
Output:
State:
Initial state:

x(t) {0, 1}
z(t) {0, 1, 2, 3, 4}
s(t) {S0, S1, S2, S3, S4}
s(0) = S0

Functions:

Counts modulo-5, i.e.,


(0,1,2,3,4,0,1,2,3,4,0...),

x=0
S0 /0

0
x=1

S1 /1

S2 /2

0
1

S3 /3

S4 /4

Figure 8.27: STATE DIAGRAM FOR Example 8.8.

Introduction to Digital Systems

8 Sequential Networks

EXAMPLE 8.8 (cont.)


z
0
1
2
3
4

z2
0
0
0
0
1

z1
0
0
1
1
0

55

z0
0
1
0
1
0

PS
Input
Input
Q2 Q1 Q0 x = 0 x = 1 x = 0 x = 1
000
000 001 000 001
001
001 010 000 011
010 011 000 001
010
011
011 100 000 111
100
100 000 000 100
NS
T 2 T1 T0
DONT CARES: 5, 6, AND 7

Introduction to Digital Systems

8 Sequential Networks

56

EXAMPLE 8.8 (cont.)

sm STATE MAP
sm:

0
2
Q2 6
4

x
011
2 3 3Q
677 1
455
Q0

T2 :

0
0
Q2 0

x
000
0 1 0Q
- - - 1
1 - Q0

T1 :

0
0
Q2 0

x
010
0 1 0Q
- - - 1
0 - Q0

T0 :

0
0
Q2 0

x
110
1 1 0Q
- - - 1
0 - Q0

T2 = xQ2 xQ1Q0
T1 = xQ0
T0 = xQ02

Introduction to Digital Systems

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57

FF2

1 Q
0

z2

Q
T

z1

FF1

Q
T

z0

FF0

Q
CLK
Figure 8.28: SEQUENTIAL NETWORK IN Example 8.8.

Introduction to Digital Systems

8 Sequential Networks

EXAMPLE 8.9: DESIGN


Input:
Output:
State:
Initial state:

x(t) = (x1, x0), xi {0, 1}


z(t) {0, 1}
s(t) {a, b, c, d}
s(0) = a

Functions:

The transition and output functions


PS
a
b
c
d

Introduction to Digital Systems

58

x 1 x0
01 10 11
b,0 c,1 c,0
a,0 d,1 d,0
d,0 c,0 a,1
c,0 a,0 d,1
N S, z

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59

EXAMPLE 8.9 (CONT.)

State Q1Q0
a
00
b
01
10
c
d
11
S1 :

Q1 --

S0 :

Q1 --

Introduction to Digital Systems

PS
Q1 Q0
00
01
10
11
x0
011
0 1 1Q
- - 0 0
- 0 x0x1
100
0 - -Q
0 - 0 0
100
x1

x 1 x0
01 10 11
01 10 10
00 11 11
11 10 00
10 00 11
NS

Q(t) Q(t + 1)
0
0
0
1
1
0
1
1
R1 :

Q1 --

R0 :

Q1 --

S
0
1
0
-

R
0
1
0

x0
- 00
- 0 0Q
001 0
010
x0x1
0 - 1 0 0Q
101 0
0 - x1

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60

S1
R1
S0
R0

=
=
=
=

x1Q01
x00Q1Q0 x1x0Q1Q00
x01Q00
x01Q0 x00Q1
z:

Q1 --

x0
001
0 0 1Q
010 0
010
x1

THE OUTPUT EXPRESSION IS


z = x00Q01 x1x0Q1

Introduction to Digital Systems

8 Sequential Networks

61

EXAMPLE 8.9 (cont.)

x0

1
Q

S1

1 Q
0

x0 x1

FF1

S
R

CLK

x1
Q

x1

S0

FF0
R

x0

x0
Q

x 11

Figure 8.29: SEQUENTIAL NETWORK IN Example 8.9.

Introduction to Digital Systems

8 Sequential Networks

62

SPECIAL STATE ASSIGNMENTS


ONE FLIP-FLOP PER STATE
start
start
"Wait" state

D Q

S0

S0
Q

start
D Q

S1

S1
Q

D Q

S2

Initially, S 0 is set to 1 and


all other flip-flops to 0
(preset and clear signals
not shown)

S2
Q

D Q

S3

S3

D Q

S4

S4
CLK

(a)

(b)

Figure 8.30: ONE FLIP-FLOP PER STATE APPROACH: a) STATE DIAGRAM. b) IMPLEMENTATION (Outputs omitted).

Introduction to Digital Systems

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63

PRIMITIVES FOR one-flip-flop-per-state APPROACH

Predecessor States

Predecessor States
D

Si

Si

Si
D

Sj

Si

Determined by
inputs

CLK

inputs

Sj
CLK
(a)

Successor States
(a)

(b)

Successor States
(b)

Figure 8.31: PRIMITIVES FOR THE ONE-FLIP-FLOP-PER-STATE APPROACH.

Introduction to Digital Systems

8 Sequential Networks

64

CONTROLLER FOR SIMPLE VENDING MACHINE

coin . return

return

coin . return

coin

Note: coin . return = 0

D Q

"Wait" state

S0

S 5 /return_all_coins, clear_sum

CLK

S0
Q

D Q

coin . return

CLK

S 2 /release_candy, clear_sum
change_available
sum=75
sum=75

S1

change_available

sum>75
S3

S4

return_change

D Q
CLK

S1

Initially, S 0 is set to 1 and


all other flip-flops to 0
(preset and clear signals
not shown)

D Q

Q
CLK

(a)

release_candy,
clear_sum
Q

S2

D Q
CLK

sum>75

return_all_coins
clear_sum

D Q
CLK

S 4 /return_change

sum<75

S5

sum<75

S3
Q

change_available
(b)

Figure 8.32: A ONE-FLIP-FLOP-PER-STATE IMPLEMENTATION OF A CONTROLLER FOR VENDING MACHINE: a) STATE


DIAGRAM. b) IMPLEMENTATION.

Introduction to Digital Systems

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65

SHIFTING STATE REGISTER: Example 8.10

Input:
Output:

x(t) {0, 1}
z(t) {0, 1}

Function: z(t) =

1 if x(t 3, t) = 1101
0 otherwise

CLK
x(t-1)
x(t)

x(t-2)

x(t-3)

D Q

D Q

D Q

Q
z(t)

Figure 8.33: IMPLEMENTATION OF PATTERN RECOGNIZER IN EXAMPLE 8.10.

Introduction to Digital Systems

8 Sequential Networks