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CD4520BMS
CMOS Dual Up Counters
December 1992
Features
Pinout
CD4518BMS, CD4520BMS
TOP VIEW
CLOCK A
16 VDD
ENABLE A
15 RESET B
Q1A
14 Q4B
Q2A
13 Q3B
Q3A
12 Q2B
Q4A
11 Q1B
RESET A
10 ENABLE B
VSS
9 CLOCK B
Functional Diagram
Applications
3
CLOCK A
1
ENABLE A
2
Frequency Dividers
10/16
C
5
6
Description
Q1A
Q2A
Q3A
Q4A
RESET A
7
11
CLOCK B
9
ENABLE B
10
10/16
C
Q1B
12
13
14
Q2B
Q3B
Q4B
RESET B
15
VSS = 8
VDD = 16
H4S
H1F
*H6P H6W
CD4520B Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
7-1206
File Number
3342
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
IIL
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VDD = 20
VDD = 18V
Output Voltage
Output Voltage
VOL15
VOH15
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
+25oC
10
+125oC
1000
-55oC
10
+25oC
-100
nA
+125oC
-1000
nA
-55oC
-100
nA
+25oC
100
nA
+125oC
1000
nA
-55oC
100
nA
1, 2, 3
+25oC,
+125oC,
-55oC
50
mV
1, 2, 3
+25oC,
+125oC,
-55oC
14.95
IOL5
+25oC
0.53
mA
IOL10
+25oC
1.4
mA
+25oC
3.5
mA
+25oC
-0.53
mA
IOL15
IOH5A
IOH5B
+25oC
-1.8
mA
IOH10
+25oC
-1.4
mA
+25oC
-3.5
mA
+25oC
-2.8
-0.7
+25oC
0.7
2.8
+25oC
+25oC
8A
+125oC
8B
-55oC
IOH15
VNTH
VPTH
F
VIL
1, 2, 3
1.5
VIH
1, 2, 3
3.5
VIL
1, 2, 3
VIH
1, 2, 3
11
7-1207
PARAMETER
Propagation Delay
Clock to Output
Propagation Delay
Reset to Ouput
Transition Time
(Note 2)
Maximum Clock Input
Frequency
SYMBOL
TPHL1
TPLH1
TPHL2
TTHL
TTLH
CONDITIONS (NOTE 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
FCL
LIMITS
MIN
MAX
UNITS
+25oC
560
ns
10, 11
+125oC, -55oC
756
ns
+25oC
650
ns
10, 11
+125oC, -55oC
878
ns
+25oC
200
ns
10, 11
+125oC, -55oC
270
ns
+25 C
1.5
MHz
10, 11
+125oC, -55oC
1.11
MHz
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
1, 2
-55oC, +25oC
+125 C
150
-55oC, +25oC
10
+125oC
300
1, 2
1, 2
-55 C, +25 C
10
+125oC
600
Output Voltage
VOL
1, 2
+25 C, +125 C,
-55oC
50
mV
Output Voltage
VOL
1, 2
+25oC, +125oC,
-55oC
50
mV
Output Voltage
VOH
1, 2
+25oC, +125oC,
-55oC
4.95
Output Voltage
VOH
1, 2
+25oC, +125oC,
-55oC
9.95
IOL5
1, 2
+125oC
0.36
mA
-55oC
0.64
mA
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125oC
0.9
mA
-55oC
1.6
mA
+125oC
2.4
mA
-55oC
4.2
mA
+125oC
-0.36
mA
-55oC
-0.64
mA
+125oC
-1.15
mA
-55oC
-2.0
mA
+125oC
-0.9
mA
-55oC
-1.6
mA
+125oC
-2.4
mA
-55oC
-4.2
mA
VIL
1, 2
+25oC, +125oC,
-55oC
VIH
1, 2
+25oC, +125oC,
-55oC
+7
7-1208
SYMBOL
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
1, 2, 3
+25oC
230
ns
Propagation Delay
Clock to Output
TPHL1
TPLH1
VDD = 15V
1, 2, 3
+25 C
160
ns
Propagation Delay
Reset to Output
TPHL2
VDD = 10V
1, 2, 3
+25oC
225
ns
Transition Time
TTHL
TTLH
FCL
TRCL
TFCL
TW
TW
TW
VDD = 10V
NOTES
CIN
VDD = 15V
1, 2, 3
+25 C
170
ns
VDD = 10V
1, 2, 3
+25oC
100
ns
VDD = 15V
1, 2, 3
+25oC
80
ns
VDD = 10V
1, 2, 3
+25 C
MHz
VDD = 15V
1, 2, 3
+25oC
MHz
VDD = 5V
1, 2, 3, 4
+25oC
15
VDD = 10V
1, 2, 3, 4
+25 C
VDD = 15V
1, 2, 3, 4
+25oC
VDD = 5V
1, 2, 3
+25 C
400
ns
VDD = 10V
1, 2, 3
+25oC
200
ns
VDD = 15V
1, 2, 3
+25oC
140
ns
VDD = 5V
1, 2, 3
+25 C
250
ns
VDD = 10V
1, 2, 3
+25oC
110
ns
VDD = 15V
1, 2, 3
+25oC
80
ns
VDD = 5V
1, 2, 3
+25 C
200
ns
VDD = 10V
1, 2, 3
+25oC
100
ns
VDD = 15V
Input Capacitance
Any Input
1, 2, 3
+25 C
70
ns
1, 2
+25oC
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
1, 4
+25oC
25
N Threshold Voltage
VNTH
1, 4
+25oC
-2.8
-0.2
N Threshold Voltage
Delta
VTN
1, 4
+25oC
P Threshold Voltage
VTP
1, 4
+25oC
0.2
2.8
P Threshold Voltage
Delta
VTP
1, 4
oC
Functional
+25
+25oC
VOH >
VDD/2
VOL <
VDD/2
1, 2, 3, 4
+25oC
1.35 x
+25oC
Limit
ns
TPHL
TPLH
VDD = 5V
7-1209
SYMBOL
DELTA LIMIT
IDD
1.0A
IOL5
IOH5A
GROUP A SUBGROUPS
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
Sample 5005
Subgroup B-5
Sample 5005
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B
Group D
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
OPEN
GROUND
VDD
Static Burn-In 1
Note 1
3-6, 11-14
1, 2, 7-10, 15
16
Static Burn-In 2
Note 1
3-6, 11-14
1, 2, 7, 9, 10,
15, 16
7, 8, 15
2, 10, 16
3-6, 11-14
1, 2, 7, 9, 10,
15, 16
Irradiation
Note 2
9V -0.5V
50kHz
3-6, 11-14
1, 9
25kHz
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V 0.5V
7-1210
CD4518BMS, CD4520BMS
Logic Diagrams
Q1
3/11
VDD
VSS
Q2
4/12
D Q
C Q
R
D Q
C Q
R
Q3
5/13
D Q
C Q
R
Q4
6/14
D Q
C Q
R
RESET
7/15
ENABLE
2/10
CLOCK
1/9
FIGURE 1. DECADE COUNTER (CD4518BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS
VDD
Q1
3/11
Q2
4/12
Q3
5/13
Q4
6/14
VSS
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
RESET
7/15
ENABLE
2/10
CLOCK
1/9
FIGURE 2. BINARY COUNTER (CD4520BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS
TRUTH TABLE
CLOCK
ENABLE
RESET
Increment Counter
Increment Counter
No Change
No Change
No Change
0
X
X
0
1
X
X = Dont Care
ACTION
No Change
Q1 thru Q4 = 0
1 High State
0 Low State
7-1211
CD4518BMS, CD4520BMS
25
20
15
10V
10
5
5V
0
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
10
15
0
-5
-10
-15
-10V
-20
-25
-15V
-30
-5
-10V
300
SUPPLY VOLTAGE (VDD) = 5V
200
10V
100
15V
50
0
20
30
40
50
60
70
80
LOAD CAPACITANCE (CL) (pF)
90
-15
10
-10
-15V
350
150
250
30
100
350
300
SUPPLY VOLTAGE (VDD) = 5V
250
200
150
10V
100
15V
50
0
10
20
30
40
50
60
70
80 90
LOAD CAPACITANCE (CL) (pF)
100
110
7-1212
CD4518BMS, CD4520BMS
200
150
100
10V
15V
50
0
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
15
10
10
15
SUPPLY VOLTAGE (VDD) (V)
104 8
6
4 SUPPLY VOLTAGE (VDD) = 15V
2
103 8
6
4
2
10V
102 8
10V
6
4
2
5V
CL = 50pF
10 8
CL = 15pF
6
4
2
1
2
4 68
0.1
4 68
4 68
4 68
102
10
4 68
103
104
Timing Diagrams
1
10 11 12 13 14 15 16 17 18
10 11 12 13 14 15
CLOCK
ENABLE
RESET
1
Q1
CD4518BMS
Q2
Q3
Q4
Q1
CD4520BMS
20
Q2
Q3
Q4
FIGURE 12. TIMING DIAGRAMS FOR CD4518BMS AND CD4520BMS
7-1213
CD4518BMS, CD4520BMS
CLOCK
INPUT
VDD
1
15
10
15
10
11
12
13
14
CD4518BMS/20BMS
11
12
13
14
CD4518BMS/20BMS
FIGURE 13. RIPPLE CASCADING OF FOUR COUNTERS WITH POSITIVE EDGE TRIGGERING
CD4071
CLOCK*
INPUT
15
10
11
12
13
14
CD4520BMS
CD4012A
CD4071
15
10
12
13
14
CD4520BMS
CD4012A
CD4012A
CD4520BMS
* For synchronous cascading, the clock transition time should be made less than or equal to the sum of the fixed propagation delay at 15pF
and the transition time of the output driver stage for the estimated capacitive load.
FIGURE 14. SYNCHRONOUS CASCADING OF FOUR BINARY COUNTERS WITH NEGATIVE EDGE TRIGGERING
7-1214
CD4518BMS, CD4520BMS
Chip Dimensions and Pad Layouts
CD4518BMS
CD4520BMS
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
AL.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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