ECE 4436

Chap. 7: HCS12 Instruction Set

Dept. of Electrical & Computer Engineering
University of Houston

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Table 7-1
Instruction
Categories

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Load Register Instructions

Table 7-5 Load Register

Instructions, show addr
modes & condition codes

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Load Register Instructions

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Store Register Instructions

Table 7-6 Store

Register
Instructions

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16- Bit Load and Store Instructions

Fig 7-1 16-bit Load

and Store

Example 7-1 Load and Store Register Instructions

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Loc
Obj. code Source line
------ --------- ----------; Immediate addressing
000000 8640
ldaa #64
;
000002 CF09 02
lds
#$0902 ;
; Direct addressing
000005 D664
ldab $64
;
000007 5A65
staa $65
;
; Extended addressing
000009 B612 34
ldaa $1234
;
00000C FE12 34
ldx
$1234
;
00000F 7E08 00
stx
$0800
;
; Indexed addressing
000012 E6E0 17
ldab 23,x
;
000015 6B40
stab ,y
;
000017 A63E
ldaa 2,x;
;

Ex. 7-1 Load and

Store Instructions,
show addr mode
syntax

Decimal 64 -> A
$0902 -> SP
($0064) -> B
A -> ($0065)
($1234) -> A
($1234:1235) -> X
X -> ($0800)

(X+23) -> B
B -> (Y)
(X) -> A
X-2 -> X (Auto
decrement)
20
; Indexed-indirect addressing
21 000019 EEEF
ldx
[d,y]
; ((D+Y)) -> X
22 00001B A6E3 0100
ldaa [$100,x]; ((X+$0100)) -> A

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Stack Instructions
Stack Pointer (SP) 16-bit address register that points to
the value on top of the stack.
Stack grows toward lower addresses.
Push operation puts new value on top of stack:
Decrement SP
Store value where SP points
Pull (pop) operation take value off top of stack:
Load value from where SP points
Increment SP

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after push

before

after pull

after 2nd push

after 3rd push

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Uses for the Stack

Temporarily saving a few bytes of data from registers,
then restoring later.
Allocating data space for temporary variables such as
automatic variables in C.
Saving the return address when the program calls a
subroutine. This is done automatically by the jump-tosubroutine instruction (JSR or BSR).
Similarly, saving the return address when an interrupt
occurs.
Normally, stack operations must be balanced, push
operations matched by pull/pop operations.

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Simple Stack Example

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Ex. 7-8 Stack

example, whats
wrong?

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Calling Subroutines
To call a subroutine:
JSR subr Jump to subroutine (many addressing modes)
BSR subr Branch to subroutine (9-bit relative)
Each works like this:
1. Pushes PC (return address, of next instruction) onto
stack.
2. Starts execution at target address (subr).
Last instruction in subroutine:
RTS Return from subroutine
Pops address off stack into PC, thus resuming
execution following the original JSR/BSR.

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Calling Subroutines

jsr printf
; call print function
<next instruction>
Address of this next
instruction (PC) is pushed
by jsr instruction.

printf:
<do printing>
rts

; return

Top of the stack is popped into the PC by

the rts instruction, returning execution
to the instruction following the jsr.

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Ex. 7-7 Stack

example, whats
wrong?

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Load Effective Address Instructions

Ex. 7-11 Load

Eff Addr
Instructions

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Clear and Set Instructions

Table 7-10 Clear and

set instructions

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Bit Clear and Set Instructions

Fig. 7-4 BCLR and

BSET for LEDs

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Fig. 4-1 MC9S12C

family block diagram

MC9S12C

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Hardware Memory Map for 9S12C32

I/O registers appear
at these addresses.

Fig 6-2
Memory map

Example 7-20 LED Program Using BCLR and BSET

Rel. Loc
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8 000000
9
10 000003

11 000006
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000009
00000C
00000F
000012
000015
000018
00001B
00001E

Obj. code Source line

--------- -----------

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XDEF Entry, main

Entry:
main:
0000 0002 DDRA: EQU
$0002 ; Data direction register
0000 0000 PTA:
EQU
$0000 ; Port A register
; . . .
4C02 FF
bset DDRA,%11111111 ; Make all lines
output
loop:
4C00 FF
bset PTA,%11111111
; Set all bits,
LEDs off
4D00 01
bclr PTA,%00000001
; Clear bit 0,
LED on
4D00 02
bclr PTA,%00000010
; Clear bit 1
4D00 04
bclr PTA,%00000100
; Clear bit 2
4D00 08
bclr PTA,%00001000
; Clear bit 3
4D00 10
bclr PTA,%00010000
; Clear bit 4
4D00 20
bclr PTA,%00100000
; Clear bit 5
4D00 40
bclr PTA,%01000000
; Clear bit 6
4D00 80
bclr PTA,%10000000
; Clear bit 7
20E3
bra
loop
; Do it forever

Ex. 7-20 LED

program using
BCLR and BSET

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Shift and Rotate Instructions

Table 7-11 Shift

and Rotate
Instructions

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Shift and Rotate Instructions

Fig. 7-5 and 7-6 Arithmetic Shift

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Shift and Rotate Instructions

Fig. 7-7 and 7-8 Logical Shift

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Shift and Rotate Instructions

Fig. 7-9 and 7-10 Rotate

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Arithmetic Instructions

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Arithmetic Instructions contd

Table 7-12
Arithmetic
Instructions

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Example 7-26 Multibyte Addition with D Register

Arithmetic Instructions

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Obj. code Source line
------ --------- ----------XDEF Entry, main

000000 FCxx xx

Entry:
main:
; Load 16 bits from Data1:Data1+1
ldd
Data1
; Add 16 bits from Data2:Data2+1
addd Data2
; Save the result
std
Data3
; Stores 16 bits
; . . .
Data:
SECTION
Data1: DS.W 1
Data2: DS.W 1
Data3: DS.W 1

Ex. 7-26 Multibyte

000006 7Cxx xx addition with D Reg
000003 F3xx xx

000000
000002
000004

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Example 7-25 Multibyte Addition withECE
Carry3436
Bit
; Add the least significant bytes first
;
Get least sig byte of 16-bit Data1
ldab Data1+1
;
Add in the least sig byte of Data2
addb Data2+1
; The sum is in B and the carry bit now has the
; carry out that must be added into the most
; significant byte addition.
; Get most sig byte, ldaa does not change the carry
ldaa Data1
;
Add most significant plus carry
adca Data2
std
Data3
; Stores 16 bits
; . . .
Data:
SECTION
Data1: DS.W 1
Data2: DS.W 1
Data3: DS.W 1

Ex. 7.25 Multibyte

addition with carry
bit

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Logic Instructions

Table 7-13
Logic
Instructions

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Ex. 7-38 Logic

instructions

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Data Test Instructions

Table 7-15 Data

test instructions

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Conditional Branch Instructions

Table 7-26
Conditional Branch
Instructions

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Signed vs. Unsigned Comparisons

Consider two 8-bit quantities: $FE and $01
If they are being used as unsigned numbers, $FE is 254:
254 > 1
$FE > $01
bhi, blo, bhs, bls will give correct sense.

If they are being used as signed numbers, $FE is -2:

-2 < +1
$FE < $01
bgt, blt, bge, ble will give correct sense.

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Ex. 7-41 Conditional

Branches

Example 7-42 BRSET and BRCLR Instructions

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000004
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000009
15

Obj. code Source line

--------- ----------XDEF Entry, main

Entry:
main:
0000 0080 BIT_7:
0000 0040 BIT_6:
0000 0240 PORTT:

EQU
EQU
EQU

%10000000
%01000000
$240

; Mask for Bit-7

; Mask for Bit-6
; Address for
Port T

Ex. 7-42 BRSET and

BRCLR
; . . . instructions

; WHILE Bit-7 is zero, wait for it to

become one
wait_for_7:
1F02 4080
brclr PORTT,BIT_7,wait_for_7
FB
; . . .
; WHILE Bit-6 is one, wait for it to
become zero
wait_for_6:
1E02 4040
brset PORTT,BIT_6,wait_for_6
FB
; ...

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Loop Primitive Instructions

Table 7-18 Loop

primitive
instructions

Example 7-43 Loop Primitive Instruction

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; Comparing loop primitive and "normal"

; decrement and branch instructions.
0000 03E8 COUNT1: EQU
1000
; Counter value
0000 00FF COUNT2: EQU
255
; Max 8-bit counter
; . . .
000000 CE03 E8
ldx
#COUNT1 ; Initialize counter
; . . .
loop:
; Here is the repetitive code
; . . .
000003 0435 FD
dbne x,loop ; Using dbne instr
; Demonstrate 8-bit decr, then branch
000006 C6FF
ldab #COUNT2 ; Initialize counter
loop2:
; Here is the repetitive code
; . . .
000008 53
decb
000009 26FD
bne
loop2

Ex. 7-43 Loop

Primitive Instructions

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Unconditional Jump and Branch

Table 7-19
Unconditional
jump and
branch

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7.21 Conclusion and Chapter Summary Points