Scribd Logo
Fazer o upload

Bem-vindo(a) ao Scribd!

  • AY 3 8910 - Feb 1979 PDF

    Enviado por

    Milton del Basso
    0 visualizações62 páginas

    Título original

    AY-3-8910_Feb-1979.pdf

    Direitos autorais

    © © All Rights Reserved

    Formatos disponíveis

    PDF ou leia online no Scribd

    Você considera este documento útil?

    Este conteúdo é inapropriado?

    Denunciar este documento

    Direitos autorais:

    © All Rights Reserved
    Baixe no formato PDF ou leia online no Scribd
    Sinalizar o conteúdo como inadequado
    0 visualizações62 páginas

    AY 3 8910 - Feb 1979 PDF

    Enviado por

    Milton del Basso

    Direitos autorais:

    © All Rights Reserved
    Baixe no formato PDF ou leia online no Scribd
    Sinalizar o conteúdo como inadequado
    de 62
    [=] . : AY-3-8910/8912 PROGRAMMABLE SOUND GENERATOR DATA MANUAL ARCHITECTURE OPERATION INTERFACING MUSIC G=NERATION SOUND EFFECTS GENERATION ELECTRICAL SPECIFICATIONS TABLE OF CONTENTS—PAGE 2 FEBRUARY 1978 Table of + TRODUCTION 4) Description Contents +2 Features 3 Scope 2. ARCHITECTURE 21 Basic Functional Blocks . 211 Register Array... 212 Sound Generating Blocks 243 VO PONS......cseseeeeeesseee 22 Pin Assignments : 23 Pin Functions 2... .csecscs as 24 Bus Timing 25 State Timing 25.1 Address PSG Register Sequence 252 Wate Data to PSG Sequence . 253 Reac Data from PSG Sequence 25 4 Wate 1o/Read from 1/0 Port Sequence 3. OPERATION 3.1 Tone Generator Control .... 32 Noise Generator Controt 3.3 Mixer Control—V/O Enabl 3.4 Amplitude Control 35 Envelope Generator Control . 351 Envelope Period Control 352 Envelope Shape/Cycle Contro 36 1/0 Port Data Store 37 DvA Converter Operation INTERFACING V Introduction... 42 Clock Generation 43 Audio Output Interface ... 44. External Memory Access .. 45 Microprocessor/Microcomputer Interface 46 Intertacing to the PIC 1650, 46.1 Write Data Routine 462 Read Data Routine 463 Read ROM Routine 47 Intertacing to the CP1600/1610 471 Write Data Routine 47.2 Read Data Routine 4 Interfacing to the M6800... - 481 Latch Address Routine 482 Write Data Rout : 4.8.3 Read Oata Routin 49 Interfacing to the 8080 $100 Bus... 491 Latch Address Routine 492 Write Data Routine . 493 Read Data Routine - wt EEREASSSSESHRSSRREBE 18 2 22 24 24 BR 128 8 5. MUSIC GENERATION 5.1 Note Generation 5.2 Tune Entry/Playb: 5.3 Tune Variation 5.3.1 Octave Shit: 532 Key... 533 Tempo. 5.34 Chords........ 5.4 Sound Variation ....... patie 5.41 Relative Channel Volume .. : 5.42 Decay......... : 8.43 Other Eliecis |. 5.5 Applications ...... 55.1 Organ Envelope Generation . 5.5.2 Organ Rhythm Generation 6. SOUND EFFECTS GENERATION 6.1 Tone Only Effects - 7 62 Noise Only Effects . i 6.3 Frequency Sweep Effects... 6.4 Multi-Channel Effects eet 7. ELECTRICAL SPECIFICATIONS 1 Maximum Ratings E 72 Stangard Condieons 7.3 DC Charactenstics .....! 74 AC Characteristics 7.5 Package Outlines gare geeseegseseaas List of illustrations Typical System Diagram ...... PSG Biock Diagram PSG Register Array AY-3-8910 Pin Assignments AY-3-8812 Pin Assignments Variable Amplitude Control. 21.1. Envelope Shape/Cycie Control... Detail of Two Gycles of Fig. 7 OVA Converter Output 10 Single Tone with Envelope Shape’Cycle Pattern 1000 . 11 Single Tone with Envelope Shape’Cycle Pattern 1100 12 Single Tone with Envelope Shape’Cycle Pattern 1010 eof Three Tones with Fixed Amplitudes 14 Systom Stock Biagrom 15 Clock Generation ... 16 Audio Output intertace 17 External Memory Access. 18 Microprocessor/Microcomputer intertace . 19 PIC 1650/AY-3-8910 System Example 20 CP1600/1610/AY-3-8910 interface . 21 M6BO0/AY-3-8910 interface 22 8080 $100 Bus/AY-3-8910 Interiace 23 Equal Tempered Chromatic Scale Fig. 24 Chord Selection Chart....-.....-. Fig. 25 Organ Envelope Generation - Fig. 26 Organ Rhythm Generation .. Fig. 27 European Siren Sound Effect Chant Fig. 28 Gunshot Sound Effect Chart Fig. 29 Explosion Sound Effect Chart eseeeReeess geeerssaa i Fig 30 Laser Sound Effect Chart @ List Of Fo 3 eee eee oe ict chan Fg 82 wort Wisse Soune enact Chart Mlustrations Fig. 33 Race Car Sound Effect Chart . (COnt.) 9 34 Anaiog Cnanne! Cutout Test Cweut pave yeiEin gs Corn te vanee Comet et areca Fig 38 Clcek an Bos Signal Tings fi De or poem muppet eerescuee eect ela caer meats ting pacer a e.orne Dane tang cei nat enice rt eTIGIle BSLIssag Fig 40 Read Data Timing. 59 Fig. 41 40 Lead Dual In Line oO Fig. 42 28 Leag Dual in Line 16 11 Description INTRODUCTION ST it is apparent that any microprocessor 1s capable of producing acceptable sounds with only a transducer it the processor has no other tasks to perform while the sound 's sustained. In real world microprocessor use. however. video games need retreshing. key- boards need scanning, etc, For example. in order to producea single channel of ninth octave C (8372 Hz) the signal needs attention every sixty microseconds. Software required to produce this simple effect and still perform other activities would in the least be very complex if not impossible. In the extreme, random noise requires periodic atten- tion even more frequently. This need for software-produced sounds without the constant attention of the processor is now satisfied with the availability of the General instrument AY-3-8910 and AY-3-8912 Programmable Sound Generators. Tne AY-3-8910'8912 Programmaple Sound Generator (PSG) 1s 2 Large Scale Integrated Circuit which can produce a wide variety of complex sounds under software contro! The AY-3-8910/8912 is manufactured in GI's N-Channe! ton implant Process. Operation requires a single SV power supply. a TTL compatible clock. and a microprocessor controller such as the G! 16-bit CP1600/1610 or one ‘of GI's PIC 1650 series of 8-bit microcomputers ‘The PSG is easily interfaced to any bus oriented system Its flexibility makes it useful in applications such as music synthesis. sound effects generation. audible alarms. tone signalling and FSK modems The analog sound outputs can each provide 4 bits of logarithmic digital to analog conversion. greatly enhancing the dynamic range of the sounds produced In order to perform sound effects while allowing the processor to continue its other tasks, the PSG can continue to produce sound after the initial commands have been given by the control processor The fact that realistic sound production often involves more han one effect is satisfied by the three independently controllable channels available in the PSG. Allof the circuit contro! signals are digital in nature and intended to be provided directly by @ microprocessor/micracomputer. This means that one PSG can produce the full range of required sounds with no change in external circuitry. Since the requency response of the PSG ranges from sub-audible at its lowest frequency to post: audible at its highest frequency. there are few sounds which are beyond reproduction with only the simplest electrical connections Since most applications of a microprocessor/PSG system would also require interfacing between the outside world and the microproces- or, this facility has been designed into the PSG. The AY-3-8910 nas two general purpose 8-bit 1/0 ports and 1s supplied in a 40 lead package: the AY-3-8912 has one port and 28 leads. —————— 12 Features 13 Scope Fig. 1 G Fun sottware contro! of sound generation ~ G interfaces to most 8-bit and 16-bit microprocessors G Three independently programmed analog outputs. O Two 8-bit general purpose 1/0 ports {AY-3-8910) 1 One 8-bit generat purpose 1:0 port (AY-3-8912) 1D Single +5 Volt Supply This Data Manual is intended to introduce the techniques needed to cause the AY-3-8910/8912 Programmable Sound Generator to per- form in its intended tashion. All of the programs. programming, and hardware designs have been tested to ensure that the methods are practical rather than purely theoretical Although the techniques described will produce powertul results, the range of sounds to be synthesized is so vast and the PSG capabilities so varied that this guide should be viewed merely as an introduction to the applications possibilities of the PSG TYPICAL SYSTEM DAG anavos & LT Functional Blocks ARCHITECTURE The AY-3-8910/8912 is a register oriented Programmable Souns Generator (PSG). Communication between the processor and the PSG is based on the concept of memory-mapped 1/0. Control ‘commands are issued to the PSG by writing to 16 memory-mapped registers Each of the 16 registers within the PSG is also readable so that the microprocessor can determine, as necessary. present states or stored data values. All functions of the PSG are controlled through its 16 registers which once programmed, generate and sustain the sounds. thus freeing the system processor for other tasks An internal block diagram of the PSG showing the various functional blocks and data flow 1s shown in Fig. 2 2.1.1 REGISTER ARRAY The principal element of the PSG 1s the array of 16 read/wnte contro! registers. These 16 registers look to the CPU as a block of memory and as such occupy a 16 word block out of 1.024 possible addresses The 10 address bits (8 bits on the common data/address bus. and 2 separate address bits A8 and AG) are decoded as follows ai[DAd] * A8 s not Bro 308 Gn ire £Y-3-8912 FS as [oa7 [ons]ons] one oaa]OA ol teolejo}ol{olojolo THRU Rohrer TTT: HGH Low ORDER ORDER {Chup Select) Register») The four low order address bits select one of the 16 registers (RO-- A179). The six high order address bits function as “chip selects” to control the triestate bidirectional buffers (when the high order address bits are “incorrect”, the bidirectional buffers are forced tc a high impedance state). High order address bits A9 A8 are fixed inthe PSG design to recognize a 01 code: high order address bits DA7~ DA4 may be mask-programmed to any 4-bit code by a special order factory mask modification. Unies otnerwise specited. adaress bis high order address laiches the reg eTOW Order 4 bits) inthe Register Address Latch/Decoder biock. A latched address will temain valid until the receipt of a new address. enabling multiple reads and writes of the same register contents without the need for redundant re-addressing. al 7 Fig. 2 PSG BLOCK DIAGRAM ok acomecions. an DurrENe ‘Decoe a Bat re Tet rT Come Tare ‘BAIT fe Tune rt Cours Tune Jcnanne @ Tore Pene cnanna Yon Banoo recisres eee Pena EBT Peres Convo. seonese a = okcoDee [crane CAnpiie o eat irtuet S. Coare Tare E sont] APY TAT ALLEL LO on Poh 2 erage Perce CONTROL Re STERS rosrt000 toarou0 te 21 Basic Functional Blocks {cont.) Conditioning of the Register Address Latch/Decoder and the Bid'- rectional Buffers to recognize the bus function required (inactive, latch address, write data, or read data) is accomplished by the Bus Control Decode block The function of each of the 16PSG registers and the data flow of each register’s contents are shown in context in Fig. 2 and explained in detar! in Section 3. “Operation”. For reference purposes. the Register Array details are reproduced in Fig. 3 2.1.2 SOUND GENERATING BLOCKS The basic blocks in the PSG which produce the programmed sounds include: Tone Generators produce the basic square wave tone frequen- cies for each channel (A.B.C) Noise Generator produces a frequency modulated pseudo random pulse width square wave output. Mixers combine the outputs of the Tone Generators and the Noise Generator. One for each chan- nel (A.B.C) Amplitude Contra! provides the D/A Converters with either a fixed or variable ampiituae pattern, The fixed amplitude is under direct CPU control; the variable amplitude ts accomplished by using, the output of the Envelope Generator Envelope Generator produces an envelope pattern which can be Used to amplitude modulate the output of each Mixer. O/A Converters the three D/A Converters each produce upto a 16 level output signal as determined by the ‘Amplitude Contro! 2.1.3 VO PORTS Two aduitional blocks are shown in the PSG Block Diagram which have nothing directly to do with the production of sound—these are the two VO Ports (A and 8). Since virtually all uses of microproces- sor-based sound would require interfacing between the outside world and the processor. this facility has been included in the PSG. Data to/trom the CPU bus may be read/written to either of two &-bit V/O Ports without affecting any other function of the PSG. The YO Ports are TTL-compatible and are provided with internal pull-ups on ‘each pin, Both Ports are available on the AY-3-8910, only /O Port Ais available on the AY-3-8912 Fig. 3 PSG REGISTER ARRAY 7 ncausrer CCranne:& Tone Per Ccnannes 8 Tone Pee eo Channa A amontase ‘Cranne Baneutaae Grane CAvpnuee Enron Sse Gree TO Pon A Oats Sire ef] or] ow set iretoe tet fe Taree Tat Gorm Tee Rot tneTome Ta Coma mee Ser Panos Corre = o t o © o n ONT DBT PARALLE. LO onPon A TT PaRAE LOPE 2.2 The AY-3-8910 is supplied in 2 40 lead dual in- ine package with the i? = pin assignments as shown in Fig, 4, The AY-3-8912s supplied in a 28 Pin Assignments ead ouatin-tine package with the pin assignments as shown in Fig § Fig. 4 AY-3-8910 PIN ASSIGNMENTS ———. Too view Vas (GND) NC ANALOG CHANNEL 8 ANALOG CHANNEL A NC. 1087 1086 108s 1oB4 1083 1082 1081 1080 1OA7 TOA6 TOAS. 1OAa 1OA3 TOA2 ToAr Ver (+5¥) TEST) ANALOG CHANNEL C Dao Dat a2 Aa Das DAS. DAS. Da7 Bc! cz DIR TEST 2 a8 J RESET cLock Too - Fig 5 AY-3-8912 PIN ASSIGNMENTS Top view ANALOG CHANNEL C TEST) Vee (+5¥) ANALOG CHANNEL B ANALOG CHANNEL A Ves (GND) 1OA7 T0A6 10AS TOA TOA TOAz Toas 10A0 23 Pin Functions DAT--DAO (inpul/output/high impecance): pins 30--37 (AY-3-8910) Data/Address 7- pins 21--28 (AY-3-8912) These 8 lines comprise the 86-bit bidirectional bus used by the microprocessor to send both data and addresses to the PSG and to receive data from the PSG. In the data mode, DA7--DA0 correspond to Register Array bits 87-80. In the address mode, DA3--DA0 select the register # (0-17.) and DA7--DA4 in conjunction with address inputs A9 and A8 form the high order address (chup select) ‘AB (input): pin 25 (AY-3-8910) eat pin 17 (AY-3-8912) HS (input): pin 24 (AY-3-8910) (not provided on AY-3-8912) ‘Address 9, Address 8 These “extra” address bits are made available to enable the position- ing of the PSG (assigning a 16 word memory space) in a total 1.024 word memory area rather than in a 256 word memory area as defined by address bits DA7--DAO alone. If the memory size does not require the use of these extra address lines they may be left unconnected as ach is provided with either an on-chip pull down (A9) or pull-up (AB) resistor. in “noisy” environments, however. it is recommended that AB and AB be tied to an externai ground and + SV. respectively, if they are not to be used RESET (input): pin 23 (AY-3-8910) pin 16 (AY-3-8912) For initialization/power-on purposes. applying a !ogic "0" (ground) to the Reset pin will reset all registers to "0", The Reset pin is provided with an on-chip pull-up resistor, CLOCK (input): pin 22 (AY-3-8910) pin 15 (AY-3-8912} This TTL-compatible input supplies the timing reference for the Tone. Noise ard Envelope Generators. BDIR, BC2, BCt (inputs): pins 27,28 29 (AY-3-8910) pins 18.19.20 (AY-3-8912) Bus DiRection, Bus Control 2.1 These bus control signals are generated directly by GI's CP1600 series of microprocessors to contro! all external and internal bus ‘operations in the PSG. When using a processor other than the CP1600. these signals can be provided either by comparable bus signals or by simulating the signals on 1/O lines of the processor. The PSG decodes these signals as illustrated in the following 3 23 Pin Functions (cont) Ey 5 cow *s0 2 § 8 eduction Function OC 0 NACT INACTIVE See 010 (IAB below Of 1 DAR LATCH ADDRESS. See 111 UNTAK) below D1 0 TAB’ INACTIVE The PSG ‘CPU bus 8 nactve DAZ--DAO ae 1 1 DYE READ FROM PSG. Ths signal causes ine conten Shoetr cn'ne PSG GPL bss GATORS aren we 7 10 0 BAR CATCH ADDRESS See 111 INTAK) below 10 + OW INACTIVE See O10 K6) above 1} 8 OWS WRITE TO P56, Tha signet nceaes a the ous contains register data which shoul be latcheo into the currently agaressed register OAT—DAO are in the input moce 3 1 1 INTAK LATCH ADDRESS This signalsnaicatesinatine bus Contains a reg:sier aaaress which shoule be latched Inthe PSG_DA—-DAO are in the input mode While interfacing to a processor other than the CP1600 would simply require simulating the above decoding. the redundancies in the PSG. functions vs. bus control signals can be used to advantage in that only four of the eight possible decoded bus functions are required by the PSG. This could simplify the programming of the bus contro! signals to the following, which would only require that the processor generate two bus control signals (BDI and BC1. with BC2 tied to +5V): « 55 eso 8 8 8 8 Function © 0 INACTIVE = 0 1 1 READFROMPSG = — 1 1 0 WRITE TO PSG. 1 1 1 LATCH ADDRESS ANALOG CHANNEL A, B, C (outputs). pins 4 3, 38 (AY-3-8910) pins 5.4, 1 (AY-3-8912) Eacn of these signals is the output of its corresponding D/A Converter. and provides an up to 1V peak-peak signal representing the complex sound waveshape generated by the PSG. IOAT--10A0 (inpuvoutput): pins 14--21 (AY-3-8910) pins 7--14 (AY-3-8912) TOB7--10B0 (input/output): pins 6--13 (AY-3-8910) {not provided on AY-3-8912) Input/Output A7--A0, B7--BO Each of these two parallel input/output ports provides 8 bits of parallel data to‘trom the PSG/CPU bus from/to any external devices connected to the IOA or IOB pins. Each pin is provided witn an on- chip pull-up resistor, so that when in the “input” mode, all pins wil read normally high. Therefore. the recommended method for scan- ‘nung external switches. for example, would be to ground the input bit 14 24 Bus Timing eee ee TEST 1: pin 39 (AY-3-8910) pin 2 (AY-3-8912) TEST 2: pin 26 (AY-3-8910) (not connected on AY-3-8912) ‘These pins are for GI test purposes only and snould be ‘eft open—do Not use as tie-points Vee: pin 40 (AY-3-8910) pin 3 (AY-3-8912) Nominal -5Volt power supply to the PSG Vss: pin 1 (AY-3-8910) pin 6 (AY-3-8912) Ground reference for the PSG Since the PSG functions are controlled by commands trom tne system processor, the common datavaddress bus (DA7--DA0i re- quires definition as to its function at any particluar time This 's, ‘accomplished by the processor issuing bus control signals. previ- ‘ously described, defining the state of the bus; the PSG then decodes these signals to perform the requestec task ‘The conditioning of these bus control signals by the processor isthe same as if he processor were interacting with RAM (1) the processor outputs a memory address: and (2 the processor either outputs or inputs data to/from the memory. The "memory" in this case is the PSG's array of 16 read/write control registers The tuming relationships in issuing the bus control signals relative to the data or address signals on the bus are reviewed in general in the following section. and in detatlin Section 7. Electrical Specifications 6 —_ 25 State Timing While the state tlow for many microprocessors can be somewnat involved tor certain operations. the sequence of events necessary to control the PSG is simple and straightforward, Each of the three ‘major state sequences (Latch Address. Write to PSG. and Read trom PSG) consists of several operations (indicated below by rectangular blocks). defined by the oattern of bus contro! signals (BDIR, BC2. BC1) i Aaoress ano wre cata 7 ie eseee segs rercrares tm na seen deca aeecaeesecemeera ' 1 saver of seer Ld feseerrer errr YO 2eerercerercee cre coureur InactWE cyte The functionat operation and relative timing of the PSG control sequences are described in the following paragraphs (in all exam- ples, BC2 has been assumed to be tied to logic “1”, ~5V) 28.1 ADDRESS PSG REGISTER SEQUENCE The “Latch Address” sequence is normally an integral part of the wnite or read sequences, but for simplicity is illustrated nere as an individuat sequence. Depending on the processor used the program sequence wili normally require four principal microstates: (1) send NACT (inactive). (2) send INTAK (latch address), (3) put address on bus. (4) sen¢ NACT (inactive). (Note. within the timing constraints detailed in Section 7. steps (2) and (3) may be interchanged. | coytmee mcr VA wex WA act oar-0K0 Fost oureut roar 7 7 Aone ° LT ES 2.8.2 WRITE DATA TO PSG SEQUENCE The “Write to PSG" sequence. which would normally follow immedi- ately alter an address sequence, requires four principal microstates (1) send NACT (inactive). (2) put data on bus. (3) send DWS (write to PSG), (4) send NACT (inactive) a contr para FORT oureuy oaTe soar . = 2.5.3 READ DATA FROM PSG SEQUENCE As with the "Write to PSG” sequence. the “Read from PSG" sequence would also normally follow immediately after an address sequence The four principal microstates of the read séquence are" (1) seno NACT (inactive). (2) send DTB (read from PSG). (3: read data on bus. (4) send NACT (inactive), 60R i ne connor eet Eg ore ZZ mer )A7--DAC Float a FLOAT baer is 2.5.4 WRITE TO/READ FROM VO PORT SEQUENCE ‘Since the two I/O Ports (Aand 8) each have an B-bit register assigned as a data store. writing 10 or reading fron either port is identical to writing oF reading to any other register Hence. the state sequences are exactly the same as described in the preceding paragraphs. | ————— ” Vv) 3 OPERATION TT Since all functions of the PSG are controlled by the host processor via a series of register loads, a detailed description of the PSG operation can best be accomplished by relating each PSGfunctionto the control of its corresponding register. The function of creating oF programming a specific sound or sound effect logically follows the control sequence listed: ‘Section Operation Registers Function 3.1 Tone Generator Control OAS Program tone periods 32 Noise Generator Control «RE Program noise penod 33 Muer Control AT Enable tone and:or novse ‘on selected channe!s 34 Amphtude Contro! RIO-AI2_ Select Wxed oF “envelove- vanaple’ ampiitudes 35 Envelope Generator RI3-R15 Program envelope penios Contra! ‘and select envelope pater 3.1 The frequency of each square wave generated by the inree Tone Generators (one each for Channeis A. 8. and C) ts obtained 1m the Tone Generator °sc by tirst counting down the put clock by 16, then by further Control cou down te reat ty the programmes 2 Tone, Pend value. Each 12-bit value is obtained in the PSG by combining tne contents of the relative Coarse and Fine Tune registers. as illustrated (Registers RO, RI, R23. RA. RS) in the tollowing: @ Coarse Tune a vase ied eet page ™ * mo ares os] oeos]er]or CCC CCC z \ Teui]ovo] too] Toe | er] 78 [os] vee | rea] ee] ve [1h] 12-bit Tone Period (TP) to Tone Generator Note that the 12-bit value programmed in the combined Coarse and Fine Tune registers is a period value—the higher the value in the registers. the lower the resultant tone frequency Note alsc that due to the design technique used in the Tone Period count-down, the lowest period value is 000000000001 (divide by 1) and the highest period value 1S 111111111111 (divide by 4.095:0) 18 The equations describing the relationsnip between the desired ‘output tone frequency and the input clock frequency and Tone Period value are. Where. fr =desired tone frequency input clock frequency fecimal equivalent of the Tone Period bits TP11--TPO. fecimal equivalent of the Coarse Tune register bits B3~B0 (TP11--TP8) Jecimal equivalent of the Fine Tune register bits 87-80 (TP7--TPO) tevoce TPro CT FTr0 Fron. she above equations it can be seen that the tone frequency can range from a low of 2B (wherein: TPio=4.09510) to a high of “ir (wherein: TP.=1). Using a 2 MHz input clock, for example. would produce a range of tone frequencies from 30.5 Hz to 125 KHz To calculate the values for the contents of the Tone Period Coarse and Fine Tune registers. given the input clock and the desired output tone frequencies. we simply rearrange the above equations, yielding feces Flu _ TP (a) TP. (oy Cte - EE = ae Example 1: f= tk? (goa = 2MHE 2x10" TP. = ee = Peo = Fecimioy ~ 78 Substituting this result nto equation (0) Fle _ 128 Ty + He a BS Ct * a6 7 66 w0Te = 0000 (83--B0) Fro = 01111701 (87-60) Example 2 ty fevoee 2x10" 16(1x10") eal Substituting this resutt into equation (01 2150 Ly. 256 256 ye = 0100 (B3--B0) 26,9 = 11100010 187--B0) 18 3.2 Noise Generator Control (Register RG} The frequency of the noise source is obtained in tne PSG by first ‘counting down the input clock by 16. then by further counting down the result by the programmed 5-bit Noise Period value This 5-bit value consists of the lower § bits (B4-B0) of register RE as tilustrated in the following Nowe Penos Negiser Ae (ele le Tolle [e[o] orp noae Foran nny ok paient ote Note that the 5-bit value in R11 1s a period value—the higher the value in the register. the lower the resultant noise frequency. Note also that. as with the Tone Period, the lowest period value is 00001 (divide by 1). the highest period value ts 11111 (divide by 3110) ‘The noise frequency equation is fase iene Where: tw ferocx NPro jesired noise frequency yput clock frequency jecimal equivalent of the Noise Period register bits B4~B0. From the above equation it can be seen that the noise frequency can range from a low of “3° (wherein: NPyo = 3tro) to a high of “7 (wherein: NP.c = 1). Using a 2 MHz input clock. for example, would produce a range of noise frequencies from 4 kHz to 125 KHZ To calculate the value for the contents of the Noise Peniod register given the input clock and the desired output noise frequencies, we simply rearrange the above equation, yielding: 20 3.3 Mixer Control- 1/0 Enable (Register 07) eee Register 7-1s a multi-function Enable register which controls the three NoiSe/Tone Mixers and the two generai purpose I/O Ports The Mixers, as previously described. combine the noise and tone frequencies fo each of the three channels, The determination of ‘combining neiher/either/both noise and tone frequencies on each channel is made by the state of bits B5~-B0 of A7 The direction (input or output } of the two general purpose I/O Ports (IOA and 108) 1s determined by the state of bits 87 and B6 of R7. These functions are illustrated in the following Miner Control 0 Enaie Repisier R7 ejlelelele ye] funcnor (REPS crane Trae eae] | Noise Enable Truth Table Tone Enable Truth Table. RT Bits Noite Enabled RT Bits Tone Enabled 8s B+ 83 ‘on Channel 82 81 Bo on Channel ooo ca, 00 0 cae; oot cea - 004 C6 010 cra oro cA Onieet c= ont e- = 100 mary 100 = 8A 101 = 8 - 4,04 - 8 - 110 eet +10 ==: fea --- ra ere VO Port Truth Table aT Bits V0 Port Status e786 © 10B TOA © 0 mput— Input 0 1 input Output 1 0 Output input + 1 Output Output ROTE Disabling nowe and tone does not turn off a channel, Turning 2 cehanne! of! can only be accompiisned by writing all zeroes into the corresponding Amplitude Control register, AIO. AIT. or AN2 (see Section 3.4) a 3.4 Amplitude Control (Registers R10, R11, A12) The amputudes of the signais generated by each of the three D/A Converters (one each for Channels A. 8. and C) ig determined by th. contents of the lower 5 bits (B4--BO} of registers R10. R11, and A12as illustrated in the following ‘Amplitude Control Register # Channet aro a An 8 Riz c Pree mE Es The amplitude “mode” (bit M) selects either fixed level ampitude (M=0) or variable level amplitude (M=1). Itfollows then that bits L3-~ LO. defining the value of a “fixed” level ampiitude, are only active when M=0. When fixed evel amplitude is selected, itis “fixed” only in the sense that the amplitude level 1s under the direct control of the system processor (via bits D3~-D0). Varying the amplitude when in this “fixed” amplitude mode requires in each instance the direct intervention of the system processor via an address laten ‘write data sequence to modity the 03-00 data When'M=1 (select "variable" level amplitudes). the amplitude of each channel is determined by the envelope pattern as defined by the Envelope Generators 4-bit output E3 E2 E1 E0. The amplitude "mode" (bit M) can also be thought of asan “envelope enable" bit: 1e.. when M=0 the envelope 1s not used. and when M=1 the envelope 1s enabled. (A full description of the Envelope Gener- ator function follows in Section 3.5) el 22 The full chart describing all combinations of the 5-bit Amplitude } Control is as follows: Amplitude Controt Register # Channel AYO A An 8 riz c a7] 66] 65] 6«]8a[e2|er[e0 TE TLLLT se Mus W2 Lt Lo Output © 0 0 0 0 0 0 0 DO )} The amoutuse is fixed at 1 oF 18 leve's as getermines by paeree aerate eee 9 LP CHL, ‘The ampinuge 1s variapie at 16 levels 1X XX XK ES ER Et ED} as determined by the ‘output of ine "TD Envelope Generator Ea ‘Tne an zeroes coge is wea ‘oir acranne on Fig. 6 graphically illustrates a selection of variable level (envelope- @ controlled) amplitude where the 16 levels directly refiect the output of the Envelope Generator. A fixed level amplitude would correspond to only one of the levels shown. with the level'directly determined by the decimal equivalent of bits L3L2 L1 LO. Fig. 6 VARIABLE AMPLITUDE CONTROL (M=1) —_- 3.5 Envelope Generator Control MRegisters R13, 4. R15) To accomplish the generation of fairly complex envelope patterns, Iwo independent methods of contro! are provided in the PSG. first it {s possible to vary the frequency of the envelope using registers F13 and R14: and second, the relative shape and cycle pattern of the envelope can be varied using register R15. The following paragraphs explain the details of the envelope control functions. describing first the envelope period control and then the envelope shapevcycie contro! fo 3.5.1 ENVELOPE PERIOD CONTROL (Registers R13, At4) The frequency of the envelope is obtained in the PSG by first counting down the input clock by 256. then by further counting down the result by the programmed 16-bit Envelope Period value. This 16-bit value ts obtained in the PSG by combining the contents of tne Envelope Coarse and Fine Tune registers. as illustrated in the following: SD a = Eel tL 16:0: Envelope Pernod /E°) 10 Envevope Genera Note that the 16-bit value programmed in the combined Coarse ang Fine Tune registers is a period value—the higher the vatue in the registers, the lower the resultant envelope frequency. Note also. that as with the Tone Period, the lowest period value is 0000000000000001 divide by 1): the highest period value 1s TUNITITTTTIT (aivide by 65.5350) The envelope frequency equations are tesoee o 2 fa) te = See (0) EP ie=258CT 0 FT» Where: fe =desired envelope frequency fevoex = input clock frequency EP.o= decimal equivalent of the Envelope Period bits EP15--EPO CT19=decimal equivaient of the Coarse Tune register bits B7--B0 (EP15--EP8) FT19= decimal equivalent of the Fine Tune register bits B7--B0 (EP7--EPO) From the above equation it can bee seen that the envelope frequency Gan range trom a low of e7#%— (wherein: EP\>=65,535:0) toa high of “a (wherein: EP.o=1). Using a 2 MHz clock. for example, would Produce a range of envelope frequencies from 0.12 Hz to 7812.6 Hz. ™ To calculate the vaiues for the contents of the Envelope Perioo Coarse and Fine Tune registers. given the nput clock ang the desired envelope frequencies. we rearrange the above equations. yielding Fle _ EPs a) Eve Hepes ieee ay es to) Ce + Se = SE Example: EP = See = 18.625 Supsiiving ins result no equation Fhc . 15628 og. 2 He” 256 a 00111101 (87-801 OTe = 3.5.2 ENVELOPE SHAPE/CYCLE CONTROL (Register RTS) The Envelope Generator further counts down the envelope tre- quency by 16, producing a 16-state per cycle envelope pattern as define by its 4-bit counter output, £3 E2 E1 EO. The particular shape and cycle pattern of any desired envelope is accomplished by controlling the count pattern (count up/count down) of the 4-bit counter and by defining a single-cycle or repeat-cycte pattern This envelope shape/cycle control is contained 1n the lower 4 bits (83-60) of register R15. Each of these 4 bits controls a function in the envelope generator. as illustrated in the following Envelope Shape ‘Cycle Gontrat Register (R15) es]aa]="]8 Commu The definition of each function is as follows: Hoid when set to logic “1”. limits the envelope to one cycle. holding the last count of the envelope counter (E3~- E0=0000 or 1111, depending on whether the envelope counter was in a count-down or count-up mode. respec tively) Alternate when set to logic “1”. the envelope counter reverses ‘count direction (up-down) after each cycle. NOTE Wnen both the Hold bit and the Alternate bit are ones. the fenvelope counter #5 reset to tS anitial count before holding 8 3.5 Envelope Generator Controt (cont.) Fig. 7 Attack wher set to logic "1", the envelope counter will count up. (attack) from £3 £2 E1 E0=0000 to E3 £2 £1 EO=1111 when set to logic "0". the envelope counter wil! count down (decay) from 1111 to 0000. Continue when set to logic “1”, the cycle pattern will be as detinec by the Hold bit: when set to logic “0”, the envelope generator will reset to 0000 after one cycle and hold at that count. To further describe the above functions could be accomplished by numerous charts of the binary count sequence of €3 £2 £1 £0 for each combination of Hold. Alternate, Attack and Continue. However since these outputs are used (when selected by the Ampi:tude Control registers) to amplitude modulate the output of the Mixers, a better understanding of their effect can be accomplished via a graphic representation of their value for each condition selected. as illustrated in Figs. 7 and 8 ENVELOPE SHAPE‘CYCLE CONTRO! ———— bito Sueur nee. Fig 8 DETAIL OF TWO CYCLES OF Fig. 7 (ret, waveform "1010" in Fig. 7) ‘ntcort Gtatearoe ar eo 3.6 1/0 Port Data Store (Megisters R16, R17) Registers R16 and R17 function as intermediate data storage regis- ters between the PSG/CPU data bus (DAO-DA7) and the two VO ports (IOA7—IOA0 and IOB7--IOB0). Both ports are available in the AY-3-8910. only I/O Port A is available in the AY-3-8912. Using registers R16 and R17 for the transter of I/O data has no effect at all ‘on sound generation To output data from the CPU bus to a peripheral device connected to VO Port A would require only the following steps: 1. Latch address R7 (select Enable register) 2. Write data to PSG (setting BE of R7 to * 3. Latch address R16 (select IOA register) 4, Write data to PSG (data to be output on 1/0 Port A) To input data from I/O Port A to the CPU bus would require the following: 1. Latch address A7 (select Enable register) 2. Write data to PSG (setting B6 to R7 to "0") 3. Latch address R16 (select IOA register) 4, Read data from PSG (data trom /O Port A} Note that once loaded with data in the output moge, the data will remain on the I/O port(s) until changed either by loading different data. by applyinga reset (grounding the Reset pin), or by switching to the input mode. Note also that when in the input mode, the contents of registers R16 and/or R17 will follow the signals applied to ine i/O port(s). However. transfer of this data to the CPU bus requires a “read” operation as described above 28 3.7 Since ine primary use of the PSG is to produce soung tor the nighly o impertect amplitude detection mechanism of the human ear, the D/A D/A Converter’ conversion is performed in logantnmic steps with a normalized 0 ti voltage range of from 0 to 1 Voll. The specific amplitude control o! PEFatiON each of the three D/A Converters is accomplished by the three sets 0" 4-bit outputs of the Amplitude Control block, while the Mixer outputs provide the base signal frequency (Noise and/or Tone} Fig. 9 illustrates tne D/A Converter output which would result it noise and tones were disabled and an envelope-controlled variable ampli- tude were selected Figs. 10 through 13 illustrate other typical output waveforms Fig. 9 D/A CONVERTER OUTPUT (Cet. Fi. 6) —— NORMALIZED VOLTAGE bs NOTE THIS IS THE ENVELOPE ONLY NOISE AND TONES. [ARE DISABLED. ror = DECIMAL VALUE OF exeze1 €0. (SEE AMPLITUDE ZZ SENTROL 7 SECTION 34) EP ENVELOPE PERIOD Fig. 10 SINGLE TONE WITH ENVELOPE SHAPE CYCLE PATTERN 1000 (RO=14.. h1=37...R7=76s, A12=20,, R1S=10., all other registers=0} Fig. 11 SINGLE TONE WITH ENVELOPE SHAPE/CYCLE PATTERN 1100 (R15=14,, all other registers same as Fig. 10) ——< ST 30 Fig. 12 SINGLE TONE WITH ENVELOPE SHAPE-CYCLE PATTERN 1010 e {A15=12., all other registers same as Fig. 10) ——____"_— ————_——_—_—————— AT Fig. 13. MIXTURE OF THREE TONES WITH FIXED AMPLITUDES smn e 31 4 introducti Fig, 4 INTERFACING TT 1 Since the AY-3-8910/8912 PSG must be used with support compo: nents, interfacing to the circuit isan obvious requirement. The PSG's IM designed to be controlled by a microprocessor or microcomputer. and drive directly into analog audio circuitry. It provides the link between the computer and a speaker to provide sounds or sound effects derived {rom digital inputs. The following paragraphs provide examples and illustrations show- ing the ease with which an AY-3-8910/8912 Programmable Sound Generator may be utilized in a microprocessor/microcomputer system. 14 SYSTEM BLOCK DIAGRAM —————— microprocessoa MichocomPuTe® ‘BU CONTROL systew cLocK GENERATOR wee. L-1] 32 4,2. An economical solution to providing a system clock 1s shown in Fig Ee 15. It consists of a 3579545MHz standard Color burst crystal. a Clock co4069 CMOS inverter, and 8 CD4013 to divide the color burst a frequency in half The clock produced for the PSG runs at a Generation 17337725ur2 rate Depending on the m:crocomputer used. its clock should be selected within iis specitied valve Fig. 15 CLOCK GENERATION ———— a srasesaons Gaver, Int yeerr2Ms IUF Lote 10 PSG “oss ‘os : 23 Me 3 43 Audio Output huterface Fig 1€ Fig. 16 wlustrates the audio output connections to a commercially available LM386 audio amplifier. It shows channels A. 8. and C summed together to enable complex wavetorms to be composed and amplified through a single external amplifier. These channels may be Individuaily amplilied through separate channels for more exotic sound systems. Each output channel is individually controlied by separate amplitude registers (R10. R11, A12) and an enable register (R7) in the PSG AUDIO OUTPUT INTERFACE ———— ‘ANG CHANNEL OUTPUTS, 34 44 External Memory Access Fig. 17 ‘The ROM or PROM shown connected to the PSGir Fig *7 illustrates an option for providing additional data information for processor support The two I/O registers within the PSG are used in this case to address the memory via I/O Port A (8 Bits) and read data {rom ine memory via I'O Port B (8 Bits) An example of the bus contro! sequence to address and read an external memory connected to 1'O ports A and B would be as follows (Assume Port A addresses and Port B reads) Bus Codes Bus Controt_ BDI BC2 BC1 Explanation of Bus Data (OAT-DA0) Laten address == 1100000111 Latch A7 to program 1 O Ports Wete to PSG. 1 1 @ 01000000 Set 87 BE 100.7 respectively Latcn agaress == 11100001110 Latch AYE to aaaress memary Wate to PSG 1 1 Q 09000001 Aagress aaa to memory Latch agaress = 1110000119? Later RIT 10 reac memory Reaa irom PSG 011 XXXXXXXX Memory gata contained!” R17 NOT. BC2:n ine above Bus Codes may be permanent’, ved 10 ~ SV tr 5 requiring onty two US contro! lines for all control operations rete: 12 Section 23 for a complete explanation: ‘Also. RAM or EAROM may be used in place of the ROM or PROM shown by altering the program to use PORT B as an I-O. Port B then will be able to write data as an output and read cata as an input EXTERNAL MEMORY ACCESS ——————— o 45 Microprocessor/ Microcomputer Interface Fig. 18 In Fig_ 18. the ines identified DA7--DA0 are the input/output bus bits. 7--0. This 8 bit bus is used to pass all data anc address information between the AY-3-8910/8912 and the system processor. 8C1, BC2 and BDIR are bus contro! signals generated by the processor to direct all bus operations. These operations are identi- fied as Latch Address, Write to PSG. Read from PSG, and Inactive. The following Sections detail specific interfaces to several popular microprocessors/microcomputers, MICROPROCESSOR/MICROCOMPUTER INTERFACE —_— ow 46 Interfacing to the PIC 1650 Fig. 19 shows the schematic of an AY-3-8910 demonstrator circult This configuration uses a PIC 1650 as the main controller in the circuit. The PIC 1650 1s used to scan the keyboard, fetch data from the PROMs, write data to the AY-3-8910 and provide the timing for the AY-3-8910 The interfacing is direct since the PIC 1650 and the AY-3-8910 ‘operate with compatible supplies and input/output voltages This particular schematic illustrates how a microcomputer with additional memory can produce a stand-alone music and sound effects circuit. The circuit as shown operates with manual keyboard selections. As Fig. 19 shows. the design for the interface connects directly tothe output pins of the 1650 and the BC1. BC2. BDIR pins. The software then has the responsibility of manipulating these signals to signal the PSG to pertorm the proper address latch. read or write operations ‘The program routine in this section illustrates code which is usedin a hand-held demonstrator unit. This demonstration unit illustrates the range of PSG capabilities, including music, sound effects and VO control. Note that the generalized routines perform the address latching before every read for convenience’ The “READ ROM" routine illustrates use of the generalized read and write routines to access the outside world through the PSG to read and write. 4.6.1 WRITE DATA ROUTINE 0 WRITE FROM 1650 TO 8910 a ADDRESS OF 8910 REG IN ADDRES 2 ATA TO WRITE IN ‘DATA c 83 024 0066 WAIT! MOVWF ADDRES 7 84 025 1026 WRITE MOVF ADDRES W GET REGISTER NO 85 026 0045 MOVWE 104 SET AODRESS 86 027 1006 MOVE IOBW — GETPRESENTEC! BC? BOIRETC 87 030 7370 ANDLW 370 88 031 6404 IORLW 4 SET BAR 89 032 0046 Movwr 108 SENO BAR 90 033 7370 ANOLW 370 91 034 0046 MOVWF 108 SENO NACT 92.035 1027 MOVE OATAW 93.036 0045 MOWWF TOA. PUT DATA ON 0 A PINS OF 8910 94.037 1006 MOVF 108.w 95 040 7370 370 96 041 6406 6 97 082 0046 to8 SEND OWS, 98 083 7370 370 SET UP NACT 99 084 0046 108 SEND NACT 300 045 4000 RETUAN TO CALLING ROUTINE a 4.6 Interfacing to the PIC 1650 (cont.) 4.6.2 READ DATA ROUTINE St 82 53 Sa 55 56 sr 58 59 ry 6 2 83 6 65 6 o 68 ° 70 " n 2 74 005 oo ‘02 003 008 (005 006 or 070 on or2 013 ons ons on6. or 026 02: 022 023 ADORESS OF READ IN REGISTER ADORES AFTER READ INPUT DATA IN REGISTER OATA ENTRANCE READ’ ASSUMES THAT REGISTER Now 1S 0066 READ! MOVWF ADDRES 1026 REAG MOVF ADDRES Ww 04s 1006 ean 086 7370 oa 6 045 1006 1376 6403 ose 1008 067 1006. 1376 0046 4000 MOWWF 108 MOVE 108.W TORLW MovWr 108 ANDLW 370 MOvWE 108 MOVLW 377 MOVWE 104 MOvF 108w ANDLW 370 TORLW 3 MOvWF 108 MOVE IOAW MOVWE DATA MOvF 108 w ANDLW 370 MOVWF 108 RET 4.6.3 READ ROM ROUTINE ADDRESS OF ROM IN W AT ENTRANCE NEXRO! ADDRESS OF ROM IN ROMAO AT ENTRANCE ROMRD 108 107 108 108 100 ne 13 5 ne nT? ne 9 120 yr a7 ost 052 055 122 056 123 057 124 125 061 1032 5015 2396 1425 1266 oro 2706 400: 2686 402: BYPASS ADDRESS STORE GET REGISTER NO MOVE TO B9iC D A Fin GET PRESENT BC1 EC? BDIR ETC SET BAR ‘SENO BAR, SENO NACT SET FOR INPUT ser ote SENG OTB. SAVE DATA SEND NACT RETURN TO CALLING ROUTINE INCREMENTS ROMAD AFTER READ \F ROU ADDRESS CROSSES 256 BORDER MAKE UPPER Banx SE_EC USES 8910 REG 16 FOR ADDRESS {8910 REG 17 FOR INPUT DATA NEXROM MOVF ROMAO Wy ROMAD MOVWF DATA MOVLY 16. MOVWF ADDRES Scr 10B6 CAL waITe INCF ADDRES CALL READ BSF 1086 INCFSZ ROMS ET BSF 108s RET Put RODRES: OA ADDRESS, TUAN ON ROM SEND TO 108 TC.10B ADDRESS GET DATA TURN OFF ROM TONEXT LOC SET HIGH SELECT RETURN TO CAL. NG ROUTINE 47 Interfacing to the CP1600/1610 ‘As shown in Fig. 20, the wiring is direct between the AY-3-6910 anda CP1600/1610 microprocessor The levels are compatible thus elimi- ‘nating any need for level converters. Even the terminology between the iC’s remains constant to provide simple-to-follow connections ‘The CP1600/1610 acts as a controller in this configuration fetching data from ROM's contained elsewhere in the system. The CP1600/ 1610 also acts as the bus controller developing the necessary timing for the AY-3-8910. 4.7.1 WRITE DATA ROUTINE The program necessary to write to a selected register ts as follows: MVI value, RO; move in value to be written MVO RO. Reg: write to register The routine to load all registers with the same value is as follows: MVII Reg 0. R4 CLAR RO Here MVO@ RO. R4 CMPI Reg 0 + 17. Rh BLT Here 4.7.2 READ DATA ROUTINE The routine to read from a selected register 1s as follows MVI Reg, RO, get data from reg in RO MVO RO. value: store in memory eee) Fig. 20 CP1606 1610 AY-3-8910 INTERFACE ————— ‘crnon 168 a 48 Interfacing to the M6800 ‘An M6800 microprocessor can be interfaced with an AY-3-8910/8912 through the addition of an M6820 PIA chip, The 1/O ports designated as PAO to PAT are used as the 8 bit bus lines and I/O ports PEO to PB2 are used as the bus control lines. The software routines shown are used to control the latch address, write data, and read data functions for the AY-3-8910/8912, 4.8.1 LATCH ADDRESS ROUTINE IAT ENTRY, 8 HAS ADDRESS VALUE LATCH CLRA STAA 8005 :GET D DIR A LOAA #FF STAA 8004 :OUTPUTS, LDAA #4 STAA 8005 :GET PERIPHERAL A. STAB 8004 ‘FORM ADDR STAA 8006 CLRA STAA 8006 :LATCH ADDRESS RTS [RETURN 4.8.2 WRITE DATA ROUTINE [AT ENTRY, B HAD DATA VALUE WRITE STAB 8004 :FORM DATA LDAA #6 :DWS STAA 8006 CLARA STAA 8006 WRITE DATA ATS ;RETURN 4.8.3 READ DATA ROUTINE :AFTER READ. B HAS READ DATA READ STA A 8005 GET D DIR STA A 8004 :INPUTS LDAA #4 STA A 8005 :GET PERIPHERAL DECA ‘STA A 8006 ;READ MODE LDA B 8004 :READ DATA CLRA ‘STA A 8006 REMOVE READ MODE ATS "RETURN ° 6800 eat-———Joro Pa} ———Jon2 ee i Stee Siecle, 43 49 Interfacing to the 8080 $100 Bus The-sample S100 bus design provides for reading and writing the PSG using only an 8080 "IN" or “OUT” instruction to the proper address Anotner feature of the design is the provision for multiple PSG cevices to be connected toa single bus. The system described s Presently running two PSG's. one to each of two stereo channels As can be seen {rom the read and write routines in the illustrative program, the program overhead necessary to communicate with the PSG is minimal 4.9.1 LATCH ADDRESS ROUTINE PORTADDR EGU 80H |ADDRESS TRANSFER PORT ADDRESS PORTOATA EQU 81H DATA TRANSFER PORT ADDRESS ‘THIS ROUTINE WILL TRANSFER THE CONTENTS OF (8080 REGISTER C TO THE PSG ADDRESS REGISTER PSGBAR MOV AC GET C INA FOR OUT. OUT —PORTBAR ‘SEND TO ADDRESS PORT RET 4.9.2 WRITE DATA ROUTINE ROUTINE TO WRITE THE CONTENTS OF 8080 REGISTER 8 TO THE PSG REGISTER SPECIFIED BY B080 REGISTER C PSGWRITE CA.i PSGBAR :GET ADDRESS LATCHED MOv A. .GET VALUE IN A FOR TRANSFER OU? PORTDATA PUT TO PSG REGISTE® id .3 READ DATA ROUTINE ROUTINE TO READ THE PSG REGISTER SPECIFIED ‘BY THE 8080 REGISTER C AND RETURN THE DATA IN 8080 REGISTER 8 PSGREAD CALL PSGBAR IN PORTDATA GET REGISTER DATA MOV B.AGET IN TRANSFER REGISTER RET ADVAUBLNI 0169-C-AV/SNA 001s O88 zz 614 45 5.1 Note Generation MUSIC GENERATION The production of music involves the creation of series of frequen- cies which are pleasing to the human ear (setting critical evaluation aside). This involves essentially mathematical relationships. making the application ideal for digital devices. For example, the shitting up ‘or down in octaves 1s a multiplication or division by a power of 2. which is a simple shift operation for most microprocessors, Another tactor in music generation 1s “communication”. The com- poser must be able to convey his tune ideas so that a musician or group of musicians can reproduce the composer's ideas—often on widely differing instruments. This concept involves “tuning” the instruments to a standard set of frequencies and following a set rhythm pattern. The tuning frequency most widely used is based on the third octave note “A” of 440H2. the "Equal Tempered Chromatic Scale’ Although it is easy to construct recognizable tunes using only one note ata time, the simultaneous sounding of more than one note to produce chords and counterpoint vastly increases the quality of the sound. This feature is easily achieved in the PSG since three channels are provided. each independently programmable Since notes are formed by sustaining a particular frequency tor a preset period of tme at a varying amplitude. the PSG pertorms this function with a series of simple register loads. The method used in many cases is to obtain register load values for first octave notes and to shift to the correct octave at playtime. The chart in Fig. 23 lists a full 8 octaves of notes from a low of C1 (82.703H2) to a high of B8 (7902.080Hz). Assuming an input clock frequency of 1.78977MHz (one half the standard “color” crystal frequency of 3.579545MHz). and applying the formulas of Section 3.1 for calculating Tone Period register load values, results in the register values shown. The nature of the PSG divider scheme produces a high degree of accuracy tor low frequencies, less for high frequencies. This can be seen in the chart in the comparison of “ideal frequencies” and “actual frequencies”. with the ideal frequencies being those of the Equal Tempered Chromatic Scale. and the actual frequencies being the “best fit” values from the formula calculation 46 UHWeebus 1" 1) dTWOS OILWWOUHD O3uaGWaL IWNOS Cz O14 v1 oo (080 206 a z oy € 0 656r6r rr 095 ese " 0 9 © 0 WORF o 2 0 0 ‘000 Ors ¥ 9 ¢ © 0 LeCOR 1 2 0 0 roa v9 "9 Sot y 0 sees 2 2 G6 0 errize are Lce8 ° Sof F 0 verc6e © 2 0 0 Circoes zB 618s 6 8 S$ F 0 Corl yr 2 0 0 BeDCEss iz Less 3 0 0 § 0 seer 5 2 0 0 verges — rae Eres e 3 © 2 $ 0 Fu66ze 3 2 0 0 ies ra0s SD acer a 0 0S $ 0 roi 0 0 0 a99099r 929869 e Q 5 ¢ S$ 0 peste Eee CHIE OH EHOSHeaEEVe "6 & 0 y 2 9 0 ceeoe ieee ie oFtHo 986 ® a y 5 9 0 aseise y © 0 0 B2058ee oro LSE 1 é S 0 f 0 ce6are 9 ¢ oC 9 tegeet — owe saute “ oy 4 0 ceocce 0 G 0 EraserE a0 02se t v yok 4k 0 peice. Z 0 0 eeoo6eE ze zee 1 "0 ££ 0 05 102 yy 0 0 wie — 9B SCIE 4 5 HEEL HO) 9 Fr C 0 SoLcrEe — ste 6s6z 4 " scot 9 $ 0 0 cesoese — 9588612 1 4 40 e 2 § 0 0 zsccogz 265 at9e 4 3 eciereuie S$ 0 oc Serserz veo sere 1 0 zou e 0 8 0 0 ctrocez ete gree a Q 2 © 2 9 0 0 Gizseee aap aize 1 2 cory 5 3 0 0 266 2602 4 2 “2 § toe 0 0 oes S61 ° a eee > 4 0 0 2 ” oo 8 oo 4 Oo 9 v eeeEHaEeEe coo 1 Oo 3 0 s 9 0 2 coo to a 5 GH DEEL rou og 9 4” steed D2 1 oo a 4 or 2 $s 2 4 0 a 3 Piste eee ea eet z © 1 Oo a "0 Fe eHEHOHHHe Foss teeteur} a Q yoo ue Soy io reg ap eeeN se aU ate: es too a a8 9s 2c 1 9 4 0 8 arth 2 € Leese HELD. $ wore 0 0 9 EHO EHEC HeEEEO: 5 vs z 9 1 € 2 0 2 0 a a a ee 24 2 0 Gree § ° eos cy 2 2 2 0 oogor 5 4 se og sy oF 2 0 ocless § 4 200 & z 5 2 9 s00es9 a2 659 5 3 ree 2 ¢ > 9 2 0 brie ose 229 $ "9 your s ac 9 4 2 0 ines eee 2s s a -hor Lt § Bu8e z Lo co jBEss e9E ¥55 s ° yc 2 9 | esKe 9 2 6 0 Mees a2 625 9 2 Ss € $ 9 gece W120 MIANTVA ADNENOIUs ADNZNORWI |AVLDO LON A AONENORS ADNANOSS 3AVLOO 310N waisiogy Lez, Wwniov. Waal to WALOv. Wal 5.2 Tune Entry/ Playback 53 Tune Variations One of the methods of entering a composition into a computer memory would be to utilize a keyboard tc pass number and alphabetic information concerning the composer's wishes. An alte nate method would be to scan a positional series of switches (like a piano keyboard) to determine note. volume and duration data Since flexibility in tune entry 1s desired. it 1s important to allow the composer to specity certain constants of entry such as octave. pitch ‘or tempo. and have these entries normalized to a known value. ‘One of the significant features of a microcomputer based music player is the ability 10 modity the tune once it has been recorded ‘Among the simpler variations are 5.3.1 OCTAVE SHIFT Ian octave constant is added to the octave of the recorded note prior to storing the value in the PSG register. dynamic pitch changes can be obtained. The programming effect would be to shift one bit left tor each lower octave and one bit right for each higher octave. For ‘example, the effect will be that a tune written to play on a piano will sound like bells if a multiple octave up modification is performed 5.3.2 KEY ‘One measure of the virtuosity of amusicianis his ability to modity the “Key” or suboctave shit of a composition The logical description of key transposition 1s to shit each note up or down by apredetermned number of notes from the original. Fer example. a piece written in C and played in Ca would have ali C notes shifted to Cw, Ce shiftedtoD. etc. (Note that the case must be considered where B of one octave 1s shitted to C of the next higher octave.) All of these operations require that the one of twelve note identification must be retained in tne recorded representation 5.3.3 TEMPO The duration of each recorded note is best expressed in terms of ‘ticks” of an overall “tempo clock” At playtime, the total durationcan be obtained by programatically multiplying the individual note to "slow down’ or “speed up" the tune without changing the crucial time relationship between the notes. This can be accomplished by imbedding the note timing loops within the tempo timing loops for ‘simple operation. Fig. 24 5.3.4 CHORDS There are certain combinations of notes which when played simul taneously produce pleasant combinations. These “chords” can be easily formed trom a base note by performing octave and key changes on two notes. which are played with tne main note These felationships are illustrated in Fig 24, which lists the various note constants which will produce musical chords. A chord with a particular quality may be formec by playing its root. a 3rd Minor or Major. and other notes from the chord chart. For example, a C Major chord 1s formed from C(+2). E(=2). and Gt=2). CHORD SELECTION CHART eer 49 5.4 Sound Variation 5.4.1 RELATIVE CHANNEL VOLUME. The independently programmable amplitude control for each chan- Nel allows up to 16 levels if using the processor controlled amplitude mode (bit 4 of registers 10. 11 or 12=0). In the case of a decaying or steady note, when anote is played or “fired”, a frequency may be set up in the coarse and fine tune registers and then an amplitude value placed in the respective register 10, 11 or 12, The h is placed to play the tune can be an independent liowing channels to play their respective melody lines with varying force. 5.4.2 DECAY The main difference between a “piano” sound and an “organ” sound is the speed with which the note loses volume. Ifall of the notes can be decayed at a uniform rate, the automatic envelope generator can be set to produce a decaying waveform. Each of the three channels can have the same decay constant but differing playing times to simulate the same instrument with differing note-strike times. 5.4.3 OTHER EFFECTS The addition of variable noise to any or all of the channels can Produce modification effects such “breathing” with a wind instru- ment. Or noise can be used alone to produce a drum rhythm. The fact that the noise dominant frequencies are variable allows “synthesizer type effects with simple processor interaction. Other pleasing effects include vibrato and tremolo, the cyclical variation of the frequency and volume. Because an intelligent microprocessor is controlling the effect. they can be all keyed to ine tune itself or 10 other external stimuli 55 Applications Fig. 25 While many applications of the PSG in music generation are apparent, for instance in the area of toys and games. other applica- tions are possible even in the area of high accuracy sophisticated musical instruments such as high-end electronic organs. With tone frequencies generated from another source to meet the exacting requirements of organ operation, tne PSG can be used as a complex envelope generator The PSG 1s also effective for generating bass notes and rhythms with percussion instruments. taking advantage of the PSG's high accuracy in producing low frequency notes The following paragraphs detail examples of these applications. 5.5.1 ORGAN ENVELOPE GENERATION The envelope generation diagram shown in Fig. 25 illustrates how an AY-3-8910 can be configured to produce envelopes for organ voicing, All functions are controlled by @ microcomputer The basis of this system consists of a master frequency generator with a string of dividers. This produces all frequencies for the keyboard. The microcomputer and the AY-3-8910 are actually used to replace the usual components of voicing filters that would ordinarily be used in an electronic organ ‘The microcomputer shown isa GI PIC 1650 controlled by inputs from the keyboard keyer circuit and a contro! switch matrix. The keyer inputs octave and key closure information to develop the envelope amplitude and duration tor the note to be played. The control switch matrix can be used to control sustain and add other special effects ‘The ROM shown connected to the AY-3-8910 1s optional depending on the amount of data necessary for the microcomputer The system shown here may also consist of multiple AY-3-8910's. all controlled by a single microcomputer. It represents an economical solution to developing voicing contro! with a minimum of compo- nents, ORGAN ENVELOPE GENERATICN st 5.5 5.5.2 ORGAN RHYTHM GENERATION a The rhythm generation diagram (Fig. 26) illustrates a simplified @ Applications sersicnot now a microcomputer can be implemented with the AY-3- 8810 to provide a percussion instrument section for an electron (cont) 8212! movee abe jon for an electronic The microcomputer used in this case could be a GI PIC 1650 which can be internally programmed to drive a series of AY-3-8910. all hardwired to an 1/0 port of the PIC. Each AY-3-8910 provides a Separate output envelope and frequency of the instrument i 1s 10 synthesize The Rhythm Switch Matrix is used to select any preprogrammed rhythm pattern and tempo from the PIC. The instrument Select switches allow manual in‘out selection of tne 8910's via the AB and A address lines providing additional instrument sound variations ‘These switches are intended to be user-selected and mounted ina convenient position on the instrument In addition. optional ROMs could be added to the PSG 1/0 ports. saving microcomputer ports. to provide extra rhythm fengin or number of patterns. These ROMs could aso be replaced by EAROMS: to provide user rhythm programming trom a modified Rhythm Switch, Matnx The programmable rhythm feature could be used to add new or original user rhythms to update the instrument Fig. 26 ORGAN RHYTHM GENERATION ———s = e ae, \—+ ror] fe fears av.t9%c (SNARE DRUM ars Soca LAY avcasi yO cemaa: EXTRA #8105 AS REQUIRES 6 SOUND EFFECTS GENERATION TS One of the main uses of the PSG is to produce non-musical sound effects to accompany visual action of as a feature in itself, The following sections outline techniques and provide actual examples of some popular effects All exampies are based on a 1.78977MHz PSG clock 6.1 Manyettects are possible using only the tone generation capability of the PSG without adding noise and without using the PSG's envelope Tone Only generation capability. Examples of this type of ettect would include Effects ‘leonore lone ieauencies (wo distinct trequencies, progucea simultaneously) or the European Siren effect listed in Fig. 27 (two. distinct fr-quencies sequentially produced). Fig. 27 EUROPEAN SIREN SOUND EFFECT CHART ——_—_—_e ~ Octal Register# Load Value ‘Explanation Any not specities 000 = RO 326) Set Channel A Tone peroa to 227m mn 00 (aout) a7 076 Enable Tone only on Channe! A only Ric ov Select maximum amplitude on Channes & (Wat approxmately 350ms before continuing) Fo 126] Sel Channel A Tone peroo 0 Ans I oot (1872) (Wait azproximatety 350ms before continuing Aro 000 Tum off Channel A to end souns etfect —_—_— 6.2 Noise Only Effects Fig. 28 Fig. 2¢ Some ct the more commonly required sounds require only the use of Aoise ang tne envelope Generator (or orocesscr contro! of channel envelope if other channels are using the envelope generator) Examples of this. which can be seen in F.gs. 28 and 29. are gunshot and explosion in Soth cases pure noise is used with a decaying envelope. In the examples shown the only changes are in the length of the envelope as modified by the coarse tune register and in the noise period. Note that a significantly lower explosion can be obtained by using all three channels operating with the same parameters. GUNSHOT SOUND EFFECT CHART Octal Register# Load Value Explanation Any not species 000 = Fe on Set Norse period to mid-value Rr 07 Enable Noise only on Channels A 8. om 020) 1 full amplitude range under direct i 920) Gaol of Emelone Geresaor Riz 020, At 020 Set Envelope perioa to 0 $86 seconas ans, (000 Select Envelope “decay’. one cycle only EXPLOSION SOUND EFFECT CHART octal fegaiers—Lone'vatn Espana Any netscaciag OD = ie 20 Set Nowe oenod to max wae m Sor Eman Noe ony on Gham ABC me GO| sete tt amotnuce range uecer mu 920} Shect connor ot Enatpe Genet a Gro Sat Emoione pana to 205 secant ms Boo Sete weeps “arcay one yt ony el 54 G.3 The Lese:. Whisting Bomb, Wolt Whistle, ana Race Car sounds ia Figs 30 inru 33 all utilize frequency sweeping effects. In all cases @ Frequency they invoive the increasing or decreasing of the values in the tone period registers with variable start, end, and time between frequency Sweep Effects Changes tor example. ine sweep speed o! he Laser 1s much more rapid than the high gear accelerate in tne race car. yet both use tne same computer routine with differing parameters Other easily achievable results include “doppler and noise sweep effects. The sweeping of the noise clocking register (A6) produces a “doppler” effect which seems well suited for “space war’ type games Fig. 30 LASER SOUND EFFECT CHART se Ocut Register ® Losd Value Explanation Any not specitied oo a7 076 ——_Enaole Tone only on Channel A ony AIO on ‘Select maximum amplitude on Channel A ‘Sweep ellect tor Channel A Tone penioe Ro 060 (stam) } via a processor loop witn approximately RO 160 jena} ) 3ms wan time between each step from 060 10 160 (0.479ms 2330-42 to? Oms: 100042, Ato ‘000 ‘Tuen off Channel A to ena souns effect Fig. 31 WHISTLING BOMB SOUND EFFECT CHART ——

    Você também pode gostar