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FEATURES
APPLICATIONS
Ultrasound and sonar time-gain controls
High performance audio and RF AGC systems
Signal measurement
GENERAL DESCRIPTION
The AD600/AD6021 dual-channel, low noise, variable gain
amplifiers are optimized for use in ultrasound imaging systems
but are applicable to any application requiring precise gain, low
noise and distortion, and wide bandwidth. Each independent
channel provides a gain of 0 dB to +40 dB in the AD600 and
10 dB to +30 dB in the AD602. The lower gain of the AD602
results in an improved signal-to-noise ratio (SNR) at the output.
However, both products have the same 1.4 nV/Hz input noise
spectral density. The decibel gain is directly proportional to the
control voltage, accurately calibrated, and supply and temperature stable.
To achieve the difficult performance objectives, a proprietary
circuit form, the X-AMP, was developed. Each channel of the
X-AMP comprises a variable attenuator of 0 dB to 42.14 dB
followed by a high speed fixed gain amplifier. In this way, the
amplifier never has to cope with large inputs and can benefit
from the use of negative feedback to precisely define the gain
and dynamics. The attenuator is realized as a 7-stage R-2R
ladder network having an input resistance of 100 , laser
trimmed to 2%. The attenuation between tap points is 6.02 dB;
the gain-control circuit provides continuous interpolation between
these taps. The resulting control function is linear in dB.
1
GAT1
SCALING
REFERENCE
PRECISION PASSIVE
INPUT ATTENUATOR
GATING
INTERFACE
C1HI
VG
A1OP
C1LO
A1CM
GAIN CONTROL
INTERFACE
0dB
12.04dB
6.02dB
18.06dB
22.08dB
36.12dB
30.1dB
42.14dB
A1HI
A1LO
500
62.5
RF2
2.24k (AD600)
694 (AD602)
RF1
20
FIXED-GAIN
AMPLIFIER
41.07dB (AD600)
31.07dB (AD602)
Patented.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
00538-001
AD600/AD602
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Specifications..................................................................................... 3
REVISION HISTORY
10/08Rev. E to Rev. F
Changes to Power Supply Parameter, Table 1 ............................... 3
Changes to Figure 41 ...................................................................... 20
Changes to Figure 45 ...................................................................... 21
Changes to Figure 47 ...................................................................... 22
Changes to Figure 51 ...................................................................... 24
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 29
5/02Rev. B to Rev. C
Changes to Specifications .................................................................2
Renumber Tables and TPCs ................................................... Global
8/01Rev. A to Rev. B
Changes to Accuracy Section of AD600A/AD602A column ......2
1/06Rev. D to Rev. E
Updated Format .................................................................. Universal
Changes to Table 2 ............................................................................ 5
Changes to The Gain-Control Interface Section ........................ 11
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
3/04Rev. C to Rev. D
Changes to Specifications ................................................................ 2
Changes to Ordering Guide ............................................................ 3
Changes to Figure 3 .......................................................................... 8
Changes to Figure 29 ...................................................................... 18
Updated Outline Dimensions ....................................................... 20
Rev. F | Page 2 of 32
AD600/AD602
SPECIFICATIONS
Each amplifier section at TA = 25C, VS = 5 V, 625 mV VG +625 mV, RL = 500 , and CL = 5 pF, unless otherwise noted.
Specifications for the AD600/AD602 are identical, unless otherwise noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Noise Spectral Density 2
Noise Figure
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
3 dB Bandwidth
Slew Rate
Peak Output 3
Output Impedance
Output Short-Circuit Current
Group Delay Change vs. Gain
Group Delay Change vs. Frequency
Total Harmonic Distortion
ACCURACY
AD600
Gain Error
Conditions
AD600J/AD602J 1
Min
Typ Max
98
RS = 50 , maximum gain
RS = 200 , maximum gain
f = 100 kHz
VOUT = 100 mV rms
RL 500
f 10 MHz
2.5
100
2
1.4
5.3
2
30
102
35
275
3
2
50
2
2
60
AD600A/AD602A1
Min
Typ Max
95
2.5
100
2
1.4
5.3
2
30
105
35
275
3
2
50
2
2
60
Unit
pF
nV/Hz
dB
dB
dB
MHz
V/s
V
mA
ns
ns
dBc
0 dB to 3 dB gain
3 dB to 37 dB gain
37 dB to 40 dB gain
VG = 625 mV to +625 mV
VG = 625 mV to +625 mV
0
0.5
1
+0.5
0.2
0.5
10
10
+1
+0.5
0
50
50
0.5
1.0
1.5
+0.5
0.2
0.5
10
10
+1.5
+1.0
+0.5
65
65
dB
dB
dB
mV
mV
10 dB to 7 dB gain
7 dB to +27 dB gain
27 dB to 30 dB gain
VG = 625 mV to +625 mV
VG = 625 mV to +625 mV
0
0.5
1
+0.5
0.2
0.5
5
5
+1
+0.5
0
30
30
0.5
1.0
1.5
+0.5
0.2
0.5
10
10
+1.5
+1.0
+0.5
45
45
dB
dB
dB
mV
mV
+3 dB to +37 dB (AD600);
7 dB to +27 dB (AD602)
31.7
32
32.3
30.5
32
33.5
dB/V
+2.5
1
50
0.75
+2.5
1
50
V
A
nA
M
dB/s
0.75
Rev. F | Page 3 of 32
0.35
10
15
40
0.35
10
15
40
AD600/AD602
Parameter
SIGNAL GATING INTERFACE
Logic Input Low (Output On)
Logic Input High (Output Off )
Response Time
Input Resistance
Output Gated Off
Output Offset Voltage
Output Noise Spectral Density
Signal Feedthrough @ 1 MHz
AD600
AD602
POWER SUPPLY
Specified Operating Range
Quiescent Current
AD600J/AD602J 1
Min
Typ Max
Conditions
AD600A/AD602A1
Min
Typ Max
0.8
2.4
On to off, off to on
Pin 4 to Pin 3; Pin 5 to Pin 6
10
65
4.75
11
V
V
s
k
400
mV
nV/Hz
0.3
30
10
65
100
80
70
Each channel
0.8
2.4
0.3
30
80
70
5.25
12.5
4.75
11
Unit
dB
dB
5.25
14
V
mA
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All
minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units.
2
Typical open- or short-circuited input; noise is lower when the system is set to maximum gain and the input is short-circuited. This figure includes the effects of both
voltage and current noise sources.
3
With an additional 1 k pull-down resistor, if RL < 500 .
4
The dc gain of the main amplifier in the AD600 is 113; therefore, an input offset of only 100 V becomes an 11.3 mV output offset. In the AD602, the amplifier gain is
35.7; therefore, an input offset of 100 V becomes a 3.57 mV output offset.
Rev. F | Page 4 of 32
AD600/AD602
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VS
Input Voltages
Pin 1, Pin 8, Pin 9, Pin 16
Pin 2, Pin 3, Pin 6, Pin 7
Pin 4, Pin 5
Internal Power Dissipation
Operating Temperature Range
J Grade
A Grade
S Grade
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
JA
16-Lead PDIP
16-Lead SOIC
16-Lead CERDIP
Rating
7.5 V
VS
2 V continuous
VS for 10 ms
VS
600 mW
ESD CAUTION
0C to 70C
40C to +85C
55C to +125C
65C to +150C
300C
85C/W
100C/W
120C/W
Rev. F | Page 5 of 32
AD600/AD602
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
C1LO
A1HI
A1LO
GAT1
16 C1HI
+
15 A1CM
A1
14 A1OP
13 VPOS
REF
GAT2
A2LO
12 VNEG
11 A2OP
A2
C2LO
10 A2CM
AD600 /
AD602
C2HI
00538-002
A2HI
Mnemonic
C1LO
A1HI
A1LO
GAT1
GAT2
A2LO
A2HI
C2LO
C2HI
A2CM
A2OP
VNEG
VPOS
A1OP
A1CM
C1HI
Description
CH1 Gain-Control Input Low. Positive voltage reduces CH1 gain.
CH1 Signal Input High. Positive voltage increases CH1 output.
CH1 Signal Input Low. Usually connected to CH1 input ground.
CH1 Gating Input. A logic high shuts off the CH1 signal path.
CH2 Gating Input. A logic high shuts off the CH2 signal path.
CH2 Signal Input Low. Usually connected to CH2 input ground.
CH2 Signal Input High. Positive voltage increases CH2 output.
CH2 Gain-Control Input Low. Positive voltage reduces CH2 gain.
CH2 Gain-Control Input High. Positive voltage increases CH2 gain.
CH2 Common. Usually connected to CH2 output ground.
CH2 Output.
Negative Supply for Both Amplifiers.
Positive Supply for Both Amplifiers.
CH1 Output.
CH1 Common. Usually connected to CH1 output ground.
CH1 Gain-Control Input High. Positive voltage increases CH1 gain.
Rev. F | Page 6 of 32
AD600/AD602
TYPICAL PERFORMANCE CHARACTERISTICS
0.45
10.0
0.35
9.8
9.6
0.15
0.05
0.05
0.15
0.25
9.2
9.0
8.8
8.6
00538-003
8.4
0.35
0.45
0.7
9.4
0.5
0.3
0.1
0.1
0.3
GAIN CONTROL VOLTAGE (V)
0.5
00538-006
0.25
8.2
8.0
0.7
0.7
0.5
0.3
0.1
0.1
0.3
GAIN CONTROL VOLTAGE (V)
0.5
0.7
VG = 0V
10dB/DIV
CENTER
FREQ 1MHz
10kHz/DIV
20dB
17dB
0
45
100k
1M
10M
FREQUENCY (Hz)
00538-007
00538-004
90
100M
10dB
7dB
0
45
00538-005
90
100k
1M
10M
FREQUENCY (Hz)
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
100M
00538-008
1.0
50
100
200
500
1000
LOAD RESISTANCE ()
2000
Rev. F | Page 7 of 32
AD600/AD602
102
101
50mV
GAIN = 40dB
OUTPUT
100
99
GAIN = 20dB
98
97
90
GAIN = 0dB
96
10
0%
00538-009
94
93
92
100k
1M
10M
FREQUENCY (Hz)
5V
100ns
00538-012
95
INPUT
INPUT IMPEDANCE ()
100
100M
50mV
100
AD600
OUTPUT
90
3
2
AD602
1
0
2
3
4
0.7
0.5
0.3
0.1
0.1
0.3
GAIN CONTROL VOLTAGE (V)
0.5
5V
1V VOUT
100ns
0.7
1s
1V
100
100
90
90
OUTPUT
OUTPUT
10
10
Figure 11. Gain Control Channel Response Time. Top: Output Voltage, 2 V
Maximum, Bottom: Gain Control Voltage VC = 625 mV
Rev. F | Page 8 of 32
0%
100mV
500ns
00538-014
1V VC
INPUT
0%
00538-011
INPUT
10
0%
00538-013
INPUT
00538-010
AD600/AD602
10
AD600: G = 20dB
AD602: G = 10dB
BOTH: VCM = 100mV rms
VS = 5V
RL = 500
TA = 25C
5
0
100
90
5
CMRR (dB)
10
AD600
15
20
25
10
0%
30
200ns
AD602
00538-015
1V
00538-018
INPUT
OUTPUT
500mV
35
40
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
100
90
20
30
AD602
AD600: G = 40dB
AD602: G = 30dB
BOTH: RL = 500
VIN = 0V
RS = 50
60
200mV
500ns
70
80
100k
1M
10M
FREQUENCY (Hz)
00538-019
40
50
10
0%
00538-016
INPUT
AD600
10
PSRR (dB)
OUTPUT
1V
100M
500mV
0
10
100
CROSSTALK (dB)
20
30
40
AD600
50
60
10
0%
70
500ns
AD602
00538-020
1V
00538-017
INPUT
OUTPUT
90
80
90
100k
1M
10M
FREQUENCY (Hz)
Rev. F | Page 9 of 32
100M
AD600/AD602
THEORY OF OPERATION
The signal applied at the input of the ladder network is
attenuated by 6.02 dB by each section; thus, the attenuation to
each of the taps is progressively 0 dB, 6.02 dB, 12.04 dB, 18.06 dB,
24.08 dB, 30.1 dB, 36.12 dB, and 42.14 dB. A unique circuit
technique is employed to interpolate between these tap points,
indicated by the slider in Figure 21, providing continuous
attenuation from 0 dB to 42.14 dB.
Note that the signal inputs are not fully differential. A1LO, A1CM
(for CH1), A2LO, and A2CM (for CH2) provide separate access
to the input and output grounds. This recognizes that, even when
using a ground plane, small differences arise in the voltages at
these nodes. It is important that A1LO and A2LO be connected
directly to the input ground(s). Significant impedance in these
connections reduces the gain accuracy. A1CM and A2CM
should be connected to the load ground(s).
NOISE PERFORMANCE
GAT1
SCALING
REFERENCE
PRECISION PASSIVE
INPUT ATTENUATOR
GATING
INTERFACE
C1HI
VG
A1OP
GAIN CONTROL
INTERFACE
A1CM
C1LO
12.04dB
6.02dB
18.06dB
22.08dB
36.12dB
30.1dB
42.14dB
A1HI
A1LO
500
62.5
RF2
2.24k (AD600)
694 (AD602)
RF1
20
FIXED-GAIN
AMPLIFIER
41.07dB (AD600)
31.07dB (AD602)
00538-021
0dB
Rev. F | Page 10 of 32
AD600/AD602
It is apparent from the foregoing that it is essential to use a low
resistance in the design of the ladder network to achieve low
noise. In some applications, this can be inconvenient, requiring
the use of an external buffer or preamplifier. However, very few
amplifiers combine the needed low noise with low distortion at
maximum input levels, and the power consumption required to
achieve this performance is quite high (due to the need to
maintain very low resistance values while also coping with large
inputs). On the other hand, there is little value in providing a
buffer with high input impedance because the usual reason for
thisthe minimization of loading of a high resistance source
is not compatible with low noise.
Apart from the small variations just mentioned, the SNR at the
output is essentially independent of the attenuator setting,
because the maximum undistorted output is 1 V rms, and the
NSD at the output of the AD600 is fixed at 113 114 nV/Hz,
or 158 nV/Hz. Therefore, in a 1 MHz bandwidth, the output
SNR is 76 dB. The input NSD of the AD600/AD602 is the same
but, because of the 10 dB lower gain in the AD602s fixed
amplifier, its output SNR is 10 dB better, or 86 dB in a 1 MHz
bandwidth.
GAIN-CONTROL INTERFACE
The attenuation is controlled through a differential, high
impedance (15 M) input, with a scaling factor that is laser
trimmed to 32 dB per volt, that is, 31.25 mV/dB. Each of the
two amplifiers has its own control interface. An internal band
gap reference ensures stability of the scaling with respect to
supply and temperature variations and is the only circuitry
common to both channels.
When the differential input voltage VG = 0 V, the attenuator
slider is centered, providing an attenuation of +21.07 dB,
resulting in an overall gain of +20 dB (= 21.07 dB + +41.07 dB).
When the control input is 625 mV, the gain is lowered by
+20 dB (= +0.625 +32) to 0 dB; when set to +625 mV, the
gain is increased by +20 dB to +40 dB. When this interface is
overdriven in either direction, the gain approaches either
1.07 dB (= 42.14 dB + +41.07 dB) or +41.07 dB (= 0 +
+41.07 dB), respectively.
The gain of the AD600 can be calculated by
Gain (dB) = 32 VG + 20
(1)
where VG is in volts.
For the AD602, the expression is
Gain (dB) = 32 VG + 10
(2)
SIGNAL-GATING INPUTS
Each amplifier section of the AD600/AD602 is equipped with a
signal-gating function, controlled by a TTL or CMOS logic
input (GAT1 or GAT2). The ground references for these inputs
are the signal input grounds A1LO and A2LO, respectively.
Operation of the channel is unaffected when this input is LO or
left open-circuited. Signal transmission is blocked when this
input is HI. The dc output level of the channel is set to within a
few millivolts of the output ground (A1CM or A2CM), and
simultaneously the noise level drops significantly. The reduction
in noise and spurious signal feedthrough is useful in ultrasound
beam-forming applications, where many amplifier outputs are
summed.
COMMON-MODE REJECTION
A special circuit technique provides rejection of voltages
appearing between input grounds (A1LO and A2LO) and
output grounds (A1CM and A2CM). This is necessary because
of the op amp form of the amplifier, as shown in Figure 21.
The feedback voltage is developed across the RF1 resistor
(which, to achieve low noise, has a value of only 20 ). The
voltage developed across this resistor is referenced to the input
common, so the output voltage is also referred to that node.
For zero differential signal input between A1HI and A1LO, the
output A1OP simply follows the voltage at A1CM. Note that the
range of voltage differences that can exist between A1LO and
A1CM (or A2LO and A2CM) is limited to about 100 mV.
Figure 18 shows the typical common-mode rejection ratio vs.
frequency.
Rev. F | Page 11 of 32
AD600/AD602
85
80
75
70
SNR (dB)
65
60
55
50
45
00538-022
40
35
30
0.5
0.5
1.0
1.5
2.0
2.5
3.0
VG
Figure 22. SNR vs. Control Voltage Sequential Control (1 MHz Bandwidth)
A2
A1
40.00dB
40.00dB
C1HI
41.07dB
42.14dB
1.07dB
C1LO
C2HI
VG1
VG2
VO1 = 0.592V
VC = 0V
41.07dB
C2LO
OUTPUT
0dB
00538-023
INPUT
0dB
41.07dB
VO2 = 1.908V
Figure 23. AD600 Gain Control Input Calculations for Sequential Control Operation (A)
A2
A1
0.51dB
0.51dB
C1HI
41.07dB
41.63dB
40.56dB
C2HI
C1LO
41.07dB
C2LO
VG2
VG1
VO1 = 0.592V
VO2 = 1.908V
VC = 1.25V
OUTPUT
40dB
00538-055
INPUT
0dB
1.07dB
Figure 24. AD600 Gain Control Input Calculations for Sequential Control Operation (B)
A2
A1
0dB
0dB
C1HI
41.07dB
C1LO
2.14dB
41.07dB
C2HI
VG2
VG1
VC = 2.5V
41.07dB
C2LO
VO1 = 0.592V
VO2 = 1.908V
Figure 25. AD600 Gain Control Input Calculations for Sequential Control Operation (C)
Rev. F | Page 12 of 32
OUTPUT
80dB
00538-056
INPUT
0dB
38.93dB
AD600/AD602
The gains are offset such that the gain of A2 is increased only
after the gain of A1 has reached its maximum value (see Figure 26).
Note that, for a differential input of 700 mV or less, the gain of
a single amplifier (A1 or A2) is at its minimum value of 1.07 dB;
for a differential input of +700 mV or more, the gain is at its
maximum value of +41.07 dB. Control inputs beyond these
limits do not affect the gain and can be tolerated without damage or
foldover in the response. See the Specifications section for more
details on the allowable voltage range. The gain is now
Gain (dB) = 32 VC
(3)
+1.07dB
0.56dB
+38.93dB
A2
+20dB
*
1.07dB
GAIN
2.14
(dB)
0.625
20
1.908
1.25
40
1.875
60
2.5
80
VC (V)
82.14
00538-024
0.592
0
0
+41.07dB
A1
Rev. F | Page 13 of 32
90
75
80
70
70
65
60
60
50
SNR (dB)
40
A1
55
50
30
COMBINED
45
A2
20
40
10
10
0.5
35
00538-025
0
0
0.5
1.0
1.5
2.0
2.5
00538-028
AD600/AD602
30
0
3.0
0.2
0.4
0.6
1.0
0.8
1.2
1.4
0.6
0
1
2
3
4
0.4
0.2
0.0
0.2
0.4
0.6
0.8
7
0
0.5
1.0
1.5
2.0
2.5
00538-029
00538-026
1.0
8
0.5
0.8
VC
VC
1.0
1.2
3.0
VC
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VC
1.3
80
75
70
65
SNR (dB)
1
0
1
2
60
55
50
5
6
0.1
0.2
0.4
0.6
0.8
1.0
00538-030
45
4
00538-027
40
35
1.2
0.2
0.4
0.6
0.8
1.0
1.2
VC
VC
Rev. F | Page 14 of 32
1.4
AD600/AD602
APPLICATIONS INFORMATION
+625mV
0dB
VOLTAGE-OUTPUT
DAC
40dB
VG
A1
GAIN
C1LO
625mV
A1HI
A1LO
GAT1
1
2
3
16
15
A1
A1OP
13
REF
5
A2LO
A2HI
C2LO
A1CM
14
GAT2
C1HI
12
VPOS
VNEG
+5V
5V
11 A2OP
A2
10 A2CM
AD600 OR
AD602
C2HI
00538-031
CONTROL VOLTAGE,
VG
Figure 33. The Simplest Application of the X-AMP Is as a TGC or TVG Amplifier
in Ultrasound or Sonar (Only A1 Connections Shown for Simplicity)
C1LO
VIN
A1HI
A1LO
GAT1
1
2
3
16
+
15
A1
A1OP
13
REF
5
A2LO
A2HI
C2LO
A1CM
14
GAT2
C1HI
12
VPOS
+5V
1k
VNEG
5V
11 A2OP
ADDED
PULL-DOWN
RESISTOR
A2
10 A2CM
AD600/
AD602
C2HI
Rev. F | Page 15 of 32
00538-032
AD600/AD602
REALIZING OTHER GAIN RANGES
+5V
R1
49.9
1F
R2
174
Q1
MRF904
R3
562
1F
VIN
R5
42.2
0.1F
5V
INPUT
GROUND
+5V
0.1F
R6
562
1F
Q2
MM4049
R7
174
GAIN-CONTROL
VOLTAGE
VG
+
100
RIN OF X-AMP
OUTPUT
GROUND
1F
R8
49.9
5V
A1HI
A1LO
GAT1
VIN
GAT2
A2LO
A2HI
C2LO
16
C1HI
A1CM
2
3
15
A1
14
13
REF
12
11
A2
100
A1OP
10
AD600 OR
AD602
VPOS
VNEG
A2OP
VOUT
+5V
5V
50
100
A2CM
C2HI
00538-033
C1LO
00538-034
R4
42.2
Rev. F | Page 16 of 32
AD600/AD602
This is a Class AB amplifier. As VIN increases in a positive
direction, Q1 conducts more heavily and its re becomes lower
while Q2 increases. Conversely, increasingly negative values of
VIN result in the re of Q2 decreasing, while the re of Q1 increases.
The design is chosen such that the net emitter resistance is
essentially independent of the instantaneous value of VIN,
resulting in moderately low distortion. Low values of resistance
and moderately high bias currents are important in achieving
the low noise, wide bandwidth, and low distortion of this
preamplifier. Heavy decoupling prevents noise on the power
supply lines from being conveyed to the input of the X-AMP.
HD2
HD3
HD2
HD3
Value
6
250
1
Unit
dB
MHz
V p-p
0.27
0.14
0.44
0.58
1.03
%
%
%
%
nV/Hz
1.4
15
150
5
15
k
pF
A
V
mA
+5V
R3
46.4k
+5V
R4
3.74k
RF
INPUT
A1HI
16
A1CM
2
A1LO
3
15
A1
A1OP
13
REF
5
A2LO
A2HI
VPOS
VNEG
12
11
A2
7
C4
0.1F
R1
100
300A
(AT 300K)
+5V DEC
FB
5V DEC
C3
15pF
A2OP
R2 +
806 VPTAT
1%
FB
RF
OUTPUT
10
C2HI
9
0.1F
C1
100pF
5V DEC
0.1F
+5V DEC
Q1
2N3904
A2CM
C2LO
+5V
C2
1F
14
GAT1
GAT2
AD590
C1HI
5V
POWER SUPPLY
DECOUPLING NETWORK
00538-035
C1LO
V G
AD600
Figure 37. This Accurate HF AGC Amplifier Uses Three Active Components
Rev. F | Page 17 of 32
AD600/AD602
Because the average emitter current is 600 A during each halfcycle of the square wave, a resistor of 833 would add a PTAT
voltage of 500 mV at 300 K, increasing by 1.66 mV/C. In
practice, the optimum value of R2 depends on the transistor
used and, to a lesser extent, on the waveform for which the
temperature stability is to be optimized; for the devices shown
and sine wave signals, the recommended value is 806 . This
resistor also serves to lower the peak current in Q1, and the
200 Hz LP filter it forms with C2 helps to minimize distortion
due to ripple in VG. Note that the output amplitude under sine
wave conditions is higher than for a square wave because the
average value of the current for an ideal rectifier would be
0.637 times as large, causing the output amplitude to be 1.88 V
(= 1.2/0.637), or 1.33 V rms. In practice, the somewhat nonideal
rectifier results in the sine wave output being regulated to about
1.275 V rms.
Rev. F | Page 18 of 32
3dB
00538-036
0.1
1
10
FREQUENCY (MHz)
100
+0.2
100kHz
0
1MHz
0.2
10MHz
0.4
00538-037
AD600/AD602
0.001
0.01
0.1
INPUT AMPLITUDE (V rms)
While the band gap principle used here sets the output
amplitude to 1.2 V (for the square wave case), the stabilization
point can be set to any higher amplitude, up to the maximum
output of (VS 2) V that the AD600 can support. It is only
necessary to split R2 into two components of appropriate ratio
whose parallel sum remains close to the zero-TC value of
806 . Figure 40 shows this and how the output can be raised
without altering the temperature stability.
5V
AD590
300A
(AT 300K)
C2
1F
Q1
2N3904
R2B
+
VPTAT R2 = R2A || R2B 806
RF
OUTPUT
00538-038
TO AD600 PIN 11
R2A
(4)
VREF
TO AD600 PIN 16
C3
15pF
V IN (rms )
Rev. F | Page 19 of 32
AD600/AD602
Vrms
AF/RF
OUTPUT
C1
0.1F
C4
4.7F
+6V DEC
INPUT
1V rms
MAX
(SINE WAVE)
R1
115
C1LO
A1HI
R2 200
A1LO
GAT1
R3
133k
U3A
1/2
AD712
VG
15.625mV/dB
GAT2
A2LO
A2HI
C2LO
R4
3.01k
+6V
1
2
3
16
15
A1
14
13
REF
5
6
12
11
A2
7
8
C1HI
A1CM
6V
DEC
VPOS
+6V
DEC
VNEG
6V
DEC
C2
2F
U1
AD600
NC 12
4 CAV
NC 11
COM 10
RL 9
6 BUF OUT
A2CM
9
3 VS
5 dB
7 BUF IN
10
FB
U2
2 NC
AD636 NC 13
A1OP
A2OP
+VS 14
1 VIN
0.1F
R7
56.2k
+6V
DEC
0.1F
6V
DEC
R6
3.16k
FB
+316.2mV
IOUT 8
C2HI
1/2
AD712
U3B
C3
1F
6V
POWER SUPPLY
DECOUPLING
NETWORK
VOUT
+100mV/dB
0V = 0dB (AT 10mV rms)
R5
16.2k
00538-039
CAL
0dB
NC = NO CONNECT
Figure 41. The Output of This Three-IC Circuit Is Proportional to the Decibel Value of the rms Input
325
300
275
250
225
00538-040
200
175
150
10
100
1m
10m
100m
INPUT SIGNAL (V rms)
10
Rev. F | Page 20 of 32
AD600/AD602
This ripple can be canceled whenever the X-AMP stages are
cascaded by introducing a 3 dB offset between the two pairs of
control voltages. A simple means to achieve this is shown in
Figure 45: the voltages at C1HI and C2HI are split by 46.875 mV,
or 1.5 dB. Alternatively, either one of these pins can be offset
by 3 dB and a 1.5 dB gain adjustment made at the input
attenuator (R1 + R2).
C1HI
16
15
U1
AD600
1 VIN
A1CM
14 A1OP
VPOS
13
VNEG
12
A2OP
11
A2CM
10
C2HI
9
2 NC
+6V DEC
6V DEC
1
2
00538-041
3
4
100
1m
10m
100m
INPUT SIGNAL (V rms)
10
Figure 43. The Decibel Output of the Circuit in Figure 41 Is Linear over an
80 dB Range
2.5
2.0
1.5
OUTPUT ERROR (dB)
2.0
1.5
1.0
0.5
0
0.5
1.0
0.5
0
0.5
1.0
1.0
1.5
1.5
2.0
00538-042
3dB OFFSET
MODIFICATION
2.5
2.0
2.5
10
78.7 78.7
5
10
10k
NC = NO CONNECT
+46.875mV
+6V
DEC
10k
100
1m
10m
100m
INPUT SIGNAL (V rms)
2.5
10
10
00538-044
VOUT (V)
NC 5 dB
7 BUF IN
46.875mV
6V
DEC
U2
AD636
4 CAV
C2
2F
NC 6 BUF OUT
4
3
3 VS
6V DEC
00538-043
100
1m
10m
100m
INPUT SIGNAL (V rms)
10
Rev. F | Page 21 of 32
AD600/AD602
A1HI
A1LO
GAT1
GAT2
A2LO
A2HI
C2LO
1
2
3
16
15
A1
14
13
REF
5
6
12
11
A2
10
C1LO
C1HI
A1CM
C1
0.1F
A1OP
VPOS
VNEG
A2OP
+5V
DEC
5V
DEC
R1
133k
C2
0.1F
R4
133k
A2CM
R2
487
A1HI
U3A
A1LO
R3
200
1/4
AD713
GAT1
GAT2
R5
1.58k
A2LO
U3B
C3
220pF
A2HI
1/4
AD713
C2HI
C2LO
1
2
3
16
2dB
62.5mV
0dB
+2dB
+62.5mV
R8
127
R9
10k
5V
FB
14
13
REF
5
6
12
10
A1OP
VPOS
VNEG
C4
2F
VOUT
+5V
DEC
5V
DEC
11 A2OP
A2
A1CM
U2 AD600
A2CM
C2HI
+5V
R6
10k
0.1F
A1
U1 AD600
+5V
15
C1HI
R7
127
+5V
DEC
C5
22F
0.1F
5V
DEC
+5V DEC
FB
5V
POWER SUPPLY
DECOUPLING
NETWORK
R14
301k
Q1
2N3906
5V
DEC
+5V DEC
R15
19.6k
R16
6.65k
+VS 14
VIN U4
AD636
NC
NC 13
VS
NC 12
CAV
NC 11
dB
BUF OUT
BUF IN
R11
46.4k
R10
3.16k
COM 10
C6
4.7F
RL 9
U3C
IOUT 8
R12
11.3k
+316.2mV
R13
3.01k
VLOG
1/4
AD713
00538-045
C1LO
INPUT
1V rms
MAX
(SINE WAVE)
NC = NO CONNECT
Figure 47. RMS Responding AGC Circuit with 100 dB Dynamic Range
2
1
0
1
2
00538-046
3
4
5
1
10
100
1m
10m
100m
10
Figure 48. VLOG Plotted vs. VIN for Figure 47s Circuit Showing 120 dB AGC Range
Rev. F | Page 22 of 32
AD600/AD602
2.0
1.5
1.0
0.5
0.1
0
0.1
0.5
1.0
2.0
1
00538-047
1.5
10
100
1m
10m
100m
INPUT SIGNAL (V rms)
10
Figure 49. Gain Error for Figure 41 Without the 2 dB Offset Modification
2.0
1.5
1.0
0.5
0.1
0
0.1
0.5
1.0
00538-048
1.5
2.0
1
In this case, the gains of all three VCA sections are varied
simultaneously, so the scaling is not 32 dB/V but 96 dB/V or
10.42 mV/dB. The fraction of VLOG required to set its scaling to
50 mV/dB is therefore 10.42/50 or 0.208. The resulting fullscale range of VLOG is nominally 2.5 V. This scaling allows the
circuit to operate from 5 V supplies.
10
100
1m
10m
100m
INPUT SIGNAL (V rms)
10
Rev. F | Page 23 of 32
AD600/AD602
read 0 dB when VIN is 3.16 mV rms and to center the 100 dB
range between 10 V rms and 1 V rms input. R5 and C3
provide a 3 dB noise bandwidth of 30 kHz. R12 to R15 change
the scaling from 625 mV/decade at the control inputs to
1 V/decade at the output. At the same time, R12 to R15 center
the dynamic range at 60 dB, which occurs if the VG of U1B is
equal to 0. These arrangements ensure that the VLOG still fits
within the 6 V supplies.
R3
R17 200
115
A1HI
A1LO
GAT1
GAT2
A2LO
A2HI
C2LO
1
2
3
16
+
15
A1
14
13
REF
12
11
A2
10
C1LO
C1HI
A1CM
C1
0.1F
A1OP
VPOS
VNEG
A2OP
R2
100
U3A
R1
+6V
DEC 133k
C2
6V
R5
DEC 0.1F 5.36k
R4
133k
A2CM
A1HI
A1LO
1/4
AD713
GAT1
GAT2
A2LO
U3B
C3
0.001F
A2HI
1/4
AD713
C2HI
C2LO
U1 AD600
R6
3.4k
R7
R8
1k 294
1
2
3
16
15
13
REF
12
VPOS
VNEG
C4
2F
VOUT
+5V
DEC
5V
DEC
11 A2OP
A2
A1OP
14
A1CM
A1
C1HI
10
9
U2 AD600
A2CM
C2HI
R9 R16
1k 287
+6V
+6V
C5
22F
FB
+6V DEC
0.1F
+6V
DEC
0.1F
6V
DEC
VIN
+VS 14
U4 NC
2 NC
13
AD636
6V
DEC
FB
6V
POWER SUPPLY
DECOUPLING
NETWORK
VS
NC 12
CAV
NC 11
NC
dB
NC
BUF OUT
BUF IN
R10
3.16k
COM 10
C6
4.7F
RL 9
U3C
+6V DEC
R15
5.11k
R11
56.2k
R13
866
R12
1k
IOUT 8
+316.2mV
R14
7.32k
NC = NO CONNECT
Figure 51. 120 dB Dynamic Range RMS Responding Circuit Optimized for SNR
Rev. F | Page 24 of 32
VLOG
1/4
AD713
00538-049
INPUT
AD600/AD602
5
400
350
2
GAIN ERROR (mV)
1
0
1
2
300
00538-050
4
5
1
10
100
1m
10m
100m
200
10
00538-052
250
10
100
10m
100m
10
90
VC SCALE = 10.417mV/dB
80
70
SNR (dB)
60
50
40
30
20
10
0
833.2 625.0 416.6 208.3
208.3
416.6
625.0
833.2
VC (mV)
Figure 55. SNR vs. Control Voltage for Parallel Gain Control (See Figure 47)
In contrast, the SNR for the sequential mode is shown in Figure 56.
U1A always acts as a fixed noise source; varying its gain has no
influence on the output noise. This is a feature of the X-AMP
technique. Therefore, for the first 40 dB of control range
(actually slightly more, as is explained later), when only this
VCA section has its gain varied, the SNR remains constant.
During this time, the gains of U1B and U2A are at their
minimum value of 1.07 dB.
1.0
90
0.5
80
VC SCALE = 31.25mV/dB
0.2
0
0.2
70
60
SNR (dB)
0.5
1.0
1.5
2.0
1
00538-051
10
100
1m
10m
100m
50
40
30
20
10
00538-054
1m
00538-053
10
0
1.183 0.558
0.067
0.692
1.317
1.942
2.567
3.192
3.817
VC (V)
Figure 56. SNR vs. Control Voltage for Sequential Gain Control (See Figure 51)
Rev. F | Page 25 of 32
AD600/AD602
For the next 40 dB of control range, the gain of U1A remains
fixed at its maximum value of 41.07 dB and only the gain of
U1B is varied, while that of U2A remains at its minimum value
of 1.07 dB. In this interval, the fixed output noise of U1A is
amplified by the increasing gain of U1B, and the SNR
progressively decreases.
Once U1B reaches its maximum gain of 41.07 dB, its output
also becomes a gain-independent noise source; this noise is
presented to U2A. As the control voltage is further increased,
the gains of both U1A and U1B remain fixed at their maximum
value of 41.07 dB, and the SNR continues to decrease. Figure 56
clearly shows this because the maximum SNR of 90 dB is
extended for the first 40 dB of input signal before it starts to roll off.
Rev. F | Page 26 of 32
AD600/AD602
OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
16
PIN 1
0.310 (7.87)
0.220 (5.59)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
0.070 (1.78) PLANE
0.030 (0.76)
15
0
0.015 (0.38)
0.008 (0.20)
Rev. F | Page 27 of 32
073106-B
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
AD600/AD602
10.50 (0.4134)
10.10 (0.3976)
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
45
8
0
0.33 (0.0130)
0.20 (0.0079)
Rev. F | Page 28 of 32
1.27 (0.0500)
0.40 (0.0157)
032707-B
AD600/AD602
ORDERING GUIDE
Model
AD600AQ
AD600AR
AD600AR-REEL
AD600AR-REEL7
AD600ARZ 1
AD600ARZ-R71
AD600ARZ-RL1
AD600JN
AD600JNZ1
AD600JR
AD600JR-REEL
AD600JR-REEL7
AD600JRZ1
AD600JRZ-R71
AD600JRZ-RL1
AD600SQ/883B 2
AD602AQ
AD602AR
AD602AR-REEL
AD602AR-REEL7
AD602ARZ1
AD602ARZ-R71
AD602ARZ-RL1
AD602JCHIPS
AD602JN
AD602JNZ1
AD602JR
AD602JR-REEL
AD602JR-REEL7
AD602JRZ1
AD602JRZ-R71
AD602JRZ-RL1
AD602SQ/883B 3
Gain Range
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
0 dB to 40 dB
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
Temperature Range
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
55C to +125C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
10 dB to +30 dB
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
55C to +125C
Rev. F | Page 29 of 32
Package Description
16-Lead CERDIP
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead PDIP
16-Lead PDIP
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead CERDIP
16-Lead CERDIP
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
DIE
16-Lead PDIP
16-Lead PDIP
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead CERDIP
Package Option
Q-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
N-16
N-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
Q-16
Q-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
N-16
N-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
Q-16
AD600/AD602
NOTES
Rev. F | Page 30 of 32
AD600/AD602
NOTES
Rev. F | Page 31 of 32
AD600/AD602
NOTES
Rev. F | Page 32 of 32