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9.

5 RON, 16-Channel, Differential 8-Channel,


15 V/+12 V/5 V iCMOS Multiplexers

ADG1406/ADG1407

APPLICATIONS
Medical equipment
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems

GENERAL DESCRIPTION
The ADG1406 and ADG1407 are monolithic iCMOS analog
multiplexers comprising 16 single channels and eight differential
channels, respectively. The ADG1406 switches one of 16 inputs
to a common output, as determined by the 4-bit binary address
lines (A0, A1, A2, and A3). The ADG1407 switches one of eight
differential inputs to a common differential output, as determined
by the 3-bit binary address lines (A0, A1, and A2). An EN input
on both devices enables or disables the device. When disabled,
all channels switch off. When on, each channel conducts equally
well in both directions and has an input signal range that extends
to the supplies.
The iCMOS (industrial CMOS) modular manufacturing
process combines high voltage CMOS (complementary metaloxide semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced
package size.

FUNCTIONAL BLOCK DIAGRAMS


ADG1406
S1

S16
1-OF-16
DECODER

A0 A1 A2 A3 EN

07419-001

9.5 on resistance @ 25C


Up to 300 mA of continuous current
Fully specified at 15 V/+12 V/5 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
28-lead TSSOP and 32-lead, 5 mm 5 mm LFCSP_VQ

Figure 1.

ADG1407
S1A
DA
S8A

S1B
DB
S8B
1-OF-8
DECODER

A0 A1 A2 EN

07419-002

FEATURES

Figure 2.

Table 1. Related Devices


Part No.
ADG1206/ADG1207

Description
Low capacitance, low charge injection,
and low leakage 8-/16-channel 15 V
multiplexers

The ultralow on resistance and on-resistance flatness of these


switches make them ideal solutions for data acquisition and
gain switching applications where low distortion is critical.
iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and batterypowered instruments.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.


Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 20082009 Analog Devices, Inc. All rights reserved.

ADG1406/ADG1407
TABLE OF CONTENTS
Features .............................................................................................. 1

Absolute Maximum Ratings ............................................................8

Applications ....................................................................................... 1

Thermal Resistance .......................................................................8

General Description ......................................................................... 1

ESD Caution...................................................................................8

Functional Block Diagrams ............................................................. 1

Pin Configurations and Function Descriptions ............................9

Revision History ............................................................................... 2

Typical Performance Characteristics ........................................... 13

Specifications..................................................................................... 3

Terminology .................................................................................... 17

15 V Dual Supply ....................................................................... 3

Test Circuits ..................................................................................... 18

12 V Single Supply ........................................................................ 4

Outline Dimensions ....................................................................... 20

5 V Dual Supply ......................................................................... 6

Ordering Guide .......................................................................... 20

Continuous Current per Channel .............................................. 7

REVISION HISTORY
3/09Rev. 0 to Rev. A
Change to IDD Parameter, Table 2 ................................................... 4
Change to IDD Parameter, Table 3 ................................................... 5
Changes to Figure 16 ...................................................................... 14
8/08Revision 0: Initial Version

Rev. A | Page 2 of 20

ADG1406/ADG1407
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V 10%, VSS = 15 V 10%, GND = 0 V, unless otherwise noted. 1
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match Between
Channels (RON)
On-Resistance Flatness (RFLAT(ON))

+25C

40C to
+85C

VSS to VDD
9.5
11.5
0.55
1
1.6
1.9

14

16

1.5

1.7

2.15

2.3

LEAKAGE CURRENTS
Source Off Leakage, IS (Off )

0.01
0.25
0.01

Drain Off Leakage, ID (Off )

0.5
0.05
0.5

Channel On Leakage, ID, IS (On)


DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current

40C to
+125C1

Break-Before-Make Time Delay, tBBM

nA max
nA typ

VS = 10 V, VD = 10 V; see Figure 28

20

VS = VD = 10 V; see Figure 29

20

nA max
nA typ
nA max
V min
V max
A typ
A max
pF typ

VIN = VGND or VDD

0.002
3

200

225
10

tON (EN)
tOFF (EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion (THD + N)
3 dB Bandwidth
ADG1406
ADG1407
Insertion Loss
CS (Off )
CD (Off )
ADG1406
ADG1407

83
110
98
120
10
73
70
0.07

VDD = +13.5 V, VSS = 13.5 V, VS = 10 V,


IS = 10 mA; see Figure 27
VDD = +13.5 V, VSS = 13.5 V , VS = 10 V, IS =
10 mA
VDD = +13.5 V, VSS = 13.5 V, VS = 10 V, IS =
10 mA
VDD = +16.5 V, VSS = 16.5 V
VS = 10 V, VD = 10 V; see Figure 28

2.0
0.8

105
160
40

V
typ
max
typ
max
typ
max

Test Conditions/Comments

nA typ

0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANSITION

Unit

140

155

145

165

ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ

RL = 100 , CL = 35 pF
VS = 10 V, see Figure 30
RL = 100 , CL = 35 pF
VS1 = VS2 = 10 V; see Figure 31
RL = 100 , CL = 35 pF
VS = 10 V; see Figure 32
RL = 100 , CL = 35 pF
VS = 10 V; see Figure 32
VS = 0 V, RS = 0 , CL = 1 nF; see Figure 33
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 35
RL = 110 , 15 V p-p, f = 20 Hz to 20 kHz; see
Figure 37
RL = 50 , CL = 5 pF; see Figure 36

60
110
0.6
8

MHz typ
MHz typ
dB typ
pF typ

RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 36


f = 1 MHz

90
45

pF typ
pF typ

f = 1 MHz
f = 1 MHz

Rev. A | Page 3 of 20

ADG1406/ADG1407
Parameter
CD, CS (On)
ADG1406
ADG1407
POWER REQUIREMENTS
IDD

+25C

40C to
+85C

40C to
+125C1

115
70
0.002
1

IDD

280
475

ISS

0.002
1
4.5/16.5

VDD/VSS
1
2

Unit

Test Conditions/Comments

pF typ
pF typ

f = 1 MHz
f = 1 MHz
VDD = +16.5 V, VSS = 16.5 V
Digital inputs = 0 V or VDD

A typ
A max
A typ
A max
A typ
A max
V min/max

Digital inputs = 5 V
Digital inputs = 0 V, 5 V or VDD

Temperature range for B version is 40C to +125C.


Guaranteed by design, not subject to production test.

12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match Between
Channels (RON)
On-Resistance Flatness (RFLAT(ON))

+25C

40C to
+85C

40C to
+125C 1
0 to VDD

18
21.5
0.55
1.2
5
6

26

28.5

1.6

1.8

6.9

7.3

LEAKAGE CURRENTS
Source Off Leakage, IS (Off )

0.01
0.25
0.01

Drain Off Leakage, ID (Off )

0.5
0.01
0.5

20

20

Channel On Leakage, ID, IS (On)


DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current

2.0
0.8
0.002

Break-Before-Make Time Delay, tBBM

4
170
250
75

V
typ
max
typ
max
typ
max
nA typ

0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANSITION

Unit

310

350
30

Rev. A | Page 4 of 20

nA max
nA typ

Test Conditions/Comments

VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,


IS = 10 mA; see Figure 27
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,
IS = 10 mA
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,
IS = 10 mA
VDD = 10.8 V
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 28
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 28

nA max
nA typ
nA max

VS = VD = 1 V or 10 V; see Figure 29

V min
V max
A typ
A max
pF typ

VIN = VGND or VDD

ns typ
ns max
ns typ
ns min

RL = 100 , CL = 35 pF
VS = 8 V; see Figure 29
RL = 100 , CL = 35 pF
VS1 = VS2 = 8 V; see Figure 31

ADG1406/ADG1407
Parameter
tON (EN)
tOFF (EN)
Charge Injection

+25C
145
205
112
150

40C to
+85C

40C to
+125C 1

250

285

175

200

pC typ

Off Isolation

73

dB typ

Channel-to-Channel Crosstalk

70

dB typ

3 dB Bandwidth
ADG1406
ADG1407
Insertion Loss

35
70
0.6

MHz typ
MHz typ
dB typ

12

pF typ

RL = 50 , CL = 5 pF, f = 1 MHz;
see Figure 36
f = 1 MHz

145
72

pF typ
pF typ

f = 1 MHz
f = 1 MHz

166
93

pF typ
pF typ

f = 1 MHz
f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD

0.002
1

IDD

150

VDD
2

Test Conditions/Comments
RL = 100 , CL = 35 pF
VS = 8 V; see Figure 31
RL = 100 , CL = 35 pF
VS = 8 V; see Figure 31
VS = 6 V, RS = 0 , CL = 1 nF; see
Figure 33
RL = 50 , CL = 5 pF, f = 1 MHz;
see Figure 34
RL = 50 , CL = 5 pF, f = 1 MHz;
see Figure 35
RL = 50 , CL = 5 pF; see Figure 36

10

CS (Off )
CD (Off )
ADG1406
ADG1407
CD, CS (On)
ADG1406
ADG1407
POWER REQUIREMENTS
IDD

Unit
ns typ
ns max
ns typ
ns max

475
5/16.5

Temperature range for B version: 40C to +125C.


Guaranteed by design, not subject to production test.

Rev. A | Page 5 of 20

A typ
A max
A typ
A max
V min/max

Digital inputs = 5 V
VSS = 0 V, GND = 0 V

ADG1406/ADG1407
5 V DUAL SUPPLY
VDD = +5 V 10%, VSS = 5 V 10%, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On -Resistance Match Between
Channels (RON)
On -Resistance Flatness (RFLAT(ON))

+25C

40C to
+85C

VSS to VDD
21
25
0.6
1.3
5.2
6.4

29

32

1.7

1.9

7.3

7.6

LEAKAGE CURRENTS
Source Off Leakage, IS (Off )

0.01
1

Drain Off Leakage, ID (Off )

0.25
0.01
0.5
0.01
0.5

Channel On Leakage, ID, IS (On)


DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current

40C to
+125C 1

Break-Before-Make Time Delay, tBBM

VS = 4.5 V, VD = 4.5 V; see Figure 28

nA max
nA typ

VS = 4.5 V, VD = 4.5 V; see Figure 28

20

VS = VD = 4.5 V; see Figure 29

20

nA max
nA typ
nA max
V min
V max
A typ
A max
pF typ

VIN = VGND or VDD

0.002
3.5

510

565
30

tON (EN)
tOFF (EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion, THD + N
3 dB Bandwidth
ADG1406
ADG1407
Insertion Loss
CS (Off )
CD (Off )
ADG1406
ADG1407
CD, CS (On)
ADG1406
ADG1407

230
335
205
290
10
73
70
0.18

VDD = +4.5 V, VSS = 4.5 V, VS = 4.5 V,


IS = 10 mA; see Figure 27
VDD = +4.5 V, VSS = 4.5 V, VS = 4.5V,
IS = 10 mA
VDD = +4.5 V, VSS = 4.5 V, VS = 4.5 V;
IS = 10 mA
VDD = +5.5 V, VSS = 5.5 V

2.0
0.8

260
435
90

V
typ
max
typ
max
typ
max

Test Conditions/Comments

nA typ

0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANSITION

Unit

400

445

340

370

ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ

RL = 100 , CL = 35 pF
VS = 5 V; see Figure 30
RL = 100 , CL = 35 pF
VS1 = VS2 = 5 V; see Figure 31
RL = 100 , CL = 35 pF
VS = 5 V; see Figure 32
RL = 100 , CL = 35 pF
VS = 5 V; see Figure 32
VS = 0 V, RS = 0 , CL = 1 nF; see Figure 33
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 35
RL = 110 , 5 V p-p, f = 20 Hz to 20 kHz; see
Figure 37
RL = 50 , CL = 5 pF; see Figure 36

40
80
1.15
10

MHz typ
MHz typ
dB typ
pF typ

RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 36


f = 1 MHz

123
62

pF typ
pF typ

f = 1 MHz
f = 1 MHz

148
88

pF typ
pF typ

f = 1 MHz
f = 1 MHz

Rev. A | Page 6 of 20

ADG1406/ADG1407
Parameter
POWER REQUIREMENTS
IDD

+25C

40C to
+85C

40C to
+125C 1

0.002
1

ISS

0.002
1
4.5/16.5

VDD/VSS
1
2

Unit
A typ
A max
A typ
A max
V min/max

Test Conditions/Comments
VDD = +5.5 V, VSS = 5.5 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V, 5 V, or VDD

Temperature range for B version: 40C to +125C.


Guaranteed by design, not subject to production test.

CONTINUOUS CURRENT PER CHANNEL


Table 5. ADG1406
Parameter
CONTINUOUS CURRENT PER CHANNEL 1
15 V Dual Supply
28-Lead TSSOP
32-Lead LFCSP
12 V Single Supply
28-Lead TSSOP
32-Lead LFCSP
5 V Dual Supply
28-Lead TSSOP
32-Lead LFCSP
1

25C

85C

125C

Unit

180
300

100
150

50
60

mA max
mA max

150
260

90
130

50
55

mA max
mA max

140
245

85
130

45
55

mA max
mA max

25C

85C

125C

Unit

135
235

85
125

45
55

mA max
mA max

110
190

70
110

40
50

mA max
mA max

105
180

65
100

40
50

mA max
mA max

Test Conditions/Comments
VDD = +13.5 V, VSS = 13.5 V

VDD = 10.8 V, VSS = 0 V

VDD = +4.5 V, VSS = 4.5 V

Guaranteed by design, not subject to production test.

Table 6. ADG1407
Parameter
CONTINUOUS CURRENT PER CHANNEL 1
15 V Dual Supply
28-Lead TSSOP
32-Lead LFCSP
12 V Single Supply
28-Lead TSSOP
32-Lead LFCSP
5 V Dual Supply
28-Lead TSSOP
32-Lead LFCSP
1

Test Conditions/Comments
VDD = +13.5 V, VSS = 13.5 V

VDD = 10.8 V, VSS = 0 V

VDD = +4.5 V, VSS = 4.5 V

Guaranteed by design, not subject to production test.

Rev. A | Page 7 of 20

ADG1406/ADG1407
ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted.

THERMAL RESISTANCE

Table 7.

JA is specified for the worst-case conditions, that is, a device


soldered in a circuit board for surface-mount packages.

Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog, Digital Inputs1

Continuous Current, Sx or Dx Pins


Peak Current, Sx or Dx Pins (Pulsed
at 1 ms, 10% Duty Cycle
Maximum)
28-Lead TSSOP
32-Lead LFCSP_VQ
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
Reflow Soldering, Pb-Free
Peak Temperature
Time at Peak Temperature
1

Rating
35 V
0.3 V to +25 V
+0.3 V to 25 V
VSS 0.3 V to VDD + 0.3 V
or 30 mA, whichever
occurs first
Table 5 and Table 6
specifications + 15%

Table 8. Thermal Resistance


Package Type
28-Lead TSSOP
32-Lead LFCSP_VQ

ESD CAUTION

300 mA
550 mA
40C to +125C
65C to +150C
150C
260 (+0/5)C
10 sec to 40 sec

Overvoltages at the Ax, EN, Sx, or Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.

Stresses above those listed under Absolute Maximum Ratings


may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any
one time.

Rev. A | Page 8 of 20

JA
97.9
27.27

JC
14

Unit
C/W
C/W

ADG1406/ADG1407

26

S8

S16

25

S7

S15

24

S6

S14

23

S5

S13

22

S4

S12

21

S3

S11

20

S2

S10 10

19

S1

S9 11

18

EN

GND 12

17

A0

NC 13

16

A1

A3 14

15

A2

ADG1406
TOP VIEW
(Not to Scale)

NC = NO CONNECT

S16
S15
S14
S13
S12
S11
S10
S9

1
2
3
4
5
6
7
8

PIN 1
INDICATOR

ADG1406
TOP VIEW
(Not to Scale)

24
23
22
21
20
19
18
17

S8
S7
S6
S5
S4
S3
S2
S1
07419-004

VSS

NC

32
31
30
29
28
27
26
25

27

9
10
11
12
13
14
15
16

28

GND
A3
A2
NC
NC
A1
A0
EN

NC

NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD TIED TO SUBSTRATE, VSS.
07419-003

VDD

NC
VDD
NC
D
NC
NC
NC
VSS

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 4. ADG1406 LFCSP Pin Configuration

Figure 3. ADG1406 TSSOP Pin Configuration

Table 9. ADG1406 Pin Function Descriptions


TSSOP
1
2, 3, 13
4
5
6
7
8
9
10
11
12
14
15
16
17
18

Pin No.
LFCSP_VQ
31
12, 13, 26,
27, 28, 30, 32
1
2
3
4
5
6
7
8
9
10
11
14
15
16

Mnemonic
VDD
NC

Description
Most Positive Power Supply Potential.
No Connect.

S16
S15
S14
S13
S12
S11
S10
S9
GND
A3
A2
A1
A0
EN

Source Terminal 16. This pin can be an input or an output.


Source Terminal 15. This pin can be an input or an output.
Source Terminal 14. This pin can be an input or an output.
Source Terminal 13. This pin can be an input or an output.
Source Terminal 12. This pin can be an input or an output.
Source Terminal 11. This pin can be an input or an output.
Source Terminal 10. This pin can be an input or an output.
Source Terminal 9. This pin can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be
connected to ground. The exposed pad is tied to the substrate, VSS.
Drain Terminal. This pin can be an input or an output.

19
20
21
22
23
24
25
26
27

17
18
19
20
21
22
23
24
25

S1
S2
S3
S4
S5
S6
S7
S8
VSS

28

29

Rev. A | Page 9 of 20

ADG1406/ADG1407
Table 10. ADG1406 Truth Table
A3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

A2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

A1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

A0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Rev. A | Page 10 of 20

On Switch
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

26

S8A

S8B

25

S7A

S7B

24

S6A

S6B

23

S5A

S5B

22

S4A

S4B

21

S3A

S3B

20

S2A

S2B 10

19

S1A

S1B 11

18

EN

GND 12

17

A0

NC 13

16

A1

NC 14

15

A2

ADG1407
TOP VIEW
(Not to Scale)

NC = NO CONNECT

S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B

1
2
3
4
5
6
7
8

PIN 1
INDICATOR

ADG1407
TOP VIEW
(Not to Scale)

24
23
22
21
20
19
18
17

S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A

07419-037

VSS

NC

32
31
30
29
28
27
26
25

DA

27

9
10
11
12
13
14
15
16

28

GND
A2
NC
NC
NC
A1
A0
EN

DB

NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD TIED TO SUBSTRATE, VSS.
07419-036

VDD

NC
DB
NC
VDD
NC
DA
NC
VSS

ADG1406/ADG1407

Figure 5. ADG1407 TSSOP Pin Configuration

Figure 6. ADG1407 LFCSP_VQ Pin Configuration

Table 11. ADG1407 Pin Function Descriptions


TSSOP
1
2
3, 13, 14
4
5
6
7
8
9
10
11
12
15
16
17
18

Pin No.
LFCSP_VQ
29
31
11, 12, 13, 26,
28, 30, 32
1
2
3
4
5
6
7
8
9
10
14
15
16

Mnemonic
VDD
DB
NC

Description
Most Positive Power Supply Potential.
Drain Terminal B. This pin can be an input or an output.
No Connect.

S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
A2
A1
A0
EN

Source Terminal 8B. This pin can be an input or an output.


Source Terminal 7B. This pin can be an input or an output.
Source Terminal 6B. This pin can be an input or an output.
Source Terminal 5B. This pin can be an input or an output.
Source Terminal 4B. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1A. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Source Terminal 3A. This pin can be an input or an output.
Source Terminal 4A. This pin can be an input or an output.
Source Terminal 5A. This pin can be an input or an output.
Source Terminal 6A. This pin can be an input or an output.
Source Terminal 7A. This pin can be an input or an output.
Source Terminal 8A. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be
connected to ground. The exposed pad is tied to the substrate, VSS.
Drain Terminal A. This pin can be an input or an output.

19
20
21
22
23
24
25
26
27

17
18
19
20
21
22
23
24
25

S1A
S2A
S3A
S4A
S5A
S6A
S7A
S8A
VSS

28

27

DA

Rev. A | Page 11 of 20

ADG1406/ADG1407
Table 12. ADG1407 Truth Table
A2
X
0
0
0
0
1
1
1
1

A1
X
0
0
1
1
0
0
1
1

A0
X
0
1
0
1
0
1
0
1

EN
0
1
1
1
1
1
1
1
1

On Switch Pair
None
1
2
3
4
5
6
7
8

Rev. A | Page 12 of 20

ADG1406/ADG1407
TYPICAL PERFORMANCE CHARACTERISTICS
16

18

VDD = +10V
VSS = 10V

14

VDD = +13.5V
VSS = 13.5V
15

ON RESISTANCE ()

VDD = +12V
VSS = 12V

10
8
6

VDD = +16.5V
VSS = 16.5V

VDD = +15V
VSS = 15V

12

TA = +125C
TA = +85C

TA = +25C
6

TA = 40C

3
TA = 25C
IS = 10mA

VDD = +15V
VSS = 15V

0
16.5 13.5 10.5 7.5 4.5

1.5

4.5

1.5

7.5

0
15

10.5 13.5 16.5

10

07419-009

07419-006

ON RESISTANCE ()

12

VS, VD (V)

Figure 7. On Resistance as a Function of VD (VS), Dual Supply


30

25

VDD = +5.0V
VSS = 5.0V

20
15

VDD = +5.5V
VSS = 5.5V

10
VDD = +7V
VSS = 7V

5
0
7

TA = +85C

15

TA = +25C
10

TA = 40C

TA = 25C
IS = 10mA
5

TA = +125C

20

VDD = +5V
VSS = 5V
0
5

07419-010

25

ON RESISTANCE ()

VDD = +4.5V
VSS = 4.5V

07419-007

ON RESISTANCE ()

15

VDD = +3.V
VSS = 3.V

30

VS, VD (V)

VS, VD (V)

Figure 11. On Resistance as a Function of VD (VS)


for Different Temperatures, 5 V Dual Supply

Figure 8. On Resistance as a Function of VD (Vs), Dual Supply


25

40
VDD = +5V
VSS = 0V

30

20

25
20

VDD = +10.8V
VSS = 0V

15

ON RESISTANCE ()

VDD = +8V
VSS = 0V
VDD = +12V
VSS = 0V

10
VDD = +15V
VSS = 0V

TA = 25C
IS = 10mA
0

1.5

3.0

4.5

6.0

7.5

9.0

10.5

12.0 13.5

TA = +85C
TA = +25C

10

TA = 40C
5

VDD = +13.2V
VSS = 0V

VDD = +12V
VSS = 0V

07419-008

TA = +125C
15

15.0

07419-011

35

ON RESISTANCE ()

10

Figure 10. On Resistance as a Function of VD (VS)


for Different Temperatures, 15 V Dual Supply

35

VS, VD (V)

10

VS, VD (V)

VS, VD (V)

Figure 12. On Resistance as a Function of VD (VS)


for Different Temperatures, 12 V Single Supply

Figure 9. On Resistance as a Function of VD (VS), Single Supply

Rev. A | Page 13 of 20

12

ADG1406/ADG1407
1.0

14
VDD = +15V
VSS = 15V
VBIAS = +10V/10V

0.4
0.2
0
0.2

IS (OFF) +
ID (OFF) +
IS (OFF) +
ID (OFF) +
ID, IS (ON) ++
ID, IS (ON)

0.4
0.6
0.8

07419-012

1.0
1.2
1.4

10

20

30

VDD = +12V
VSS = 0V
VBIAS = +1V/+10V

12

LEAKAGE CURRENT (nA)

LEAKAGE CURRENT (nA)

0.6

40

60

50

70

10
8

IS (OFF) +
ID (OFF) +
IS (OFF) +
ID (OFF) +
ID, IS (ON) ++
ID, IS (ON)

6
4
2
0

07419-015

0.8

2
4

80

20

40

TEMPERATURE (C)

Figure 13. Leakage Current as a Function of Temperature (up to 85C),


15 V Dual Supply

120

IDD (A)

100

0
IS (OFF) +
ID (OFF) +
IS (OFF) +
ID (OFF) +
ID, IS (ON) ++
ID, IS (ON)

4
6

20

80

VDD = +15V
VSS = 15V

60
VDD = +12V
VSS = 0V

40
20

40

60

80

100

120

07419-016

07419-013

LEAKAGE CURRENT (nA)

120

TA = 25C
IDD PER LOGIC INPUT

140

VDD = +5V
VSS = 5V
0

1.5

3.0

TEMPERATURE (C)

6.0

4.5

7.5

9.0

10.5

12.0

13.5

15.0

LOGIC LEVEL (Ax, EN) (V)

Figure 14. Leakage Current as a Function of Temperature,


15 V Dual Supply

Figure 17. IDD vs. Logic Level

100
TA = 25C

VDD = +5V
VSS = 5V
VBIAS = +4.5V/4.5V
IS (OFF) +
ID (OFF) +
IS (OFF) +
ID (OFF) +
ID, IS (ON) ++
ID, IS (ON)

4
3
2
1
0
1

07419-014

2
3
0

20

40

60

80

100

VDD = +15V
VSS = 15V

60
40
VDD = +5V
VSS = 5V

20
0

VDD = +12V
VSS = 0V

20
40
60
80
15

120

TEMPERATURE (C)

07419-017

80

CHARGE INJECTION (pC)

LEAKAGE CURRENT (nA)

100

160
VDD = +15V
VSS = 15V
VBIAS = +10V/10V

80

Figure 16. Leakage Current as a Function of Temperature,


12 V Single Supply

10

60

TEMPERATURE (C)

10

10

VS (V)

Figure 15. Leakage Current as a Function of Temperature,


5 V Dual Supply

Figure 18. Charge Injection vs. Source Voltage

Rev. A | Page 14 of 20

15

ADG1406/ADG1407
350

TIME (ns)

200

CROSSTALK (dB)

VDD = +5V
VSS = +5V

250

VDD = +12V
VSS = 0V

150
100
VDD = +15V
VSS = 15V

0
40

20

20

40

60

ADJACENT CHANNELS
(S1A TO S2A)

40

60

80
ADJACENT SWITCHES
(S1A TO S1B)

100
07419-018

50

VDD = +15V
VSS = 15V
TA = 25C

20

80

100

120
1k

120

10k

100k
1M
10M
FREQUENCY (Hz)

TEMPERATURE (C)

1G

Figure 22. ADG1407 Crosstalk vs. Frequency

Figure 19. Transition Time vs. Temperature


0

20

100M

07419-021

300

VDD = +15V
VSS = 15V
TA = 25C

0.5

60

80

100

2.0
2.5
3.0
3.5

10k

100k
1M
10M
FREQUENCY (Hz)

100M

1G

VDD = +15V
VSS = 15V
TA = 25C

4.0
100

07419-019

120
1k

1.5

Figure 20. Off Isolation vs. Frequency

100M

0.14

VDD = +15V
VSS = 15V
TA = 25C

VS = 20V p-p
0.12
0.10

THD + N (%)

50
70
90

VS = 15V p-p
0.06
0.04

130

0.02

10k

100k
1M
10M
FREQUENCY (Hz)

100M

1G

Figure 21. ADG1406 Crosstalk vs. Frequency

VDD = +15V
VSS = 15V
TA = 25C
RL = 100

0.08

110

150
1k

10M

Figure 23. ADG1406 On Response vs. Frequency

07419-020

CROSSTALK (dB)

30

10k
100k
1M
FREQUENCY (Hz)

VS = 10V p-p
07419-023

10

1k

07419-022

INSERTION LOSS (dB)

OFF ISOLATION (dB)

1.0
40

10

12

14

16

18

FREQUENCY (kHz)

Figure 24. THD + N vs. Frequency, 15 V Dual Supply

Rev. A | Page 15 of 20

20

ADG1406/ADG1407
0

1.2

20

VS = 10V p-p
VDD = +5V
VSS = 5V
TA = 25C
RL = 110

ACPSRR (dB)

40

0.6

0.4

VS = 5V p-p

0.2

VS = 2.5V p-p
0

10

NO DECOUPLING
CAPACITORS

60

80

DECOUPLING
CAPACITORS
ON SUPPLIES

100
07419-024

THD + N (%)

0.8

12

14

16

18

120
100

20

FREQUENCY (kHz)

1k

10k
100k
FREQUENCY (Hz)

Figure 26. ACPSRR vs. Frequency

Figure 25. THD + N vs. Frequency, 5 V Dual Supply

Rev. A | Page 16 of 20

1M

10M

07419-025

1.0

VDD = +15V
VSS = 15V
TA = 25C
V p-p = 0.63V

ADG1406/ADG1407
TERMINOLOGY
tBBM
Off time measured between the 80% points of the switches
when switching from one address state to another.

RON
Ohmic resistance between the D and S terminals.
RON
Difference between the RON of any two channels.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.

VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.

IS (Off)
Source leakage current when the switch is off.

IINL, IINH
Input current of the digital input.

ID (Off)
Drain leakage current when the switch is off.

IDD
Positive supply current.

ID, IS (On)
Channel leakage current when the switch is on.

ISS
Negative supply current.

VD, VS
Analog voltage on Terminal D and Terminal S.

Off Isolation
A measure of unwanted signal coupling through an off channel.

CS (Off)
Channel input capacitance for the off condition.

Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

CD (Off)
Channel output capacitance for the off condition.

Bandwidth
The frequency at which the output is attenuated by 3 dB.

CD, CS (On)
On switch capacitance.

On Response
The frequency response of the on switch.

CIN
Digital input capacitance.

THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.

tON (EN)
Delay time between the 50% and 90% points of the digital input
and the switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and the switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.

ACPSRR (AC Power Supply Rejection Ratio)


Measures the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude
of signal on the output to the amplitude of the modulation is
the ACPSRR.

Rev. A | Page 17 of 20

ADG1406/ADG1407
TEST CIRCUITS
V

IDS

ID (ON)

ID (OFF)
A

NC

VD

Figure 27. On Resistance

50%

50%

A
VD

NC = NO CONNECT

Figure 28. Off Leakage

3V
ADDRESS
DRIVE (VIN)

VS

07419-125

VS

Figure 29. On Leakage

tr < 20ns
tf < 20ns

VDD

VSS

VDD

VSS

A0

0V

VIN

tTRANSITION

S1

A1

50

VS1

S2 TO S15

A2
A3

tTRANSITION

VS16

S16

ADG14061

90%
2.4V

OUTPUT

OUTPUT
D

EN
GND

300

35pF

1SIMILAR

07419-028

90%

CONNECTION FOR ADG1407.

Figure 30. Address to Output Switching Times, tTRANSITION

3V
ADDRESS
DRIVE (VIN)

VDD

VSS

VDD

VSS

A0
VIN

0V

S1

A1

50

VS

S2 TO S15

A2
A3

S16
80%

ADG14061

80%

OUTPUT

2.4V

OUTPUT
D

EN
GND

300

35pF
07419-029

tBBM
1SIMILAR CONNECTION FOR ADG1407.

Figure 31. Break-Before-Make Delay, tBBM

3V
ENABLE
DRIVE (VIN)

50%

VDD

VSS

VDD

VSS

A0

50%

S1

A1
A2

0V

VS

S2 TO S16

A3

tOFF (EN)
0.9VOUT

OUTPUT

ADG14061

0.9VOUT
VIN

50

OUTPUT
D

EN
GND

300

1SIMILAR CONNECTION FOR ADG1407.

Figure 32. Enable Delay, tON (EN), tOFF (EN)

Rev. A | Page 18 of 20

35pF
07419-030

tON (EN)

07419-027

IS (OFF)

07419-026

ADG1406/ADG1407

3V

VDD

VSS

VDD
A0

VSS

A1
A2

VIN

A3

ADG14061

VOUT

VOUT

EN

VS

QINJ = CL VOUT

GND

VIN

CL
1nF

VOUT

07419-031

RS

1SIMILAR CONNECTION FOR ADG1407.

Figure 33. Charge Injection

VSS
0.1F

VDD

NETWORK
ANALYZER

NETWORK
ANALYZER

VSS
S

VOUT

VOUT

VS

VOUT
VS

07419-032

OFF ISOLATION = 20 log

R
50

GND

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

Figure 34. Off Isolation

VDD

VSS

S2

D
RL
50

VDD

0.1F

VS

GND

VSS

S1

RL
50

50

50

VDD
0.1F

VOUT
VS

07419-034

VDD
0.1F

Figure 36. Channel-to-Channel Crosstalk

VSS
0.1F

0.1F

VDD

VDD

VSS

VSS
0.1F

0.1F

NETWORK
ANALYZER

AUDIO PRECISION
VDD

50
VS

GND

IN

VOUT

VOUT WITHOUT SWITCH

RL
10k

07419-033

GND

INSERTION LOSS = 20 log

VS
V p-p

D
VIN

VOUT WITH SWITCH

RS

D
RL
50

VSS

Figure 37. THD + Noise

Figure 35. Bandwidth

Rev. A | Page 19 of 20

VOUT
07419-035

ADG1406/ADG1407
OUTLINE DIMENSIONS
9.80
9.70
9.60

28

15

4.50
4.40
4.30
1

6.40 BSC

14

PIN 1
0.65
BSC

1.20 MAX

0.15
0.05
COPLANARITY
0.10

0.30
0.19

SEATING
PLANE

8
0

0.20
0.09

0.75
0.60
0.45

COMPLIANT TO JEDEC STANDARDS MO-153-AE

Figure 38. 28-Lead Thin Shrink Small Outline Package [TSSOP]


(RU-28)
Dimensions shown in millimeters
0.60 MAX

5.00
BSC SQ

0.60 MAX

PIN 1
INDICATOR

0.50
BSC

4.75
BSC SQ

0.50
0.40
0.30
12 MAX

17
16

0.80 MAX
0.65 TYP

0.30
0.23
0.18

3.25
3.10 SQ
2.95

EXPOSED
PAD
(BOTTOM VIEW)

0.25 MIN
3.50 REF

0.05 MAX
0.02 NOM
SEATING
PLANE

0.20 REF

COPLANARITY
0.08

FOR PROPER CONNECTION OF


THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

011708-A

TOP
VIEW

1.00
0.85
0.80

PIN 1
INDICATOR
32

25
24

Figure 39. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]


5 mm 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model
ADG1406BRUZ 1
ADG1406BRUZ-REEL71
ADG1406BCPZ-REEL71
ADG1407BRUZ1
ADG1407BRUZ-REEL71
ADG1407BCPZ-REEL71
1

Temperature Range
40C to +125C
40C to +125C
40C to +125C
40C to +125C
40C to +125C
40C to +125C

Description
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Z = RoHS Compliant Part.

20082009 Analog Devices, Inc. All rights reserved. Trademarks and


registered trademarks are the property of their respective owners.
D07419-0-3/09(A)

Rev. A | Page 20 of 20

Package Option
RU-28
RU-28
CP-32-2
RU-28
RU-28
CP-32-2