Introduction to Silvaco ATHENA Tool and

Basic Concepts in Process Modeling

Part - 2
Instructor: Dragica Vasileska
Department of Electrical Engineering
Arizona State University

EEE 533 Semiconductor Device and Process Simulation

3. Description of the diffusion process

The diffusion process is a main step in the fabrication of
integrated circuits.

Some characteristic features of the diffusion process are
listed below:
 temperature: 900 C to 1300 C
 type of diffusion: selective and
non-selective

 amount of diffused impurities:

determined via solid-solubility limits

Solid-solubility of impurity
elements in silicon

EEE 533 Semiconductor Device and Process Simulation


The process of diffusion is described via the two Ficks laws:

J i = Di Cti Z i i (Cti Cci )E

Cti
+ J i = Gi
t
Ji
Cti
Cci
Zi
Di






i 
E 
Gi 

flux of diffusing species

total concentration
concentration of electrically inactive impurities
charge state of the i-th particle
diffusion coefficient
mobility
electric field
net generation term which equals zero for impurity
diffusion

EEE 533 Semiconductor Device and Process Simulation


The electric field term that appears in the expression

describing first Fick law should, in principle, be calculated by
solving Poissons equation, of the form:

e
= ( p n + ND N A )

where the net concentration of ionized impurities is:

C = Z i (Cti Cci )
i

For simplicity, the potential, and therefore, the electric field

are calculated using charge-neutrality, which gives:

= VT sinh

2ni

EEE 533 Semiconductor Device and Process Simulation


The magnitude of the diffusion coefficient depends upon the

concentration of defects in the crystal

There are four different types of defects that can be
observed in a crystal:
Impurity on interstitial site






point defects
line defects
area defects
volume defects

Silicon interstitial

Frenkel
defect
Silicon atoms
Vacancy

Impurity on substitutional site

Point defects description

EEE 533 Semiconductor Device and Process Simulation


The position of the interstitial voids in a zincblende lattice is

schematically illustrated in the figure below:

EEE 533 Semiconductor Device and Process Simulation


Listed below are the characteristic features of vacancies:

 Vacancy is a missing atom in the crystalline lattice
 The energy of formation of a vacancy equals 2.3 eV (to break
four bonds), and the energy of migration is 0.18 eV
 Since divacancy requires breaking of six covalent bonds, the
energy of formation of divacancy is only slightly higher, and is,
therefore, commonly encountered
 The # of vacancies per unit volume is given by:

Es
ns = N exp

k BT

N  total # of atoms in a crystal

(51022 cm-3)
Es  energy of formation
ns  density of vacancies

 Since the presence of a vacancy results in four unsatisfied

bonds, vacancies are of an acceptor-type with energy levels:
(EV + 0.71 eV)
for V
(vacancy)
(EV + 1.0 eV)
for V=
(divacancy)
EEE 533 Semiconductor Device and Process Simulation


The characteristic features of interstitials are listed below:

 Interstitial is a Si atom located on one of many interstitial sites
 The energy of formation of an interstitial equals 1.1 eV
 The # of interstitials is calculated in the same manner as the
# of vacancies
 Interstitials have four valence electrons that can be donated
to the conduction band, and are of a donor-type, with energy level
+
(EC - 0.91 eV)
for V

Some characteristic properties of Frenkel pairs:

 The energy of formation of a Frenkel pair is comparable to
the energy of formation of an interstitial
 The # of Frenkel pairs is calculated from:

Ef

n f = N exp
2 k BT

Ef  energy of formation
of a Frenkel defect

EEE 533 Semiconductor Device and Process Simulation


The diffusion process in a semiconductor occurs via

vacancies and interstitials, which is schematically shown in
the figures below:
Vacancy
diffusion

Interstitial
diffusion

The magnitude of the diffusion coefficient is of the following

form for the two dopant concentration limiting cases:
(a) low concentration:

E
D = D0 exp a
Ea  activation energy
k BT
(b) high concentration: D = Di0 + Di V + Di= V = + Di+ V +
2

0 n n
= p +
= Di + Di + Di + Di
ni
ni
ni

EEE 533 Semiconductor Device and Process Simulation


For doping concentrations close to the solid-solubility limit,

the impurities start to cluster and stop diffusing:
 The relationship between the total Ct and the electrically
inactive concentration Cc due to clustering effect, is found by
solving the following equation:

Cc
= m kc (Ct Cc )m kd Cc
t
Clustering rate

Declustering rate

Cluster size
 The clustering effect is important when the doping concentration is on the order of 31020 cm-3 for arsenic.

EEE 533 Semiconductor Device and Process Simulation


Under the assumption of zero electric field and constant

diffusion coefficient, one needs to solve the following
differential equation using, for example, Laplace transform:
C
C
2C
1D
2
= D C
=D 2
t
t
x
 Depending upon the type of boundary conditions, two
possible solutions exist:
 diffusion from an infinite source
 diffusion from a finite source
Diffusion from an infinite source
 The initial and boundary conditions for this case are:

C ( x = 0, t 0) = Cs

and

C ( x > 0, t = 0) = 0

 This leads to the following form of the solution:

x
C ( x, t ) = Cs erfc
,
2 Dt

Dt  characteristic length

EEE 533 Semiconductor Device and Process Simulation

Diffusion from a finite source

 Using a predeposition process, a certain ammount of
impurity atoms is added in a very narrow region near the
surface. Then the sample is heated and diffusion process
takes place.
 The initial and boundary conditions for this case are:

C
= 0 and Q = C ( x, t ) dx = const .
x x = 0,t 0
0
 This leads to the following form of the solution:
x2
Q

C ( x, t ) =
exp
4 Dt
Dt

C/Cs
C/Cs

Dt
Finite
Infinite
source
source
x
EEE 533 Semiconductor Device and Process Simulation

Dt
x


Junction depth determination

During the diffusion of, for example,
acceptor-type impurities, the net
acceptor concentration equals to:

N Anet ( x, t ) = N A ( x, t ) N D

N ( x, t )
p-type n-type

The junction depth is, then, given by

the following expressions:

N A ( x, t )

(a) Infinite source:

N D = const .

1 N D

x j = 2 Dt erfc
N0
(b) Finite source:

Q
x j = 2 Dt ln

N D Dt
EEE 533 Semiconductor Device and Process Simulation

xj


Lateral diffusion
The previously described model accurately describes the
diffusion process, except near the edges of the mask
windows, where impurities also diffuse laterally.
 The ratio of the lateral to vertical penetration is about 75% for
concentration independent diffusivities and about 65% to 70% for
concentration dependent diffusivities.
 Since electric field intensities are higher for cylindrical and spherical
junction regions, avalanche breakdown voltages will be substantially
lower when compared to the plane junction case.

2D - diffusion profile
showing the lateral diffusion

EEE 533 Semiconductor Device and Process Simulation


Impurity redistribution during subsequent oxidation

Dopant impurities near the silicon surface are redistributed
during the subsequent thermal oxidation process. The
redistribution process depends upon several factors listed
below:
 The magnitude of the segregation coefficient:

C in Si
k=
C in SiO 2
 The magnitude of the impurity
diffusivity in the oxide
 The consumption of the
underlying Si layer

EEE 533 Semiconductor Device and Process Simulation


Diffusion constant determination

Decribed below are two methods for the experimental determination of the diffusion constant:
(A) pn-junction method
The requirement here is to make one or more diffusions into semiconductors with known background concentration and opposite impurity
type. After determining the junction depth, one gets:
2
2

x
N B1 = N 0erfc x j1 2 Dt
1
j1
j2

(
N B 2 = N 0erfc (x j 2

) D

Dt )
4t ln[(N B 2 x j1 ) N B1x j 2 ]

(B) Boltzmann-Matano method

This method is used when the depth-dependence of the doping profile is
obtained, for example, via SIMS technique. Then, for initially undoped
substrates, one has:
The diffusion constant is determined
N1
1 dx
from the knowledge of the slope at
DN = N1 =
xdN
arbitrary depth and the total # of dif2t dN 0
fused impurities.

EEE 533 Semiconductor Device and Process Simulation


Most important statements for ATHENA diffusion simulation

DIFFUSE statement
 This statement initiates a time temperature step for

oxidation, silicidation and diffusion of impurities

 Important parameters that can be specified here are:

 Surface impurity concentration via: C.ARSENIC,

C.BORON, C.ANTIMONY, etc.
 CONTINUE  continuation of the diffusion process
 DRYO2, WETO2, NITROGEN, AMMONIA, ARGON
 gas present in the furnace (one type is specified)
 F.02, F.H2, F.H20, F.N2 and F.HCL  flow-rates
 HCL.PC  percentage of HCL in the oxidant stream
 PRESSURE  partial pressure of active species
 TEMPERATURE  furnace temperature
 T.FINAL, T.RATE  final T and ramp-rate
 TIME  amount of time spent in the furnace
EEE 533 Semiconductor Device and Process Simulation

METHOD statement
 This statement is used to set flags for selecting various
mathematical algorithms used in the simulation and to select
the desired diffusion model complexity
 Important parameters that can be specified here are:
 VACANCIES, INTERSTIT, ARSENIC, .., OXIDANT,
VELOCITY, TRAPS, PSI, etc.  parameters used to
specify a single impurity, trap or a potential
 FERMI  the defects are assumed to be a function
of the Fermi level only
TWO.DIM  full time-dependent transient simulation has to be performed
STEADY  defects are in steady-state
FILL.CPL  full coupling between defects and
dopants is included
 CLUSTER.DAM  Stanford cluster model enabled
 HIGH.CONC  doping concentration dependent
point defect recombination model terms enabled
EEE 533 Semiconductor Device and Process Simulation

4. Description of the oxidation process

The oxidation process involves thermal growth of SiO2 or
deposition of silicon nitride

The deposited SiO2 layer can be used for the following
purpose:
 diffusion mask for selective dopant diffusion
 pn-junction protection from atmospheric influence
 dielectric layer in MOS-transistors (gate oxide)
 isolation between transistors fabricated on the same
chip (field oxide)

Some figures of merit for the oxidation process:
 oxidation temperature: 900 C to 1200 C
 typical gas flow rate: 1 cm/sec
 depending upon the ambient, one can have:
(a) Dry oxidation process: Si + O2  SiO2
(b) Wet oxidation process: Si + 2H20  SiO2 + 2H2
EEE 533 Semiconductor Device and Process Simulation

 During the oxidation process, the underlying Si material

is consumed:
Si thickness = 0.44 (oxide thickness)
 the basic structural unit of thermally grown SiO2 is
shown in the figure below:

(a) Basic structural unit

of SiO2
(b) Quartz crystal lattice
(c) Amorphous structure

EEE 533 Semiconductor Device and Process Simulation


The kinetics of thermal oxidation is described via the DealGrove model that is given below:
F1 = h(C*-C0) - flux of oxidant from the bulk of the gas
to the gas-oxide interface
C* = oxidant concentration in the bulk
C0 = oxidant concentration at gas/oxide interface
h = gas-phase mass transfer ratio

F2 = D(C0-Cs)/Xox - flux across the oxide

Cs = oxidant concentration at the SC/oxide interface
D = diffusion coefficient
C(x)

F3 = ksCs - oxide/SC oxidation reaction

F1 = F2 = F3 = N1dXox/dt

silicon

C0

ks = chemical surface-reaction coefficient

F1

N1 = # of oxidant molecules incorporated

into unit volume

EEE 533 Semiconductor Device and Process Simulation

F2
0

Cs

F3
Xox


The analytic solution of the kinetic equations gives:

X ox (0) 2 4 Bt
A
X ox (t ) = 1 + 2
+
1

2
2
A
A

where: A = 2 D 1 + 1 , B = 2 DC *
N1
ks h

(a) short-time limit behavior: X ox (t ) ( B / A)(t + )

- the linear rate constant B/A varies as exp(-Ea/kBT)
with activation energy Ea of about 2 eV
- B/A has orientation dependence
(b) long-time limit behavior: X ox (t ) Bt
- The activation energy for the parabolic rate constant
equals to: Ea(dry)=1.24 eV and Ea(wet)=0.71 eV
- does not exhibit orientation dependence
EEE 533 Semiconductor Device and Process Simulation


For thin oxides, the differential equation that describes the

oxide growth is modified to:
dX ox
ThE
X ox
B
exp

=
+ Rth , Rth = Th0 exp
dt
A + 2 X ox
k BT
ThL

In the SSUPREM4 implementation of the oxidation process,

one can distinguish between:
 analytical oxidation models
 numerical oxidation models
(A) Analytical oxidation models
The initial silicon surface must be planar. Also:
B/A = L0LpLHClLbaf

L0 = intrinsic linear oxidation rate

Lp = pressure dependent coefficient
LHCl = chlorine dependent coefficient
Lbaf = doping-dependent coefficient

B = P0PpPHCl

same meaning as above

EEE 533 Semiconductor Device and Process Simulation

(B) Numerical oxidation models

 Three numerical models have also been implemented
in SSUPREM4:
VERTICAL, COMPRESS and VISCOUS
 In all three models, the oxidation equations are solved
to obtain the growth rate at each point of the Si/SiO2 interface
 COMPRESS and VISCOUS solve:
2V = P,

where:

P = hydrodynamic pressure
gradient
V = velocity
= E/(2+2) = viscosity

 The VISCOUS model is more advanced than

COMPRESS, since it incorporates strain into the problem.
EEE 533 Semiconductor Device and Process Simulation


Most important statements for oxidation simulation

OXIDE statement
 All parameters related to the description of the oxidation

process are specified here

 Important parameters include:

 DRY02, WET02  type of oxidation process for

which specific coefficients apply
 LIN.L.0, LIN.L.E, LIN.H.0, LIN.H.E, L.BREAK 
specification of linear-rate coefficient B/A
 PAR.L.0, PAR.L.E, PAR.H.0, PAR.H.E, P.BREAK
 parabolic rate coefficient B specification
METHOD statement
 ERFC, ERF1, ERF2, ERFG  Birds beak spec.
 VERTICAL  vertical oxide growth
 COMPRESS  compressible liquid model
 VISCOUS  incompressible liquid model
EEE 533 Semiconductor Device and Process Simulation


Charged states at the interface and in the oxide

 The electronic properties of the oxide and the oxide/SC interface
have profound effect on the properties of the devices
 There are a number of allowed states within the forbidden gap,
called Shockley or Tamm states:


Fast surface states:

- density: 1011 to 1012 cm-2
- time constant: 1 sec
- responsible for generation-recombination effects at the surface
- increased leakage current when junction penetrates the surface
- Shorter minority carrier lifetimes
- early fall-off in transistor gain

Slow states:
- behave as traps and are essentially ionized silicon
- time constant on the order of seconds and months
- do not influence electrical properties, but affect threshold voltage

Oxygen-ion vacancies and alkali ions

EEE 533 Semiconductor Device and Process Simulation

Location of the oxide charges

The charges that exist in a realistic MOS structure can be
classified into four different categories:

(1) Mobile ionic charges

(2) Oxide-trapped charges

+-

+
Na
+-

K
+-

+-

++

+-

+-

(3) Fixed oxide charges

+

(4) Interface-trap charges

EEE 533 Semiconductor Device and Process Simulation

 Mobile oxide charges: Due to ionic impurities such as Na,

K, etc.
Oxide-trapped charge: May be positive or negative and is
due to holes or electrons trapped in the bulk of the oxide.
Fixed oxide charges: Due to structural defects (ionized
silicon) in the oxide layer.
Interface-trapped charges: Positive or negative charges due
to:
structural, oxidation induced defects
metal impurities
other defects due to bond-breaking processes
Unlike other oxide charges, interface-trapped charge is in
electrical communication with the underlying silicon and
can be charged and discharged.
EEE 533 Semiconductor Device and Process Simulation

 The expression for the voltage drop across the oxide layer
Vox in the presence of a non-zero charge distribution (x) is
found from the solution of the 1D Poisson equation, using
the boundary conditions: ox(0)=0 and ox(dox)=Vox .
The final result of this calculation is given below:
d ox

Vox

Qox
1
= d ox Fox (d ox )
, =
Cox
d ox

xox ( x)dx

0
d ox

ox ( x)dx

Special cases:
 uniform charge distribution: =1/2
 Charges at the SC/oxide interface: =1
 Charges at the metal/oxide interface: =0
EEE 533 Semiconductor Device and Process Simulation

 The threshold voltage shift due to workfunction difference

and charges in the oxide is given by:
Oxide charges

VG = VG VG'
Voltage applied to real
MOS capacitor with
oxide charges

Work function
difference

Qox 1
=
+ MS = VFB
Cox q

Flat-band
voltage

Voltage applied to ideal

MOS capacitor

Important note: All the charges (mobile ion charges, fixed

oxide charges, oxide trapped charges) except the interfacetrap charges lead to rigid shift of the CV curve.
EEE 533 Semiconductor Device and Process Simulation

 More information on interface-trapped charges:

Most of the interface-trapped charges can be neutralized
by low-temperature hydrogen annealing.
The interface trap density is given by:
D it

1 dQit # of charges
Dit =

2
q dE cm eV

<111>
<100>

Interface trap charges can be:

- acceptor-like (above the intrinsic level)
- donor-like (below the intrinsic level)
EEE 533 Semiconductor Device and Process Simulation

Eg

 Use simplified model that all of the states below the Fermi
level are full and all of the states above the Fermi level are
empty.
Depletion:

Accumulation:

EC

Ei
E FS
EV

The excess negative charges

lead to positive shift.

EC

Ei
E FS
EV
The excess positive charges
lead to negative shift.

EEE 533 Semiconductor Device and Process Simulation

 Modification of the HF-CV curve due to interface-trapped

charges.
Gate

C tot
Cox
Interface-traps close
to valence band.
Interface-traps
close to mid-gap.

Cox
Interface-traps close
to conduction band.

C HF

Cinv C depl C acc

Cit

VG
Contribution from the charging and
discharging of the interface traps.
EEE 533 Semiconductor Device and Process Simulation


Modeling of charge states

 The density of trapped carriers on the discrete set of defects/trap
centers is given by:
k

nt = nt ,
=1

pt = pt

: # of acceptor traps; : # of donor traps

=1

K
+
G
n
p

nt = N ta
,

G p + Gn + K p + K n

pt = N td

K p + Gn

G p + Gn + K p + K n

where:

K p = pV p p; K n = nVn n
E Et
1
;
G p = pV p ni exp i

k BT

E Et

Gn = nVn ni exp i
k BT

Et : energy level of the trap

: degeneracy factor
Vn, Vp : thermal velocities
n, p : capture cross-sections

EEE 533 Semiconductor Device and Process Simulation

The introduction of traps into the model gives rise to

(a) Additional charge term in the Poisson equation:

t = q ( pt nt )
(b) Modification of the SRH recombination term
2

pn ni
R, =

E E ,
E E ,
1
t + n + n exp i
t
n p +
ni exp i
p
i

k
T
kBT

,
B

where: = ( V N )1; = V N 1
n
n n t
p
p p t


The ATLAS implementation is via the TRAP statement:

DONOR, ACCEPTOR  trap type
E.LEVEL  trap energy level
DENSITY  density Nt of traps
DEGEN.FACTOR 
SIGN, SIGP  capture cross-sections for electrons and holes
TAUN, TAUP  electron and hole lifetimes (alternative)

EEE 533 Semiconductor Device and Process Simulation

5. Description of the etching process

Within the SSUPREM4 software, there is a very rudimentary
model for the etching process, which considers etching as a
purely geometrical problem

Etch steps are simulated using the ETCH statement in
which the material to be etched and the geometrical shape
of the etch region are specified:
 polygonal region
 region to the left or right of a line segment
 region between top boundary and a line obtained by
translating top boundary down in the y-direction (DRY
and THICKNESS parameters)
 All regions of a particular material type (ALL parameter)

All materials in the defined region will be etched

Specifying the material to be etched limits the etching process to the pre-selected material type
EEE 533 Semiconductor Device and Process Simulation

ETCH statement
This statement allows simulation of the etching process.
SSUPREM4 only purely geometrical etch model, and ELITE
includes physical etch model.
 Important parameters that can be specified here are:

 SILICON, OXIDE, POLYSILICON, GAAS,

PHOTORESIST, INP, ,  material to be etched
 ALL  all of the specified material is removed
 DRY  resulting surface replicates the exposed
surface
 LEFT, RIGHT, ABOVE, BELOW  quick means of
etching in a trapezoidal region (P1.X, P1.Y, P2.X,
P2.Y)
 START, CONTINUE, DONE  arbitrary complex
region to be etched
 THICKNESS  thickness to be etched
EEE 533 Semiconductor Device and Process Simulation

6. Description of the deposition process

Deposition process is described via a simple algorithm that
describes conformal deposition

Parameters that are specified within the DEPOSIT statement include:
MATERIAL  specify material to be deposited
NAME.RESIST  type of photoresist to be deposited
THICKNESS  specifies the deposited thickness, in micrometers
DIVISIONS  number of vertical grid spacings in deposited layer
CONC  concentration of impurity (type must be specified also)
MIN.SPACE  minimum spacing between points on the surface
DY  nominal spacing in the layer
YDY  depth at which nominal spacing is applied relative to the
surface
MIN.DY  minimum spacing allowed between grid-lines
(default value is 10 angstroms)

EEE 533 Semiconductor Device and Process Simulation

7. Description of the epitaxy process

This process simulates epitaxial deposition of silicon. It is
limited to silicon on silicon applications and should not be
used when other materials are present

Parameters that are specified within the EPITAXY statement include:
ARSENIC, BORON, PHOSPH  specify material to be deposited
CONC  concentration of impurity
DIVISIONS  number of vertical grid spacings in deposited layer
DY  nominal spacing in the layer
YDY  depth at which nominal spacing is applied relative to the
surface
MIN.DY  minimum spacing allowed between grid-lines
(default value is 10 angstroms)
PRESS  defines the pressure of epitaxial deposition process
T.FINAL  final temperature for ramped epitaxial steps
TEMP  defines the temperature of the epitaxial deposition
TIME, THICKNESS, RATE  parameters of epitaxial process

EEE 533 Semiconductor Device and Process Simulation