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DESIGN
A. Albert Raj
T. Latha
VLSI DESIGN
A. ALBERT RAJ
T. LATHA
Assistant Professor
Assistant Professor
New Delhi-110001
2008
VLSI DESIGN
A. Albert Raj and T. Latha
2008 by PHI Learning Private Limited, New Delhi. All rights reserved. No part of this book may be
reproduced in any form, by mimeograph or any other means, without permission in writing from the
publisher.
ISBN-978-81-203-3431-1
The export rights of this book are vested solely with the publisher.
Published by Asoke K. Ghosh, PHI Learning Private Limited, M-97, Connaught Circus,
New Delhi-110001 and Printed by Mudrak, 30-A, Patparganj, Delhi-110091.
Contents
Preface
xiii
1. INTRODUCTION
1 4
2.6
15
21
Interconnect
22
Circuit Elements
25
BiCMOS Technology
2.7.1
2.7.2
11
2.7
10
NMOS Fabrication 12
Basic CMOS Technology
2.5.1
2.5.2
2.5.3
2.5.4
2.4
2.5
533
Introduction 5
Basic MOS Transistor Operation
2.2.1
2.2.2
29
Summary
32
Review Questions 33
Short Answer Questions
33
iii
iv
Contents
Introduction 34
Static Behaviour of the MOS Transistor
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.3
3.7
3.8
43
Threshold Variations
46
SourceDrain Resistance
47
Variation in I-V Characteristics
Subthreshold Conduction
49
CMOS Latchup
50
46
48
NMOS Inverter 50
Determination of Pull-up to Pull-down Ratio (Zp.u/Zp.d) for an
NMOS Inverter Driven by Another NMOS Inverter 52
Pull-up to Pull-down Ratio for an NMOS Inverter Driven Through One
or More Pass Transistors 54
Device Models for Simulation 56
3.8.1
3.8.2
3.8.3
3.8.4
MOS Models
56
DC MOSFET Model
56
High Frequency MOSFET Model
SPICE Models
60
Summary
62
Review Questions 62
Short Answer Questions
57
62
4.5
4.6
6389
Introduction 63
CMOS InverterDC Characteristics 65
Design Parameters of CMOS Inverter 75
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.4
42
3.5
3.6
35
3.4
3462
85
81
80
78
Contents
4.7
Power Dissipation
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
86
88
5.6
90115
Introduction 90
Why Design Rules 90
MOS Layers 91
Stick Diagrams 91
5.4.1
5.4.2
5.5
94
95
96
109
Basic Concepts
110
Design Hierarchies
111
Summary
114
Review Questions 114
Short Answer Questions
114
Static Dissipation
87
Dynamic Dissipation
87
Short-circuit Dissipation
87
Total Power Dissipation
87
Power Economy
88
Summary
88
Review Questions 88
Short Answer Questions
5.1
5.2
5.3
5.4
Introduction 116
Tally Circuits 117
NANDNAND, NORNOR, and AOI Logic
Exclusive-OR Structures 122
Barrel Shifter 127
Transmission Gates 130
Latches and Flip-flops 131
6.7.1
6.7.2
116136
119
134
vi
Contents
Introduction 137
RC Delay Lines 138
Super Buffers 139
7.3.1
7.3.2
7.3.3
7.3.4
7.4
7.5
7.6
7.7
137157
142
Summary
156
Review Questions 156
Short Answer Questions
153
155
156
Introduction 158
Static CMOS Design
8.2.1
8.2.2
8.2.3
8.3
159
Complementary CMOS
159
Ratioed Logic
163
Pass-Transistor Logic
164
158178
166
167
172
9.4.1
9.4.2
9.4.3
9.4.4
9.5
179197
Introduction 179
Timing Metrics for Sequential Circuits 180
Classification of Memory Elements 181
Static Latches and Registers 183
Bistability Principle
183
Multiplexer-Based Latches
183
MasterSlave Edge-Triggered Register
Low Voltage Static Latches
187
185
187
188
Contents
9.6
9.7
192
193
Summary
196
Review Questions 196
Short Answer Questions
vii
192
Pulse Registers
192
Sense Amplifier-Based Registers
194
197
198225
217
Multiplier: Definitions
218
Partial-Product Generation
219
Partial-Product Accumulation
220
Final Addition
223
Summary
224
Review Questions 224
Short Answer Questions
225
226258
227
232
232
239
242
Summary
257
Review Questions 258
Short Answer Questions
258
viii
Contents
259 284
260
262
Summary
283
Review Questions 283
Short Answer Questions
285307
294
304
Clock Routing
Power Routing
Summary
306
Review Questions 306
Short Answer Questions
277
284
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
262
304
305
306
Contents
ix
308351
Functionality Tests
309
Manufacturing Tests
309
Test Process
310
Reliability
311
Reliability Modelling
310
312
314
Fault Models
314
Gate Level Testing
317
Observability
321
Controllability
321
Fault Coverage
321
Automatic Test Pattern Generation (ATPG)
Fault Grading and Fault Simulation
326
Delay Fault Testing
327
Statistical Fault Analysis
328
Fault Sampling
329
330
333
343
343
344
344
Verilog by Example
350
352365
322
354
354
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Author : RAJ, A.
ALBERT, LATHA, T.