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// Code your testbench here

// or browse Examples

`timescale 1 ns / 1 ps

module axi_mod_v1_0 #
(
// Users to add parameters here

// User parameters ends


// Do not modify the parameters beyond this line

// Parameters of Axi Slave Bus Interface S0_AXI


parameter integer C_S0_AXI_ID_WIDTH= 1,
parameter integer C_S0_AXI_DATA_WIDTH

= 32,

parameter integer C_S0_AXI_ADDR_WIDTH

= 32,

parameter integer C_S0_AXI_AWUSER_WIDTH= 0,


parameter integer C_S0_AXI_ARUSER_WIDTH = 0,
parameter integer C_S0_AXI_WUSER_WIDTH = 0,
parameter integer C_S0_AXI_RUSER_WIDTH = 0,
parameter integer C_S0_AXI_BUSER_WIDTH

= 0,

// Parameters of Axi Master Bus Interface M0_AXI


parameter C_M0_AXI_TARGET_SLAVE_BASE_ADDR
parameter integer C_M0_AXI_BURST_LEN
parameter integer C_M0_AXI_ID_WIDTH

= 16,
= 1,

parameter integer C_M0_AXI_ADDR_WIDTH


parameter integer C_M0_AXI_DATA_WIDTH

= 32,
= 32,

parameter integer C_M0_AXI_AWUSER_WIDTH

= 0,

parameter integer C_M0_AXI_ARUSER_WIDTH

= 0,

parameter integer C_M0_AXI_WUSER_WIDTH

= 0,

= 32'h40000000,

parameter integer C_M0_AXI_RUSER_WIDTH

= 0,

parameter integer C_M0_AXI_BUSER_WIDTH

=0

)
(
// Users to add ports here
//input bg_axi_sel,
output wire [31:0] qa1,
//output wire selo1,
// User ports ends
// Do not modify the ports beyond this line

// Ports of Axi Slave Bus Interface S0_AXI


input wire s0_axi_aclk,
input wire s0_axi_aresetn,
input wire [C_S0_AXI_ID_WIDTH-1 : 0] s0_axi_awid,
input wire [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_awaddr,
input wire [7 : 0] s0_axi_awlen,
input wire [2 : 0] s0_axi_awsize,
input wire [1 : 0] s0_axi_awburst,
input wire s0_axi_awlock,
input wire [3 : 0] s0_axi_awcache,
input wire [2 : 0] s0_axi_awprot,
input wire [3 : 0] s0_axi_awqos,
input wire [3 : 0] s0_axi_awregion,
input wire [C_S0_AXI_AWUSER_WIDTH-1 : 0] s0_axi_awuser,
input wire s0_axi_awvalid,
output wire s0_axi_awready,
input wire [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_wdata,
input wire [(C_S0_AXI_DATA_WIDTH/8)-1 : 0] s0_axi_wstrb,
input wire s0_axi_wlast,
input wire [C_S0_AXI_WUSER_WIDTH-1 : 0] s0_axi_wuser,

input wire s0_axi_wvalid,


output wire s0_axi_wready,
output wire [C_S0_AXI_ID_WIDTH-1 : 0] s0_axi_bid,
output wire [1 : 0] s0_axi_bresp,
output wire [C_S0_AXI_BUSER_WIDTH-1 : 0] s0_axi_buser,
output wire s0_axi_bvalid,
input wire s0_axi_bready,
input wire [C_S0_AXI_ID_WIDTH-1 : 0] s0_axi_arid,
input wire [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_araddr,
input wire [7 : 0] s0_axi_arlen,
input wire [2 : 0] s0_axi_arsize,
input wire [1 : 0] s0_axi_arburst,
input wire s0_axi_arlock,
input wire [3 : 0] s0_axi_arcache,
input wire [2 : 0] s0_axi_arprot,
input wire [3 : 0] s0_axi_arqos,
input wire [3 : 0] s0_axi_arregion,
input wire [C_S0_AXI_ARUSER_WIDTH-1 : 0] s0_axi_aruser,
input wire s0_axi_arvalid,
output wire s0_axi_arready,
output wire [C_S0_AXI_ID_WIDTH-1 : 0] s0_axi_rid,
output wire [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_rdata,
output wire [1 : 0] s0_axi_rresp,
output wire s0_axi_rlast,
output wire [C_S0_AXI_RUSER_WIDTH-1 : 0] s0_axi_ruser,
output wire s0_axi_rvalid,
input wire s0_axi_rready,

//---------------------------------- master ports


input wire m0_axi_init_axi_txn,
output wire m0_axi_txn_done,
output wire m0_axi_error,

input wire m0_axi_aclk,


input wire m0_axi_aresetn,
output wire [C_M0_AXI_ID_WIDTH-1 : 0] m0_axi_awid,
// output wire [C_M0_AXI_ADDR_WIDTH-1 : 0] m0_axi_awaddr,
output wire [7 : 0] m0_axi_awlen,
output wire [2 : 0] m0_axi_awsize,
output wire [1 : 0] m0_axi_awburst,
output wire m0_axi_awlock,
output wire [3 : 0] m0_axi_awcache,
output wire [2 : 0] m0_axi_awprot,
output wire [3 : 0] m0_axi_awqos,
output wire [C_M0_AXI_AWUSER_WIDTH-1 : 0] m0_axi_awuser,
output wire m0_axi_awvalid,
input wire m0_axi_awready,
output wire [C_M0_AXI_DATA_WIDTH-1 : 0] m0_axi_wdata,
output wire [C_M0_AXI_DATA_WIDTH/8-1 : 0] m0_axi_wstrb,
output wire m0_axi_wlast,
output wire [C_M0_AXI_WUSER_WIDTH-1 : 0] m0_axi_wuser,
output wire m0_axi_wvalid,
input wire m0_axi_wready,
input wire [C_M0_AXI_ID_WIDTH-1 : 0] m0_axi_bid,
input wire [1 : 0] m0_axi_bresp,
input wire [C_M0_AXI_BUSER_WIDTH-1 : 0] m0_axi_buser,
input wire m0_axi_bvalid,
output wire m0_axi_bready,
output wire [C_M0_AXI_ID_WIDTH-1 : 0] m0_axi_arid,
// output wire [C_M0_AXI_ADDR_WIDTH-1 : 0] m0_axi_araddr,
output wire [7 : 0] m0_axi_arlen,
output wire [2 : 0] m0_axi_arsize,
output wire [1 : 0] m0_axi_arburst,
output wire m0_axi_arlock,
output wire [3 : 0] m0_axi_arcache,

output wire [2 : 0] m0_axi_arprot,


output wire [3 : 0] m0_axi_arqos,
output wire [C_M0_AXI_ARUSER_WIDTH-1 : 0] m0_axi_aruser,
output wire m0_axi_arvalid,
input wire m0_axi_arready,
input wire [C_M0_AXI_ID_WIDTH-1 : 0] m0_axi_rid,
input wire [C_M0_AXI_DATA_WIDTH-1 : 0] m0_axi_rdata,
input wire [1 : 0] m0_axi_rresp,
input wire m0_axi_rlast,
input wire [C_M0_AXI_RUSER_WIDTH-1 : 0] m0_axi_ruser,
input wire m0_axi_rvalid,
output wire m0_axi_rready
);
wire bg_axi_sel;
// Instantiation of Axi Bus Interface S0_AXI
assign m0_axi_awid = s0_axi_awid;
// assign m0_axi_awaddr = s0_axi_awaddr;
assign m0_axi_awlen = s0_axi_awlen;
assign m0_axi_awsize = s0_axi_awsize;
assign m0_axi_awburst = s0_axi_awburst;
assign m0_axi_awlock = s0_axi_awlock;
assign m0_axi_awcache = s0_axi_awcache;
assign m0_axi_awprot = s0_axi_awprot;
assign m0_axi_awqos = s0_axi_awqos;
assign m0_axi_awuser = s0_axi_awuser;
assign m0_axi_awvalid = s0_axi_awvalid;
assign m0_axi_wdata = s0_axi_wdata;
assign m0_axi_wstrb = s0_axi_wstrb;
assign m0_axi_wlast = s0_axi_wlast;
assign m0_axi_wuser = s0_axi_wuser;
assign m0_axi_wvalid = s0_axi_wvalid;
assign m0_axi_bready = s0_axi_bready;

assign m0_axi_arid = s0_axi_arid;


// assign m0_axi_araddr = s0_axi_araddr;
assign m0_axi_arlen = s0_axi_arlen;
assign m0_axi_arsize = s0_axi_arsize;
assign m0_axi_arburst = s0_axi_arburst;
assign m0_axi_arlock = s0_axi_arlock;
assign m0_axi_arcache = s0_axi_arcache;
assign m0_axi_arprot = s0_axi_arprot;
assign m0_axi_arqos = s0_axi_arqos;
assign m0_axi_aruser = s0_axi_aruser;
assign m0_axi_arvalid = s0_axi_arvalid;
assign m0_axi_rready = s0_axi_rready;
// -------------------------------------assign s0_axi_awready = m0_axi_awready;
assign s0_axi_wready = m0_axi_wready;
assign s0_axi_bid = m0_axi_bid;
assign s0_axi_bresp = m0_axi_bresp;
assign s0_axi_buser = m0_axi_buser;
assign s0_axi_bvalid = m0_axi_bvalid;
assign s0_axi_arready = m0_axi_arready;
assign s0_axi_rid = m0_axi_rid;
assign s0_axi_rdata = m0_axi_rdata;
assign s0_axi_rresp = m0_axi_rresp;
assign s0_axi_rlast = m0_axi_rlast;
assign s0_axi_ruser = m0_axi_ruser;
assign s0_axi_rvalid = m0_axi_rvalid;

// Add user logic here


//assign bg_axi_sel = (s0_axi_awvalid == 1'b1 && m0_axi_awready ==
1'b1)? 1'b1 : 1'b0;
assign qa1 = (s0_axi_awvalid) ? s0_axi_awaddr : (s0_axi_arvalid) ?
s0_axi_araddr : qa1;
//assign selo1 = bg_axi_sel;

// User logic ends

endmodule

`timescale 1 ns / 1 ps

module axi_mod_b2_v1_0 #
(
// Users to add parameters here

// User parameters ends


// Do not modify the parameters beyond this line

// Parameters of Axi Master Bus Interface M0_AXI


parameter C_M0_AXI_TARGET_SLAVE_BASE_ADDR =
32'h40000000,
parameter integer C_M0_AXI_BURST_LEN

= 16,

parameter integer C_M0_AXI_ID_WIDTH

= 1,

parameter integer C_M0_AXI_ADDR_WIDTH

= 32,

parameter integer C_M0_AXI_DATA_WIDTH

= 32,

parameter integer C_M0_AXI_AWUSER_WIDTH


parameter integer C_M0_AXI_ARUSER_WIDTH= 0,
parameter integer C_M0_AXI_WUSER_WIDTH = 0,
parameter integer C_M0_AXI_RUSER_WIDTH = 0,
parameter integer C_M0_AXI_BUSER_WIDTH = 0,

// Parameters of Axi Slave Bus Interface S0_AXI


parameter integer C_S0_AXI_ID_WIDTH

= 1,

parameter integer C_S0_AXI_DATA_WIDTH


parameter integer C_S0_AXI_ADDR_WIDTH

= 32,
= 32,

= 0,

parameter integer C_S0_AXI_AWUSER_WIDTH

= 0,

parameter integer C_S0_AXI_ARUSER_WIDTH

= 0,

parameter integer C_S0_AXI_WUSER_WIDTH

= 0,

parameter integer C_S0_AXI_RUSER_WIDTH

= 0,

parameter integer C_S0_AXI_BUSER_WIDTH

=0

)
(
// Users to add ports here
input [31:0] qa2,
//input bg_axi_sel,

// User ports ends


// Do not modify the ports beyond this line
input wire s0_axi_aclk,
input wire s0_axi_aresetn,
input wire [C_S0_AXI_ID_WIDTH-1 : 0] s0_axi_awid,
//input wire [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_awaddr,
input wire [7 : 0] s0_axi_awlen,
input wire [2 : 0] s0_axi_awsize,
input wire [1 : 0] s0_axi_awburst,
input wire s0_axi_awlock,
input wire [3 : 0] s0_axi_awcache,
input wire [2 : 0] s0_axi_awprot,
input wire [3 : 0] s0_axi_awqos,
input wire [3 : 0] s0_axi_awregion,
input wire [C_S0_AXI_AWUSER_WIDTH-1 : 0] s0_axi_awuser,
input wire s0_axi_awvalid,
output wire s0_axi_awready,
input wire [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_wdata,
input wire [(C_S0_AXI_DATA_WIDTH/8)-1 : 0] s0_axi_wstrb,
input wire s0_axi_wlast,
input wire [C_S0_AXI_WUSER_WIDTH-1 : 0] s0_axi_wuser,

input wire s0_axi_wvalid,


output wire s0_axi_wready,
output wire [C_S0_AXI_ID_WIDTH-1 : 0] s0_axi_bid,
output wire [1 : 0] s0_axi_bresp,
output wire [C_S0_AXI_BUSER_WIDTH-1 : 0] s0_axi_buser,
output wire s0_axi_bvalid,
input wire s0_axi_bready,
input wire [C_S0_AXI_ID_WIDTH-1 : 0] s0_axi_arid,
// input wire [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_araddr,
input wire [7 : 0] s0_axi_arlen,
input wire [2 : 0] s0_axi_arsize,
input wire [1 : 0] s0_axi_arburst,
input wire s0_axi_arlock,
input wire [3 : 0] s0_axi_arcache,
input wire [2 : 0] s0_axi_arprot,
input wire [3 : 0] s0_axi_arqos,
input wire [3 : 0] s0_axi_arregion,
input wire [C_S0_AXI_ARUSER_WIDTH-1 : 0] s0_axi_aruser,
input wire s0_axi_arvalid,
output wire s0_axi_arready,
output wire [C_S0_AXI_ID_WIDTH-1 : 0] s0_axi_rid,
output wire [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_rdata,
output wire [1 : 0] s0_axi_rresp,
output wire s0_axi_rlast,
output wire [C_S0_AXI_RUSER_WIDTH-1 : 0] s0_axi_ruser,
output wire s0_axi_rvalid,
input wire s0_axi_rready,

// Ports of Axi Master Bus Interface M0_AXI


input wire m0_axi_init_axi_txn,
output wire m0_axi_txn_done,
output wire m0_axi_error,

input wire m0_axi_aclk,


input wire m0_axi_aresetn,
output wire [C_M0_AXI_ID_WIDTH-1 : 0] m0_axi_awid,
output wire [C_M0_AXI_ADDR_WIDTH-1 : 0] m0_axi_awaddr,
output wire [7 : 0] m0_axi_awlen,
output wire [2 : 0] m0_axi_awsize,
output wire [1 : 0] m0_axi_awburst,
output wire m0_axi_awlock,
output wire [3 : 0] m0_axi_awcache,
output wire [2 : 0] m0_axi_awprot,
output wire [3 : 0] m0_axi_awqos,
output wire [C_M0_AXI_AWUSER_WIDTH-1 : 0] m0_axi_awuser,
output wire m0_axi_awvalid,
input wire m0_axi_awready,
output wire [C_M0_AXI_DATA_WIDTH-1 : 0] m0_axi_wdata,
output wire [C_M0_AXI_DATA_WIDTH/8-1 : 0] m0_axi_wstrb,
output wire m0_axi_wlast,
output wire [C_M0_AXI_WUSER_WIDTH-1 : 0] m0_axi_wuser,
output wire m0_axi_wvalid,
input wire m0_axi_wready,
input wire [C_M0_AXI_ID_WIDTH-1 : 0] m0_axi_bid,
input wire [1 : 0] m0_axi_bresp,
input wire [C_M0_AXI_BUSER_WIDTH-1 : 0] m0_axi_buser,
input wire m0_axi_bvalid,
output wire m0_axi_bready,
output wire [C_M0_AXI_ID_WIDTH-1 : 0] m0_axi_arid,
output wire [C_M0_AXI_ADDR_WIDTH-1 : 0] m0_axi_araddr,
output wire [7 : 0] m0_axi_arlen,
output wire [2 : 0] m0_axi_arsize,
output wire [1 : 0] m0_axi_arburst,
output wire m0_axi_arlock,
output wire [3 : 0] m0_axi_arcache,

output wire [2 : 0] m0_axi_arprot,


output wire [3 : 0] m0_axi_arqos,
output wire [C_M0_AXI_ARUSER_WIDTH-1 : 0] m0_axi_aruser,
output wire m0_axi_arvalid,
input wire m0_axi_arready,
input wire [C_M0_AXI_ID_WIDTH-1 : 0] m0_axi_rid,
input wire [C_M0_AXI_DATA_WIDTH-1 : 0] m0_axi_rdata,
input wire [1 : 0] m0_axi_rresp,
input wire m0_axi_rlast,
input wire [C_M0_AXI_RUSER_WIDTH-1 : 0] m0_axi_ruser,
input wire m0_axi_rvalid,
output wire m0_axi_rready
);
// Instantiation of Axi Bus Interface M0_AXI

// Add user logic here


assign m0_axi_awid = s0_axi_awid;
// assign m0_axi_awaddr = s0_axi_awaddr;
assign m0_axi_awlen = s0_axi_awlen;
assign m0_axi_awsize = s0_axi_awsize;
assign m0_axi_awburst = s0_axi_awburst;
assign m0_axi_awlock = s0_axi_awlock;
assign m0_axi_awcache = s0_axi_awcache;
assign m0_axi_awprot = s0_axi_awprot;
assign m0_axi_awqos = s0_axi_awqos;
assign m0_axi_awuser = s0_axi_awuser;
assign m0_axi_awvalid = s0_axi_awvalid;
assign m0_axi_wdata = s0_axi_wdata;
assign m0_axi_wstrb = s0_axi_wstrb;
assign m0_axi_wlast = s0_axi_wlast;
assign m0_axi_wuser = s0_axi_wuser;
assign m0_axi_wvalid = s0_axi_wvalid;

assign m0_axi_bready = s0_axi_bready;


assign m0_axi_arid = s0_axi_arid;
// assign m0_axi_araddr = s0_axi_araddr;
assign m0_axi_arlen = s0_axi_arlen;
assign m0_axi_arsize = s0_axi_arsize;
assign m0_axi_arburst = s0_axi_arburst;
assign m0_axi_arlock = s0_axi_arlock;
assign m0_axi_arcache = s0_axi_arcache;
assign m0_axi_arprot = s0_axi_arprot;
assign m0_axi_arqos = s0_axi_arqos;
assign m0_axi_aruser = s0_axi_aruser;
assign m0_axi_arvalid = s0_axi_arvalid;
assign m0_axi_rready = s0_axi_rready;
// -------------------------------------assign s0_axi_awready = m0_axi_awready;
assign s0_axi_wready = m0_axi_wready;
assign s0_axi_bid = m0_axi_bid;
assign s0_axi_bresp = m0_axi_bresp;
assign s0_axi_buser = m0_axi_buser;
assign s0_axi_bvalid = m0_axi_bvalid;
assign s0_axi_arready = m0_axi_arready;
assign s0_axi_rid = m0_axi_rid;
assign s0_axi_rdata = m0_axi_rdata;
assign s0_axi_rresp = m0_axi_rresp;
assign s0_axi_rlast = m0_axi_rlast;
assign s0_axi_ruser = m0_axi_ruser;
assign s0_axi_rvalid = m0_axi_rvalid;
// User logic ends
assign m0_axi_awaddr = (s0_axi_awvalid) ? qa2 : m0_axi_awaddr;
assign m0_axi_araddr = (s0_axi_arvalid) ? qa2 : m0_axi_araddr;

endmodule