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SIGNAL
PROPAGATION
ADVANCED BLACK MAGIC
Howard Johnson
Martin Graham
`\\\
PRENTICE
HALL
PTR
NJ 07458
TABLE OF CONTENTS
Preface
xxi
Glossary of Symbols
xxvii
1 Fundamentals
1.1
Impedance of Linear, Time-Invariant, Lumped-Element Circuits
1.2
Power Ratios
1.3
Rufes of Scaling
1.3.1
Scaling of Physical Size
1.3.1.1 Scaling Inductors
1.3.1.2 Scaling Transmission-Line Dimensions
1.3.2
Power Scaling
1.3.3
Time Scaling
1.3.4
Impedance Scaling with Constant Voltage
1.3.5
Dielectric-Constant Scaling
1.3.5.1 Partially Embedded Transmission Lines
1.3.6
Magnetic Permeability Scaling
1.4 The Concept of Resonance
1.5
Extra for Experts: Maximal Linear System Response to a Digital Input
2 Transmission Line Parameters
1
2
5
6
8
8
9
10
12
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16
22
29
2.1
Telegrapher's Equations
2.1.1
So Good II Works an Barbed Wire
2.1.2
The No-Storage Principle and Its Implications for
Returning Signal Current
2.2
Derivation of Telegrapher's Equations
2.2.1
Definition of Characteristic Impedance ZC
2.2.2
Changes in Characteristic Impedance
2.2.3
Calculation of Impedance Zc From Parameters R, L, G, And C
2.2.4
Defmition of Propagation Coefficient y
2.2.5
Calculation of Propagation Coefficient y from Parameters R, L, G, and C
Ideal Transmission Line
2.3
2.4
DC Resistance
DC Conductance
2.5
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Table of Contents
3.4.3
Taylor-Series Approximation of H (Lumped-Element Region)
3.4.4
Input impedance (Lumped-Element Region)
3.4.5
Transfer Function (Lumped-Element Region)
3.4.6
Step Response (Lumped-Element Region)
3.5 RC Region
3.5.1
Boundary of RC Region
3.5.2
Input Impedance (RC Region)
3.5.3
Characteristic Impedance (RC Region)
3.5.4
General Behavior within RC Region
3.5.5
Propagation Coefficient (RC Region)
3.5.6
Transfer Function (RC Region)
3.5.6.1 Propagation Function of RC Line with Open-Circuited Load
3.5.6.2 Propagation Function of RC Line with Matched End Termination
3.5.6.3 Propagation Function of RC Line with Matched Source Termination
3.5.6.4 Propagation Function of RC Line with Resistive End Termination
3.5.7
Normalized Step Response (RC Region)
3.5.8
Tradeoffs Between Distance and Speed (RC Region)
3.5.9
Closed-Form Solution for Step Response (RC Region)
3.5.10 Elmore Delay Estimation (RC Region)
LC Region (Constant-Loss Region)
3.6
3.6.1
Boundary of LC Region
Characteristic Impedance (LC Region)
3.6.2
Influence of Series Resistance on TDR Measurements
3.6.3
Propagation Coefficient (LC Region)
3.6.4
Possibility of Severe Resonance within the LC Region
3.6.5
3.6.5.1 Alternate Interpretation of Equation [3.17]
3.6.5.2 Practical Effect of Resonance
Terminating an LC Transmission Line
3.6.6
3.6.6.1 End Termination
3.6.6.2 Source Termination
3.6.6.3 Both-Ends Termination
3.6.6.4 Subtle Differences Between Termination Styles
3.6.6.5 Application of Termination Equations to Other Regions
Tradeoffs Between Distance And Speed (LC Region)
3.6.7
Mixed-Mode Operation (LC and RC Regions)
3.6.8
Skin-Effect Region
3.7
Boundary of Skin-Effect Region
3.7.1
Characteristic Impedance (Skin-Effect Region)
3.7.2
Influence of Skin-Effect on TDR Measurement
3.7.3
Propagation Coefficient (Skin-Effect Region)
3.7.4
Possibility of Severe Resonance within Skin-Effect Region
3.7.5
3.7.5.1 Subtle Differences Between Termination Styles
3.7.5.2 Application of Termination Equations to Other Regions
Step Response (Skin-Effect Region)
3.7.6
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xiv
Table of Contents
Through-Hole Clearances
5.4.2
Measuring Connectors
5.4.3
Tapered Transitions
5.4.4
Straddle-Mount Connectors
5.4.5
Cable Shield Grounding
5.4.6
Modeling
Vias
5.5
Incremental
Parameters of a Via
5.5.1
Three Models for a Via
5.5.2
Dangling Vias
5.5.3
Capacitance Data
5.5.4
5.5.4.1 Three-Layer Via Capacitance
5.5.4.2 Effect of Back-Drilling
5.5.4.3 Effect of Multiple Planes
Inductance Data
5.5.5
5.5.5.1 Through-Hole Via Inductance
5.5.5.2 Via Crosstalk
Tlw Future of On-Chip Interconnections
5.6
6 Differential Signaling
Single-Ended Circuits
6.1
Two-Wire Circuits
6.2
Differential Signaling
6.3
6.4 Differential and Common-Mode Voltages and Currents
Differential and Common-Mode velocity
6.5
6.6 Common-Mode Balance
6.7 Common-Mode Range
6.8 Differential to Common-Mode Conversion
Differential Impedance
6.9
6.9.1
Relation Between Odd-Mode and Uncoupled Impedance
6.9.2
Why the Odd-Mode Impedance Is Always Less Than the
Uncoupled Impedance
6.9.3
Differential Reflections
6.10 Pcb Configurations
6.10.1 Differential (Microstrip) Trace Impedance
6.10.2 Edge-Coupled Stripline
6.10.3 Breaking Up a Pair
6.10.4 Broadside-Coupled Stripline
6.11 Pcb Applications
6.11.1 Matching to an External, Balanced Differential Transmission Medium
6.11.2 Defeating ground bounce
6.11.3 Reducing EMI with Differential Signaling
6.11.4 Punching Through a Noisy Connector
6.11.4.1
Differential Signaling (Through Connectors)
6.11.5 Reducing Clock Skew
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xvi
Table of Contents
Fiber-Optic Cabling
11.1 Making Glass Fiber
11.2 Finished Core Specifications
11.3 Cabling the Fiber
11.4 Wavelengths of Operation
11.5 Multimode Glass Fiber-Optic Cabling
11.5.1 Multimode Signal Propagation
11.5.2 Why Is Graded-Index Fiber Better than Step-Index?
11.5.3
Standards for Multimode Fiber
11.5.4 What Considerations Govern the Use of 50-micron Fiber?
475
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Table of Contents
Clock Distribution
12.1 Extra Fries, Please
12.2 Aritlunetic of Clock Skew
12.3 Clock Repeaters
12.3.1 Active Skew Correction
12.3.2 Zero-Delay Clock Repeaters
12.3.3 Compensating for Line Length
12.4 Stripline vs. Microstrip Delay
12.5 Importance of Tenninating Clock Lines
12.6 Effect of Clock Receiver Thresholds
12.7 Effect of Split Termination
12.8 Intentional Delay Adjustments
12.8.1 Fixed Delay
12.8.2 Adjustable Delays
12.8.3 Automatically Programmable Delays
12.8.4 Serpentine Delays
12.8.5 Switchback Coupling
12.9 Driving Multiple Loads with Source Termination
12.9.1 To Tee or Not To Tee
12.9.2 Driving Two Loads
Daisy-Chain Clock Distribution
12.10
Case Study of Daisy-Chained Clock
12.10.1
12.11
The Jitters
When Clock Jitter Matters
12.11.1
12.11.1.1 Clock Jitter Rarely Matters within the Boundaries of a
Synchronous State Machine
12.11.1.2 Clock Jitter Propagation
12.11.1.3 Variance of the Tracking Error
12.11.1.4 Clock Jitter in FIFO-Based Architectures
xvil
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Table of Contents
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645
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651
12.11.2.1 Jitter Measurement
654
12.11.2.2 Jitter and Phase Noise
Power Supply Filtering for Clock Sources, Repeaters, and PLL Circuits 656
12.12
659
12.12.1
Healthy Power
661
12.12.2
Clean Power
663
12.13
Intentional Clock Modulation
665
12.13.1
Signal Integrity Mailbag
12.13.2
Jitter-Free Clocks
667
668
Reduced-Voltage Signaling
12.14
Controlling Crosstalk an Clock Lines
669
12.15
670
12.16
Reducing Emission
13
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Collected References
703
Table of Contents
xix
Points to Remember
710
731
733
735
737
739
741
743
745
Appendix E - erf( )
747
Index
749