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UC3842B/3B/4B/5B
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Minidip
SO8
DESCRIPTION
The UC384xB family of control ICs provides the necessary features to implement off-line or DC to DC
fixed frequency current mode control schemes with
a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lockout featuring start-up current less than 0.5mA, a precision reference trimmed for accuracy at the error
amp input, logic to insure latched operation, a PWM
BLOCK DIAGRAM (toggle flip flop used only in UC3844B and UC3845B)
Vi
7
UVLO
34V
GROUND
S/R
5V
REF
INTERNAL
BIAS
2.50V
VREF GOOD
LOGIC
RT/CT
VFB
COMP
CURRENT
SENSE
2
1
3
OSC
+
-
ERROR AMP.
VREF
5V 50mA
OUTPUT
T
2R
R
S
1V
R
CURRENT
SENSE
COMPARATOR
PWM
LATCH
UC3842B
D95IN331
March 1999
1/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vi
Vi
IO
EO
Value
Unit
30
Self Limiting
1
5
Output Current
Analog Inputs (pins 2, 3)
0.3 to 5.5
J
V
10
1.25
mA
W
Ptot
800
mW
65 to 150
40 to 150
C
C
300
Tstg
TJ
TL
* All voltages are with respect to pin 5, all currents are positive into the specified terminal.
COMP
VREF
VFB
Vi
ISENSE
OUTPUT
RT/CT
GROUND
D95IN332
PIN FUNCTIONS
No
Function
COMP
Description
VFB
This is the inverting input of the Error Amplifier. It is normally connected to the switching
power supply output through a resistor divider.
ISENSE
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
RT/CT
The oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible.
GROUND
OUTPUT
This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced
and sunk by this pin.
VCC
Vref
This is the reference output. It provides charging current for capacitor C T through resistor RT.
This pin is the Error Amplifier output and is made available for loop compensation.
ORDERING NUMBERS
SO8
UC2842BD1;
UC2843BD1;
UC2844BD1;
UC2845BD1;
2/15
UC3842BD1
UC3843BD1
UC3844BD1
UC3845BD1
Minidip
UC2842BN;
UC2843BN;
UC2844BN;
UC2845BN;
UC3842BN
UC3843BN
UC3844BN
UC3845BN
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
THERMAL DATA
Symbol
Rth j-amb
Description
Thermal Resistance Junction-ambient.
Minidip
SO8
Unit
100
150
C/W
max.
ELECTRICAL CHARACTERISTICS ( [note 1] Unless otherwise stated, these specifications apply for
-25 < Tamb < 85C for UC284XB; 0 < Tamb < 70C for UC384XB; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
Symbol
Parameter
REFERENCE SECTION
VREF
Output Voltage
Test Conditions
Line Regulation
12V Vi 25V
VREF
Load Regulation
1 Io 20mA
ISC
(Note 2)
10Hz f 10KHz Tj = 25C
(note 2)
50
Tamb =
(note 2)
125C,
-30
VOSC
(peak to peak)
Idischg
V3
Ib
50
25
25
mV
55
56
275
KHz
KHz
KHz
0.2
0.2
0.5
1.6
1.6
7.8
7.5
8.3
8.8
8.8
7.8
7.6
8.3
8.8
8.8
mA
mA
TJ = 25C
-0.1
-1
-0.1
90
65
0.7
12V Vi 25V
60
70
-2
V
A
90
dB
0.7
MHz
60
70
dB
12
12
mA
-0.5
-1
-0.5
-1
mA
6.2
6.2
0.8
(note 3 & 4)
2.85
VPIN1 = 5V (note 3)
0.9
12 Vi 25V (note 3)
Delay to Output
mV/C
5.18
52
250
4.82
49
48
225
mV
55
56
275
65
25
52
250
2V Vo 4V
VPIN2 = 2.3V;
RL = 15K to Ground
VPIN2 = 2.7V;
RL = 15K to Pin 8
mA
AVOL
mV
-100 -180
VFB = 5V
VOUT High
20
-30
VOUT Low
SVR
VPIN1 = 2.5V
0.2
5.1
-100 -180
49
Tj = 25C
48
TA = Tlow to Thigh
TJ = 25C (RT = 6.2k, CT = 1nF) 225
TA = Tlow to Thigh
4.9
1000Hrs
Io
25
fOSC/T
Io
BW
20
0.2
fOSC/V
PSRR
OSCILLATOR SECTION
fOSC
Frequency
Ib
Tj = 25C Io = 1mA
VREF
UC284XB
UC384XB
Unit
Min. Typ. Max. Min. Typ. Max.
1.1
3.15 2.85
1.1
70
0.9
0.8
1.1
3.15
V/V
1.1
70
V
dB
-2
-10
-2
-10
150
300
150
300
ns
3/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Conditions
UC284XB
UC384XB
Unit
Min. Typ. Max. Min. Typ. Max.
OUTPUT SECTION
VOL
VOH
VOLS
ISINK = 20mA
0.1
0.4
0.1
0.4
ISINK = 200mA
1.6
2.2
1.6
2.2
ISOURCE = 20mA
13
13.5
13
13.5
ISOURCE = 200mA
12
13.5
12
13.5
UVLO Saturation
0.1
1.1
0.1
1.1
tr
Rise Time
50
150
50
150
ns
tf
Fall Time
50
150
50
150
ns
X842B/4B
15
16
17
14.5
16
17.5
X843B/5B
7.8
8.4
9.0
7.8
8.4
9.0
X842B/4B
10
11
8.5
10
11.5
X843B/5B
7.0
7.6
8.2
7.0
7.6
8.2
X842B/3B
94
96
100
94
96
100
X844B/5B
47
48
50
47
48
50
PWM SECTION
Maximum Duty Cycle
Start-up Current
0.3
0.5
0.3
0.5
mA
0.3
0.5
0.3
0.5
mA
12
17
12
17
mA
VPIN2 = VPIN3 = 0V
Zener Voltage
Ii = 25mA
30
36
30
36
Notes : 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as
close to Tamb as possible.
2. These parameters, although guaranteed, are not 100% tested in production.
3. Parameter measured at trip point of latch with VPIN2 = 0.
4. Gain defined as :
VPIN1
A=
; 0 VPIN3 0.8 V
VPIN3
5. Adjust Vi above the start threshold before setting at 15 V.
4/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
Figure 1: Open Loop Test Circuit.
VREF
RT
4.7K
2N2222
100K
COMP
1K
ISENSE
ADJUST
4.7K
5K
Vi
2
3
RT/CT
OUTPUT
1W
1K
0.1F
UC2842B
ISENSE
Vi
0.1F
8
VFB
ERROR AMP.
ADJUST
VREF
OUTPUT
GROUND
CT
GROUND
D95IN343
RT
(K)
D95IN333
D95IN334
50
T=
20
0p
T=
10
0p
T=
50
20
CT=5nF
50
CT=2nF
30
0p
CT=5nF
20
T=
1n
CT=1nF
10
CT=10nF
CT=100pF
Vi=15V
TA=25C
1
0.8
10K
CT=200pF
CT=2nF
CT=10nF
CT=500pF
10
Vi=15V
TA=25C
20K
30K
50K
100K
200K 300K
500K
fOSC(KHz)
1
10K
20K
30K
50K
100K
200K 300K
500K fOSC(KHz)
5/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
Figure 4: Oscillator Discharge Current vs. Temperature.
Idischg
(mA)
D95IN335
Dmax
(%)
Vi=15V
VOSC=2V
90
8.5
Idischg=7.5mA
80
Idischg=8.8mA
70
8.0
60
Vi=15V
CT=3.3nF
TA=25C
7.5
50
40
7.0
-55
-25
25
50
75
100 TA(C)
(dB)
Vi=15V
VO=2V to 4V
RL=100K
TA=25C
80
Gain
60
0.8
RT(K)
Figure 7: Current Sense Input Threshold vs. Error Amp Output Voltage.
30
Vth
(V)
D95IN338
Vi=15V
1.0
TA=25C
60
0.8
90
0.6
20
120
0.4
150
0.2
180
f(Hz)
0.0
TA=125C
40
Phase
-20
10
100
1K
10K
100K
1M
60
Vi=15V
50
TA=-40C
ISC
(mA)
Vi=15V
RL0.1
100
TA=-40C
40
VO(V)
90
TA=125C
30
TA=25C
80
20
70
10
60
50
6/15
20
40
60
80
100 Iref(mA)
-55
-25
25
50
75
100 TA(C)
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
Figure 10: Output Saturation Voltagevs. Load
Current.
Ii
(mA)
D95IN341
Vi
-1
-2
Source Saturation
(Load to Ground)
TA=25C
TA=-40C
D95IN342
20
Vi=15V
80s Pulsed Load 120Hz Rate
15
UCX843/45
10
TA=-40C
TA=25C
5
Sink Saturation
(Load to Vi)
0
0
200
400
RT=10K
CT=3.3nF
VFB=0V
ISense=0V
TA=25C
UCX842/44
Vsat
(V)
GND
0
600
IO(mA)
10
20
30
Vi(V)
Vi =15V
CL = 1.0nF
TA = 25C
90%
VO
20V/DIV
ICC
10%
100mA/DIV
50ns/DIV
100ns/DIV
Vi
CT
7
8
5V REG
OUTPUT
PWM
RT
LARGE RT/SMALL CT
OUTPUT
CLOCK
4
OSCILLATOR
CT
ID
OUTPUT
CT
5
SMALL RT/LARGE CT
GND
D95IN344
7/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
Figure 15 : Error Amp Configuration.
2.5V
1mA
+
VFB
COMP
Zi
Zf
D95IN345
Vi
ON/OFF COMMAND
TO REST OF IC
ICC
UC3842B UC3843B
UC3844B UC3845B
VON
16V
8.4V
VOFF
10V
7.6V
<17mA
<0.5mA
VOFF VON
D95IN346
VCC
3
CURRENT
SENSE
5
GND
D95IN347
2R
R
1V
CURRENT
SENSE
COMPARATOR
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
Figure 18 : Slope Compensation Techniques.
VREG
VREG
RT
RT
RT/CT
IS
RSLOPE
CT
R1
RT/CT
IS
UC3842B
RSLOPE
ISENSE
R1
3
5
RS
UC3842B
CT
ISENSE
3
5
RS
GND
GND
D95IN348
Vin
ISOLATION
BOUNDARY
5.0Vref
VGS Waveforms
+
0
-
Q1
+
S
R
50% DC
Ipk =
+
0
-
V(pin 1) -1.4
3RS
25% DC
NS
( )
NP
+
COMP/LATCH
3
C
RS
NS
NP
D95IN349
9/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
Figure 20 : Latched Shutdown.
4
OSC
8
R
BIAS
R
+
1mA
2R
+
-
EA
1
5
2N
3905
2N
3903
D95IN350
SCR must be selected for a holding current of less than 0.5mA at TA(min).
The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.
From VO
2.5V
1mA
Ri
2
Rd
2R
Cf
EA
Rf
1
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.
From VO
2.5V
1mA
RP
Ri
2
CP
Rd
2R
Cf
Rf
EA
1
5
D95IN351
Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.
10/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
Figure 22: External Clock Synchronization.
VREF
8
R
BIAS
RT
R
4
EXTERNAL
SYNC INPUT
OSC
CT
0.01F
2R
47
EA
5
D95IN352
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of CT to go more than 300mV below ground
Figure 23: External Duty Cycle Clamp and Multi Unit Synchronization.
VREF
RA
RB
5K
5
5K
4
+
Q
+
R
3
BIAS
5K
NE555
OSC
2R
+
-
EA
1
5
f=
1.44
(RA + 2RB)C
Dmax =
RB
TO ADDITIONAL
UCX84XAs
D95IN353
RA + 2RB
11/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
Figure 24: Soft-Start Circuit
5Vref
R
+
BIAS
R
4
OSC
1mA
2R
1M
+
EA
1V
1
C
5
D95IN354
Figure 25: Soft-Start and Error Amplifier Output Duty Cycle Clamp.
VCC
Vin
5Vref
R
+
BIAS
R
4
VClamp
1mA
2
R2
EA
Q1
2R
+
-
OSC
1V
Comp/Latch
5
R1
RS
BC109
VCLAMP =
12/15
R1
R1 + R 2
Ipk(max) =
VCLAMP
RS
D95IN355
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.25
a2
MAX.
0.069
0.004
0.010
1.65
0.065
a3
0.65
0.85
0.026
0.033
0.35
0.48
0.014
0.019
b1
0.19
0.25
0.007
0.010
0.25
0.5
0.010
0.020
c1
45 (typ.)
D (1)
4.8
5.0
0.189
0.197
5.8
6.2
0.228
0.244
1.27
e3
0.050
3.81
0.150
F (1)
3.8
4.0
0.15
0.157
0.4
1.27
0.016
0.050
M
S
OUTLINE AND
MECHANICAL DATA
0.6
0.024
SO8
8 (max.)
13/15
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
mm
DIM.
MIN.
A
TYP.
inch
MAX.
MIN.
3.32
TYP.
MAX.
0.131
a1
0.51
1.15
1.65
0.045
0.065
0.356
0.55
0.014
0.022
b1
0.204
0.304
0.008
0.012
0.020
D
E
10.92
7.95
9.75
0.430
0.313
0.384
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
6.6
0.260
5.08
0.200
L
Z
14/15
3.18
OUTLINE AND
MECHANICAL DATA
3.81
1.52
0.125
0.150
0.060
Minidip
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics Printed in Italy All Rights Reserved
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15/15