06 Seq

Sequential logic
Sequential circuits
q
q
q
q
q
outputs = f(inputs, past inputs, past outputs)

basis for building "memory" into logic circuits
door combination lock is an example of a sequential circuit
n
cascading flip-flops for proper operation

clock skew
n
n
state is memory
state is an "output" and an "input" to combinational logic
combination storage elements are also memory
new
C1
C2
multiplexer
shift registers
simple counters
reset
C3
mux
control
comb. logic
state
comparator
clock
Hardware description languages and sequential logic

equal
VI - Sequential Logic
Copyright 2004, Gaetano Borriello and Randy H. Katz
Circuits with feedback

n
equal
value
metastability and synchronization
Basic registers
q
Circuits with feedback

q
Asynchronous inputs
q
simple circuits with feedback

latches
edge-triggered flip-flops
Timing methodologies
q
Sequential circuits
open/closed
2
Simplest circuits with feedback
How to control feedback?

q
what stops values from cycling around endlessly
Two inverters form a static memory cell

q
will hold value as long as it has power applied

"1"
X1
X2
Xn
"stored value"
switching
network
Z1
Z2
Zn
"0"
How to get a new value into the memory cell?

q
q
selectively break feedback path

load new value into cell
"remember"
"data"
"load"
"stored value"
4
Memory with cross-coupled gates

n
Cross-coupled NOR gates

q
similar to inverter pair, with capability to force output to 0

(reset=1) or 1 (set=1)
R
Q'
R
S
Timing behavior
Reset
Cross-coupled NAND gates

q
similar to inverter pair, with capability to force output to 0

(reset=0) or 1 (set=0)
S'
S'
Q'
Set
Reset
Q'
R'
\Q
5
Q'
Q
hold
0
1
unstable
Theoretical R-S latch behavior
SR=00
SR=01
Q Q'
1 0
SR=01
Q Q'
0 1
SR=01
Q'
Q Q'
0 0
SR=00
SR=10
SR=10
State diagram
q
states: possible values

transitions: changes
based on inputs
SR=11
SR=01
Q Q'
1 1
Q Q'
1 0
SR=11
SR=10
Q Q'
0 1
R
0
1
0
1
Race
100
Truth table of R-S latch behavior
S
0
0
1
1
Set
State behavior or R-S latch

n
R'
Hold
possible oscillation
between states 00 and 11
7
Q Q'
0 0
SR=11
SR=00
SR=11
SR=00
SR=10
Q Q'
1 1
Observed R-S latch behavior
Q'
Very difficult to observe R-S latch in the 1-1 state
R-S latch analysis

Break feedback path
one of R or S usually changes first
Ambiguously returns to state 0-1 or 1-0
q
q
a so-called "race condition"

or non-deterministic transition
SR=01
Q Q'
0 1
SR=01
Q Q'
1 0
SR=00
SR=10
S
0
0
0
0
1
1
1
1
SR=10
SR=11
Q Q'
0 0
SR=11
SR=11
SR=00
SR=00
9
Activity: R-S latch using NAND gates
Q'
S
0
0
0
0
1
1
1
1
R
0
0
1
1
0
0
1
1
S
1
1
1
1
0
0
0
0
R
1
1
0
0
1
1
0
0
Q(t)
0
1
0
1
0
1
0
1
Q(t+)
0
1
0
0
1
1
X
X
Q(t)
Q(t+)
hold
Q(t)
set
not allowed
Q(t)
R
characteristic equation
Q(t+) = S + R Q(t)
10
otherwise, the
slightest glitch on R
or S while enable is
low could cause
change in value
stored
R'
enable'
Q'
S'
Set
100
Reset
S'
R'
enable'
Q(t+) = S + R Q(t)
Q(t+)
0
hold
1
0
reset
0
1
set
1
X not allowed
X
Control when R and

S inputs matter
R
S
reset
Q(t)
0
1
0
1
0
1
0
1
Gated R-S latch
Q(t)
Q'
R
0
0
1
1
0
0
1
1
SR=10
SR=00
SR=01
Q
Q'
11
12
Clocks
n
Used to keep time

q
q
Clocks (contd)
n
wait long enough for inputs (R' and S') to settle

then allow to have effect on value stored
Clocks are regular periodic signals

q
q
Controlling an R-S latch with a clock

q
period (time between ticks)

duty-cycle (time clock is high between ticks - expressed as % of
period)
can't let R and S change while clock is active (allowing R and S to

pass)
only have half of clock period for signal changes to propagate
signals must be stable for the other half of clock period
R
clock
duty cycle (in this case, 50%)
S
stable changing stable changing stable
R and S
period
clock
13
Cascading latches
n
n
q
q
Break flow by alternating clocks (like an air-lock)

q
need to be able to control flow of data from one latch to the next
move one latch per clock period
have to worry about logic between latches (arrows) that is too fast
R
S
Q
Q
R
S
use positive clock to latch inputs into one R-S latch

use negative clock to change outputs with another R-S latch
View pair as one basic unit

q
14
Master-slave structure
Connect output of one latch to input of another

How to stop changes from racing through chain?
q
master-slave flip-flop
twice as much logic
output changes a few gate delays after the falling edge of clock
but does not affect any cascaded flip-flops
slave stage
master stage
Q
Q
clock
CLK
15
16
The 1s catching problem

n
D flip-flop
In first R-S stage of master-slave FF

q
q
Set
Reset
1s
catch
q
q
slave stage
master stage
R
P
P
q
q
eliminates 1s catching problem

can't just hold previous value
(must have new value ready every clock period)
value of D just before clock goes low is what is stored in flip-flop
can make R-S flip-flop by adding logic to make D = S + R Q
CLK
P
P
Q
Q
slave stage
master stage
CLK
S
R
Master
Outputs
CLK
Slave
Outputs
10 gates
17
Edge-triggered flip-flops
n
Make S and R complements of each other
0-1-0 glitch on R or S while clock is high is "caught" by master stage

leads to constraints on logic to be hazard-free
holds D when
clock goes low
0
R
Clk=1
Q
Step-by-step analysis
D
sensitive to inputs only near edge of clock signal (not while high)
18
Edge-triggered flip-flops (contd)
More efficient solution: only 6 gates

q
negative edge-triggered D
flip-flop (D-FF)
4-5 gate delays

must respect setup and hold time
constraints to successfully
capture input
D
R
Clk=0
Clk=0
S
S
D
0
holds D when
clock goes low
D
D
D
Q(t+1) = D
19
new D
new D old D
when clock is low

when clock goes high-to-low
is latched Copyright 2004, Gaetano Borriello and Randy H. Katz data is held
data
20
Edge-triggered flip-flops (contd)

n
Positive edge-triggered
q
n
inputs sampled on rising edge; outputs change after rising edge
Negative edge-triggered flip-flops

q
Rules for interconnecting components and clocks

q
inputs sampled on falling edge; outputs change after falling edge
we'll focus on systems with edge-triggered flip-flops
many custom integrated circuits focus on level-sensitive latches
100
D
CLK
Qpos
positive edge-triggered FF
Qneg
negative edge-triggered FF
Qneg
21
Timing methodologies (contd)

n
periodic event, causes state of memory element to change

can be rising edge or falling edge or high level or low level
setup time: minimum time before the clocking event by which the
input must be stable (Tsu)
hold time: minimum time after the clocking event until which the
input must remain stable (Th)
data
D Q
CLK
positive
edge-triggered
flip-flop
D Q
G
clock
clock
there is a timing "window"

around the clocking event
during which the input must
remain stable and unchanged
in order to be recognized
22
D
CLK
Qedge
D Q
input
D Q
clock:
Tsu Th
(1) correct inputs, with respect to time, are provided to the flipflops
(2) no flip-flop changes state more than once per clocking event
Comparison of latches and flip-flops
Definition of terms
q
found in programmable logic devices
Basic rules for correct timing:

q
Qpos
guarantee proper operation of system when strictly followed
Approach depends on building blocks used for memory

elements
Qlatch
CLK
stable changing
transparent
(level-sensitive)
latch
data
clock
23
behavior is the same unless input changes

while the clock is high
24
Comparison of latches and flip-flops (contd)
Typical timing specifications

n
Positive edge-triggered D flip-flop
Type
When inputs are sampled When output is valid
unclocked
latch
always
level-sensitive
latch
clock high
(Tsu/Th around falling
edge of clock)
propagation delay from input change

or clock edge (whichever is later)
master-slave
flip-flop
clock high
edge of clock)
propagation delay from falling edge

of clock
negative
edge-triggered
flip-flop
clock hi-to-lo transition

edge of clock)
propagation delay from falling edge

of clock
Clk
propagation delay from input change
q
q
setup and hold times

minimum clock width
propagation delays (low to high, high to low, max and typical)
Tsu
Th
1.8
ns
0.5
ns
Tsu
Th
1.8
ns
0.5
ns
Tw
3.3
ns
Tw
3.3
ns
Tpd
3.6 ns
1.1 ns
Tpd
3.6 ns
1.1 ns
all measurements are made from the clocking event (the rising edge of the clock)
25
Cascading edge-triggered flip-flops

n
q
q
IN
new value goes into first stage

while previous value of first stage goes into second stage
consider setup/hold/propagation delays (prop must be > hold)
D Q
Q0
D Q
Q1
q
q
propagation delays exceed hold times

clock width constraint exceeds setup time
this guarantees following stage will latch current value before it
changes to new value
In
Q0
100
Tsu
1.8ns
Tsu
1.8ns
Tp
1.1-3.6ns
Tp
1.1-3.6ns
assumes infinitely fast

distribution of the clock
Q0
CLK
Q1
CLK
timing constraints
guarantee proper
operation of
cascaded components
Q1
IN
26
Why this works

q
OUT
CLK
Cascading edge-triggered flip-flops (contd)
Shift register
q
Th
0.5ns
27
Th
0.5ns
28
Clock skew
n
Summary of latches and flip-flops
The problem
q
correct behavior assumes next state of all storage elements

determined by all storage elements at the same time
this is difficult in high-performance systems because time for clock
to arrive at flip-flop is comparable to delays through logic
effect of skew on cascaded flip-flops:
q
q
q
CLK0
CLK1
can be made with 4 switches
edge-triggered used in programmable logic devices

good choice for data storage register
Historically J-K FF was popular but now never used

q
CLK1 is a delayed
version of CLK0
Q0
Q1
level-sensitive used in custom integrated circuits

n
100
In
Development of D-FF
q
similar to R-S but with 1-1 being used to toggle output (complement state)
good in days of TTL/SSI (more complex input function: D = J Q + K Q
not a good choice for PALs/PLAs as it requires 2 inputs
can always be implemented using D-FF
Preset and clear inputs are highly desirable on flip-flops

q
used at start-up or to reset system to a known state
original state: IN = 0, Q0 = 1, Q1 = 1
due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1
29
Metastability and asynchronous inputs

n
inputs, state, and outputs sampled or changed in relation to a

common reference signal (called the clock)
e.g., master/slave, edge-triggered
30
Occurs when FF input changes close to clock edge

q
q
q
the FF may enter a metastable state neither a logic 0 nor 1

it may stay in this state an indefinite amount of time
this is not likely in practice but has some probability
Asynchronous circuits
q
Synchronization failure
Clocked synchronous circuits

q
logic 1
inputs, state, and outputs sampled or changed independently of a

common reference signal (glitches/hazards a major concern)
e.g., R-S latch
Asynchronous inputs to synchronous circuits

q
q
q
inputs can change at any time, will not meet setup/hold times
dangerous, synchronous inputs are greatly preferred
cannot be avoided (e.g., reset signal, memory wait, user input)
logic 0
31
logic 1
small, but non-zero probability

that the FF output will get stuck
in an in-between state
logic 0
oscilloscope traces demonstrating
synchronizer failure and eventual
decay to steady state
32
Dealing with synchronization failure

n
Handling asynchronous inputs
Probability of failure can never be reduced to 0, but it can be reduced

q
(1) slow down the system clock

this gives the synchronizer more time to decay into a steady state;
synchronizer failure becomes a big problem for very high speed systems
(2) use fastest possible logic technology in the synchronizer
this makes for a very sharp "peak" upon which to balance
(3) cascade two synchronizers
this effectively synchronizes twice (both would have to fail)
Never allow asynchronous inputs to fan-out to more than one flip-flop

q
synchronize as soon as possible and then treat as synchronous signal
Clocked
Synchronous
System
Async
Input
Synchronizer
Q0
D Q
Async
Input
D Q
Clock
Clock
asynchronous
input
Q1
D Q
synchronized
input
Q1
D Q
Clock
Clock
Clk
Q0
D Q
synchronous system
33
Handling asynchronous inputs (contd)

n
input changes too close to clock edge (violating setup time

constraint)
Q1
In is asynchronous and
fans out to D0 and D1
inconsistent state may

be reached!
35
Dnew = R' Dold + S

Dnew = R' Dold + R'S
(set-dominant)
(reset-dominant)
Selective input capability (input enable or load) LD or EN

q
CLK
synchronous: Dnew = Dold + S (when next clock edge arrives)

asynchronous: doesn't wait for clock, quick but dangerous
Both reset and preset

q
one FF catches the

signal, one does not
synchronous: Dnew = R' Dold (when next clock edge arrives)

asynchronous: doesn't wait for clock, quick but dangerous
Preset or set (set state to 1) S (or sometimes P)

q
Q0
34
Reset (set state to 0) R

q
In
Flip-flop features
What can go wrong?

q
multiplexor at input: Dnew = LD' Q + LD Dold

load may or may not override reset/set (usually R/S have priority)
Complementary outputs Q and Q'
36
Registers
n
Collections of flip-flops with similar controls and logic

q
q
q
Shift register
n
stored values somehow related (for example, form binary value)

share clock, reset, and set lines
similar logic at each stage
Holds samples of input

q
q
store last 4 input values in sequence

4-bit shift register:
Examples
q
q
OUT1
shift registers
counters
OUT1
OUT2
OUT3
OUT4
IN
"0"
D Q
D Q
OUT2
OUT3
D Q
OUT4
D Q
CLK
R S
R S
R S
R S
D Q
D Q
D Q
D Q
CLK
IN1
IN2
IN3
IN4
37
Universal shift register

n
q
q
q
serial or parallel inputs

serial or parallel outputs
permits shift left or right
shift in new values from left or right
Consider one of the four flip-flops

q
new value at next clock cycle:
right_out
right_in
clock
input
clear
1
0
0
0
0
s0
0
0
1
1
s1
0
1
0
1
new value
0
output
output value of FF to left (shift right)
output value of FF to right (shift left)
input
Nth cell
output
left_in
left_out
clear
s0
s1
38
Design of universal shift register
Holds 4 values
q
to N-1th
cell
clear sets the register contents

and output to 0
to N+1th
cell
Q
D
CLK
s1 and s0 determine the shift function

s0
0
0
1
1
s1
0
1
0
1
function
hold state
shift right
shift left
load new input
CLEAR
0 1 2 3 s0 and s1
control mux
Q[N-1]
(left)
39
Input[N]
Q[N+1]
(right)
40
10
Shift register application

n
Pattern recognizer
Parallel-to-serial conversion for serial transmission
Combinational function of input samples

q
parallel outputs
in this case, recognizing the pattern 1001 on the single input

signal
OUT
OUT1
OUT2
OUT3
OUT4
parallel inputs
D Q
IN
serial transmission
41
Counters
n
D Q
42
How does this counter work?
in this case, 1000, 0100, 0010, 0001

if one of the patterns is its initial state (by loading or set/reset)
OUT1
IN
OUT1
IN
D Q
Activity
Sequences through a fixed set of patterns

q
D Q
CLK
D Q
D Q
OUT2
OUT3
D Q
D Q
D Q
OUT2
D Q
OUT3
OUT4
D Q
CLK
OUT4
D Q
Counts through the sequence: 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000
CLK
Known as Mobius (or Johnson) counter
43
44
11
Binary counter
n
Four-bit binary synchronous up-counter
Logic between registers (not just multiplexer)

q
q
XOR decides when bit should be toggled

always for low-order bit,
only when first bit is true for second bit,
and so on
OUT1
D Q
OUT2
D Q
Standard component with many applications

q
q
q
q
OUT3
D Q
positive edge-triggered FFs w/ synchronous load and clear inputs

parallel load data from D, C, B, A
enable inputs: must be asserted to enable counting
EN
RCO: ripple-carry out used for cascading counters
n
OUT4
high when counter is in its highest state 1111

implemented using an AND gate
(2) RCO goes high
D Q
CLK
D
C
B
A
RCO
QD
QC
LOAD QB
QA
CLK
CLR
(3) High order 4-bits

are incremented
(1) Low order 4-bits = 1111
"1"
45
Offset counters
n
"1"
e.g., 0110, 0111, 1000, 1001,

1010, 1011, 1100, 1101, 1111, 0110, . . .
"0"
"1"
"1"
"0"
"0"
46
EN
RCO
QD
D
QC
C
QB
B
QA
A
LOAD
CLK
CLR
Flip-flops
q
q
n
n
representation of clocks - timing of state changes

asynchronous vs. synchronous
Shift registers
Simple counters
Ending offset counter comparator for ending value

q
Hardware Description Languages and Sequential

Logic
Starting offset counters use of synchronous load

q
e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000
Combinations of the above (start and stop value)
"1"
EN
"0"
"0"
"0"
"0"
D
C
B
A
LOAD
CLK
CLR
RCO
QD
QC
QB
QA
47
48
12
Flip-flop in Verilog
n
More Flip-flops
Use always block's sensitivity list to wait for clock edge
Synchronous/asynchronous reset/set
single thread that waits for the clock
three parallel threads only one of which waits for the clock
q
q
module dff (clk, d, q);
Synchronous
input clk, d;
output q;
reg
q;
module dff
input
output
reg
always @(posedge clk)

q = d;
(clk, s, r, d, q);
clk, s, r, d;
q;
q;
Asynchronous
module dff
input
output
reg

if (r)
q = 1'b0;
else if (s) q = 1'b1;
else
q = d;
endmodule
(clk, s, r, d, q);
clk, s, r, d;
q;
q;
always @(posedge r)
q = 1'b0;
always @(posedge s)
q = 1'b1;
q = d;
endmodule
endmodule
49
Incorrect Flip-flop in Verilog

n
Blocking assignments (X=A)
Non-blocking assignments (X<=A)
module dff (clk, d, q);
always @(clk)
q = d;
Not correct! Q will

change whenever the
clock changes, not
just on an edge.
completes the assignment before continuing on to next statement

completes in zero time and doesnt change the value of the
target until a blocking point (delay/wait) is encountered
Example: swap
always @(posedge CLK)
begin
temp = B;
B = A;
A = temp;
end
endmodule
50
Blocking and Non-Blocking Assignments
Use always block's sensitivity list to wait for clock to change
input clk, d;
output q;
reg
q;
51
always @(posedge CLK)

begin
A <= B;
B <= A;
end
52
13
Register-transfer-level (RTL) Assignment

n
Mobius Counter in Verilog

initial
begin
A =
B =
C =
D =
end
Non-blocking assignment is also known as an RTL assignment

q
q
if used in an always block triggered by a clock edge

all flip-flops change together
// B,C,D all get the value of A

begin
B = A;
C = B;
D = C;
end

begin
A <= ~D;
B <= A;
C <= B;
D <= C;
end
// implements a shift register too

begin
B <= A;
C <= B;
D <= C;
end
1b0;
1b0;
1b0;
1b0;
53
Binary Counter in Verilog
Sequential logic summary
module binary_counter (clk, c8, c4, c2, c1);
input clk;
output c8, c4, c2, c1;
input clk;
output c8, c4, c2, c1, rco;
reg [3:0] count;
reg [3:0] count;

reg rco;
=
=
=
=
endmodule
count[3];
count[2];
count[1];
count[0];
initial begin . . . end
always @(posedge clk) begin . . . end

assign
assign
assign
assign
assign
synchronizer failure: what it is and how to minimize its impact
Basic registers
q
q
use of clocks
cascaded FFs work because propagation delays exceed hold times
beware of clock skew
Asynchronous inputs and their dangers

q
c8 = count[3];
c4 = count[2];
c2 = count[1];
c1 = count[0];
rco = (count == 4b1111);
latch and flip-flop

R-S latch, R-S master/slave, D master/slave, edge-triggered D flip-flop
always @(posedge clk) begin

count = count + 4b0001;
end
c8
c4
c2
c1
initial begin
count = 0;
end
assign
assign
assign
assign
Fundamental building block of circuits with state

q
module binary_counter (clk, c8, c4, c2, c1, rco);
54
shift registers
counters
Hardware description languages and sequential logic
endmodule
55
56
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Sequential logic

outputs = f(inputs, past inputs, past outputs)

cascading flip-flops for proper operation

Hardware description languages and sequential logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

Circuits with feedback

metastability and synchronization

Circuits with feedback

simple circuits with feedback

Copyright 2004, Gaetano Borriello and Randy H. Katz

Simplest circuits with feedback

How to control feedback?

what stops values from cycling around endlessly

Two inverters form a static memory cell

will hold value as long as it has power applied

How to get a new value into the memory cell?

selectively break feedback path

Copyright 2004, Gaetano Borriello and Randy H. Katz

Copyright 2004, Gaetano Borriello and Randy H. Katz

Memory with cross-coupled gates

Cross-coupled NOR gates

similar to inverter pair, with capability to force output to 0

Cross-coupled NAND gates

similar to inverter pair, with capability to force output to 0

Copyright 2004, Gaetano Borriello and Randy H. Katz

Theoretical R-S latch behavior

states: possible values

Copyright 2004, Gaetano Borriello and Randy H. Katz

Copyright 2004, Gaetano Borriello and Randy H. Katz

Truth table of R-S latch behavior

State behavior or R-S latch

Copyright 2004, Gaetano Borriello and Randy H. Katz

Observed R-S latch behavior

Very difficult to observe R-S latch in the 1-1 state

R-S latch analysis

one of R or S usually changes first

Ambiguously returns to state 0-1 or 1-0

a so-called "race condition"

Copyright 2004, Gaetano Borriello and Randy H. Katz

Activity: R-S latch using NAND gates

Copyright 2004, Gaetano Borriello and Randy H. Katz

Copyright 2004, Gaetano Borriello and Randy H. Katz

Control when R and

Gated R-S latch

Copyright 2004, Gaetano Borriello and Randy H. Katz

Used to keep time

wait long enough for inputs (R' and S') to settle

Clocks are regular periodic signals

Controlling an R-S latch with a clock

period (time between ticks)

can't let R and S change while clock is active (allowing R and S to

duty cycle (in this case, 50%)

Copyright 2004, Gaetano Borriello and Randy H. Katz

Break flow by alternating clocks (like an air-lock)

use positive clock to latch inputs into one R-S latch

View pair as one basic unit

Copyright 2004, Gaetano Borriello and Randy H. Katz

Connect output of one latch to input of another

Copyright 2004, Gaetano Borriello and Randy H. Katz

Copyright 2004, Gaetano Borriello and Randy H. Katz

The 1s catching problem

In first R-S stage of master-slave FF

eliminates 1s catching problem