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I

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FDD project
1.Add script dc.tcl
/tools/synopsys/syn_vJ-2014.09-SP5-2/libraries/syn/dft_jtag.sldb \
/tools/synopsys/syn_vJ-2014.09-SP5-2/libraries/syn/dft_lbist.sldb \
/tools/synopsys/syn_vJ-2014.09-SP5-2/libraries/syn/dft_mbist.sldb \
/tools/synopsys/syn_vJ-2014.09-SP5-2/libraries/syn/dw_foundation.sldb \
/tools/synopsys/syn_vJ-2014.09-SP5-2/libraries/syn/standard.sldb \
2.Name of library in PERSEUS config
1.9 lib: -library_name fdd_mem_v1p9
2.1 lib: -library_name fdd_mem_v2p1
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Test system
ustat --> u
Delete all job
qdel -u quangt
ures | grep quangt
qhost
/tools/synopsys/scl_v11.9/amd64/bin/lmstat -a -c 27000@a2x16-02 -f PrimeTime : c
heck primetime license.
du -sh *: chek storage current folder
ssh -X login05
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Run tools
/tools/.cshrc.lic
module load synopsy
-lic_queue 1500: wait license
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WinSCP
FTP
Host: vn-i2x16-01 --> 172.16.37.11
172.16.5.1-5
user: quangt
password: system pass
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Back up data
qlogin -l h=vn-i2x144-01
cd /mnt/net/backups/vault2/asic
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Copy from vn to us
rsync -a --stats --progress vn_file login01:/home/quangt
Copy from us to vn
rsync -a --stats --progress us_file login01:/home/quangt
sftp a4x128-01 --> password
1. to get file from us
get $us_link $vn_link
2. to send file to us
put $vn_link $us_link
ftp 172.16.37.11
Name: quangt
Pass: ****
copy: get file > home directory of macbook
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grep "nameofstring" director

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dc_synth
.vh vs .v la verilog
.sv la sverilog
.vhd la vhdl
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Floorlan
1. Remove TAP cell and CAP cell
selectInst NameCell
deleteSelectedFromFPlan
saveFFPlan name.fp
addHaloBlock {2 2 2 2} -allBlock
createRouteBlk -box 1046.7800 1575.0000 1070.4400 1651.8600 -layer {layreIdlist}
| all
deleteRouteBlk -all
deleteAllPowerPreroutes
setPreference EnlargeLogicalPin 1Al
saveIoFile file.tcl
set a 0; set area 0; foreach a [ dbGet top.insts.area ] {set area [expr $a+$area
]}; puts $area
createInstGroup GR0222 -fence 2312.276 1042.452 2466.260 972.135 --> create regi
on group
addInstToInstGroup GR0222 C1C2_wrapper_Wrapper_inst/C1C2_wrapper_dmc_mpr_interr
upt_q_Q0_wrp0_1418/U6 --> add inst to group
selectObjByProp Instance <Type>=<Block> > select all of blocks
selectObjByProp Pin {And(<Type>=<I/O Pin>,!<Status>=<Placed><layer>=<M2>)} > select
all of pins (placed/M2)
selectObjByProp Module {OR(<Constraint Type>=<Fence>,<Constraint Type>=<Region>)
} > select all of region/fence
runN2NOpt -effort high -inDir n2n.input -outDir n2n.output -report all -saveToDe
signName ./dbs/soc_ddr_wrapper.enc.floorplan -insertClockGating -incrFirst high
-multiMode -preserveClockNetsAll > opt netlist
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Placement
setLayerPeference -congestH -isVisible 1
setLayerPeference -congestV -isVisible 1
gte_property [get_cells nameofcell]
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Formality:
analyze_points -failing/-all
report_analysis_results -summary
set_constant i:/WORK/namofpoint 0/1
report_undriven_nets
set verification_
set_dont_verify -directly_undriven_output
set_constant -type net ref:/WORK/C3/cas_fc_out 1
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Cts:
resolve skew clock at cts step
ClkGroup
+
+
resolve crossover and reconvergence
GlobalLeafPin
+
+
LeafPinGroup nameof group
+ +

There are other CP pins in the clock path that might be seen as a leafPin when i
t should be a through pin.
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Route:
report_timing -machine_readable -from -to >kaka
load_timing_debug_reprt -name
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ECO:
selectObject Module C1C2_Q0/u_C1/fmc/cpu
unplaceGuide C1C2_Q0/u_C1/fmc/cpu
setAttribute -net NETNAME -non_default_rule rule_ndr_2w2s
setNanoRouteMode -routeSelectedNetOnly
set_interactive_constraint_modes func
selectNet NETNAME
globalDetailRoute -select
set_dont_touch NETNAME true

true

setNanoRouteMode -routeSelectedNetOnly

false

#############
# COMMAND EDI
#############
dbGet [dbGet top.insts.cell.baseClass block -p2].name #get macro name
dbForEachCellInst [dbgTopCell] inst {set name [dbInstCellName $inst]; if {[dbIsC
ellBlock
\
$name]} {puts $name}}
dbGet top.hInst.hInsts.name #get module name
setInstancePlacementStatus -allHardMacros -status fixed #fixed macro
createFence #~ create_plan_group
createRegion #~ create_bounds -type hard
createGuide #~ create_bounds -type soft
ecoAddRepeater #~ insert_buffer
ecoChangeCell #~ size_cell
all_setup/hold_analysis_view #~
get_equivalent_cells #~ get_alternative_cells
get_property [get_cells inst_pb_rams_gen_ram_repair_12__inst_ram_repair_register
_reg_addr_reg_12_] ref_name #~ get_attribute
#############

# COMMAND ICC
#############
change_selection [get_port [get_attribute [get_clock] sources]]
create_bounds -name bound_cmptop -coordinate { 597.4900 536.0050 982.4750 1247.
6400 } -type soft {"mac2/cmp_top/*"} -cycle_color
create_bounds -name clk -coordinate {940 2343 1569 2647} -type hard "mac3/mac_to
p3_common/mac_top3_reset_clock/* mac2/mac_common/mac_reset_clock/*"
create_bounds -name clk -coordinate {870.7600 3391.8500 898.7600 3402.8500} -typ
e hard {mac2/sgp_top/sgp/i_sgp_jtck_scan_mux/clk_mx2_clkcell mac2/cmp_top/cmp/i_
cmp_jtck_scan_mux/clk_mx2_clkcell g416 g2829 mac2/mac_common/mac_reset_clock/i_s
gp_gclk/
RC_CG_HIER_INST5876/main_gate_clkcell mac2/mac_common/mac
_reset_clock/i_cmp_gclk/RC_CG_HIER_INST5870/main_gate_clkcell}

alias fp "source /mnt/net/vault1/asic/proj/sigma/golan3/script/common/icc/icc_cr


eate_pg_mesh.golan.tcl; create_fp_placement; route_zrt_global -congestion_map_on
ly true -exploration true"
cat cts_opt_ccd.prects_structure_temp | grep SINK | awk '{print $2}'
change_selection [get_pin -of [get_selection ] -filter full_name=~*Q*]
cat /mnt/net/vault1/asic/proj/agilent/insight/build/silver003/mem/perseus_lanh/s
oc_pnr/output/mem.v.floorplan.hier | awk '{if($1~"module" && $2=="HMCmemoryContr
oller"){flag=1} else if ($1~"endmodule") {flag=0}; if(flag==0){print}}' > mem.v.
floorplan.hier.edit1
insert_buffer clk SEL_BUF_24 -location {115 3566}
insert_buffer eco_cell/X SEL_BUF_24 -location {544 3565}
insert_buffer eco_cell_0/X SEL_BUF_24 -location {544 3133}
insert_buffer eco_cell_1_0/X SEL_BUF_24 -location {544 2668}
insert_buffer eco_cell_2_0/X SEL_BUF_24 -location {1200 2668}
set_dont_touch [get_cells "eco_cell*"]
set_dont_touch_network [get_pins eco_cell/A]
set_dont_touch_network [get_pins "eco_cell*/X"]
set_dont_touch_placement [get_cells "eco_cell*"]
set ports_clock_root {}
foreach_in_collection a_clock [get_clocks -quiet] {
set src_ports [filter_collection [get_attribute $a_clock sources] @object_cl
ass==port]
set ports_clock_root [add_to_collection $ports_clock_root $src_ports]
}
set_false_path -from [remove_from_collection [all_inputs] $ports_clock_root]
set_false_path -to [all_outputs]
foreach_in_collection pin [get_pin [all_fanin -to [get_pin -hier tgmem/*] -start
points_only -flat ] -f max_rise_slack<0] {puts "[get_object_name $pin] [get_attr
ibute [get_pin [get_object_name $pin]] max_rise_slack]"}; #

> Create lib form EDI


Commands:
set_analysis_view -setup <view> -hold <view>
do_extract_model -lib_name <lib_name> <output_file_name> -view <view>
Example:
set_analysis_view -setup ff__1p210v_1p210v_m040c_func_cbest -hold ff__1p210v_1p
210v_m040c_func_cbest
do_extract_model -lib_name topaz.ff__1p210v_1p210v_m040c_func_cbest topaz.rout
e_opt.ff__1p210v_1p210v_m040c_func_cbest.lib -view ff__1p210v_1p210v_m040c_func_
cbest
setAttribute -net net1 -si_post_route_fix true
setNanoRouteMode -routeWithPostRouteFix true
globalDetailRoute