ADC LAB Updated MANUAL PDF

K.L.N.
COLLEGE OF ENGINEERING
POTTAPALAYAM - 6 3 0 6 1 2
(AN ISO 9001:2008 CERTIFIED INSTITUTION AFFILIATED TO
ANNA UNIVERSITY)
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
FOR III SEMESTER

Regulation 2013
EC6311-Analog and Digital Circuits Laboratory
PREPARED
M.AMUDHA
T.R.MUTHU
AP(Sr.Gr)/ECE
AP(Sr.Gr)/ECE
Academic Year: 2015-2016
INDEX
S.No
Date
Name of the Experiment
SYLLABUS
LIST OF EXPERIMENTS
LIST OF ANALOG EXPERIMENTS:
Page
No
Marks
Signature
1.
2.
3.
4.
5.
6.
7.
Half Wave and Full Wave Rectifiers, Filters, Power supplies

Frequency Response of CE, CB, CC and CS amplifiers
Darlington Amplifier
Differential Amplifiers- Transfer characteristic, CMRR Measurement
Cascode / Cascade amplifier
Class A and Class B Power Amplifiers
Spice Simulation of Common Emitter and Common Source amplifiers
LIST OF DIGITAL EXPERIMENTS

8. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa
9. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC
7483
10. Design and implementation of Multiplexer and De-multiplexer using logic gates
11. Design and implementation of encoder and decoder using logic gates
12. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple
counters
13. Design and implementation of 3-bit synchronous up/down counter
14. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops
TOTAL: 45 PERIODS
CIRCUIT DIAGRAM
Fig 1 Half Wave Rectifier without filter
Fig 2 Half Wave Rectifier with filter
Fig 3 Power Supply Using Bridge Rectifier
EX.NO:
DATE:
AIM
RECTIFIERS, FILTERS AND POWER SUPPLIES
(i) To construct a half wave rectifier with/ without capacitor filter. and to measure,
Ripple factor
Efficiency
Peak Inverse Voltage
(ii) Construct Power Supply Circuit and to measure constant DC Output
APPARATUS REQUIRED:
Diode, Transformer, Resistor, Capacitor, CRO, Multimeter, Bread Board, Connecting
wires.
THEORY
A rectifier is a circuit, which uses one or more diodes to convert A.C voltage into D.C
voltage. In this rectifier during the positive half cycle of the A.C input voltage, the diode is
forward biased and conducts for all voltages greater than the offset voltage of the semiconductor
material used. The voltage produced across the load resistor has same shape as that of the
positive input half cycle of A.C input voltage.
During the negative half cycle, the diode is reversing biased and it does not conduct. So
there is no current flow or voltage drop across load resistor. The net result is that only the
positive half cycle of the input voltage appears at the output.
The basic building blocks of a regulated dc power supply are a step down transformer,
rectifier, DC filter and regulator. Today almost every electronic device needs a dc supply for its
smooth operation and they need to be operated within certain power supply limits. This required
dc voltage or dc supply is derived from single phase ac mains. A regulated power supply can
convert unregulated an ac (alternating current or voltage) to a constant dc (direct current or
voltage). A regulated power supply is used to ensure that the output remains constant even if
the input changes. A regulated DC power supply is also called as a linear power supply.
FORMULA USED
2
Ripple factor,
Vrms Vdc
Where Vdc
Vdc
Vm
; Vrms
Vm
Pdc
Efficiency
Pac Vm
Vm
2
TABULATION
Measurement of Half-wave rectifier without filter & with filter
Input Signal
Output Signal
Without filter
Amplitude
(V)
Time period
(ms)
Amplitude
(V)
Time period
(ms)
With filter
Amplitude
(V)
Time period
(ms)
MODEL GRAPH
Fig 4 Input & Output waveform of Half-wave rectifier
PROCEDURE
HALF WAVE RECTIFIER
Test your transformer: Give 230V, 50Hz source to the primary coil of the transformer and
observe rated value at the secondary of the transformer by multimeter.
I. Without Capacitor
1. Connect the circuit diagram as shown in Fig 1.

2. Note down the output voltage using CRO. And plot it in the graph.
II. With Capacitor
4. Note down the output voltage in presence of capacitor using CRO. And plot it in the
graph.
POWER SUPPLY
2. Note down the output voltage using Multimeter.
RESULT
The half - wave rectifier and power supply circuit is designed and hooked up, Input Output waveform was drawn and following parameters was measured.
S. No
Parameters
1.
Ripple factor
2.
Efficiency
3.
Power supply- Output DC

voltage
CIRCUIT DIAGRAM:
Theoretical
Practical
EX.NO:
DATE:
COMMON EMITTER AMPLIFIER USING VOLTAGE DIVIDER BIAS
AIM:
To Design and implement the common emitter amplifier circuit for given specifications and
measures its gain & frequency response
APPARATUS REQUIRED:
Transistor (BC107), Resistors, Capacitors, AFO, CRO and RPS
THEORY:
Voltage divider bias (Self bias)
A combination of fixed and self-bias can be used to improve stability and at
the same time overcome some of the disadvantages of the other two biasing methods. One of the
most widely used combination-bias systems is the voltage-divider type. The voltage divider is
formed using external resistors R1 and R2. The voltage across R 2 forward biases the emitter
junction. By proper selection of resistors R1 and R2, the operating point of the transistor can be
made independent of . In this circuit, the voltage divider holds the base voltage fixed
independent of base current provided the divider current is large compared to the base current.
However, even with a fixed base voltage, collector current varies with temperature (for example)
so an emitter resistor is added to stabilize the Q-point. However, to provide long-term or dc
thermal stability, and at the same time, allow minimal ac signal degeneration, the bypass
capacitor is placed across R3. If bypass capacitor is large enough, rapid signal variations will not
change its charge materially and no degeneration of the signal will occur
DESIGN SPECIFICATION:
DESIGN:
(i) Selection of
Where
(ii) Selection of
(iii) Selection of
(iv) Selection of
Where
Where
MODEL GRAPH:
TABULATION:
Measurement for frequency response characteristics
Vin=
S.No
Frequency (Hz)
Output Voltage(V)
Gain 20 log
Vo
(dB)
Vin
PROCEDURE
I.Measurement for frequency response characteristics
1. Connect the circuit diagram as shown in Fig.
2. Set Input voltage (Vin) using AFO (signal generator). Keeping input voltage constant, vary the
frequency from 1Hz to 1MHz in regular steps.
3. Note down the corresponding output voltage.
4. Plot the graph: Gain (dB) Vs Frequency (Hz).
5. Calculate the Bandwidth from the frequency response graph.
II.Plotting the frequency response characteristics
6. The frequency response curve is plotted on a semi-log scale.
7. The mid- frequency voltage gain is calculated as times of Av max or -3 dB from Av max and
corresponding readings are noted.
8. The high frequency point is called the upper 3-dB point (f2).
9. The lower frequency point is called the lower 3-dB point (f1).
10. The difference between the upper 3-dB point and the lower 3-dB point in the frequency scale
gives the bandwidth of the amplifier. i.e Bandwidth = f2 - f1
11. Finally, calculate the Gain bandwidth product.
RESULT
Thus the common emitter amplifier with voltage divider bias is designed and its characteristics
are measured as,
Bandwidth (B.W.)
Maximum Voltage gain (Av)
3-dB Voltage gain (Av @ 3dB)
Gain Bandwidth product (GBW)
CIRCUIT DIAGRAM:
EX.NO:
DATE:
COMMON SOURCE AMPLIFIER
AIM:
To Design and implement the common source amplifier circuit using FET for given
specifications and measures its gain & frequency response
APPARATUS REQUIRED:
FET, Resistors, Capacitors, AFO, CRO and RPS

THEORY:
In common source amplifier circuit source terminal is made common to the other two
terminals. The coupling capacitors C1 and C2 are used to isolate the D.C biasing from the applied
ac signal, and acts as short circuit for the ac analysis. The CS amplifier which provides good
voltage amplification is most frequently used. In cascade amplifier input impedance of the
second stage acts as shunt across output of first stage and Rd is shunted by Ci. Since the
reactance decreases with increasing frequencies, the output impedance will be low at high
frequencies; this will result in decreasing the gain at high frequencies.
7,
f = 1 KHz,
DESIGN:
(i)Selection of
Where
(ii)Selection of
Where
Selection of
Where
Where
MODEL GRAPH:
TABULATION:
Vin=
S.No
Frequency (Hz)
Output Voltage(V)
Gain 20 log
Vo
(dB)
Vin
PROCEDURE

II. Plotting the frequency response characteristics
RESULT
Thus the common source amplifier is designed and its characteristics are measured as,
Bandwidth (B.W.)

CIRCUIT DIAGRAM:
:
:
VCC
R1
BC107
BC107
Cin
Vin
R2
RE
EX.NO:
DATE:
Co R
L
VO
DARLINGTON AMPLIFIER
AIM:
To Design and implement a Darlington amplifier circuit using BJT for given
specifications and measures its gain & frequency response
APPARATUS REQUIRED:
Transistor (BC107), Resistors, Capacitors, AFO, CRO and RPS
THEORY:
In some occasions, the current gain and input impedance often an emitter follower are
insufficient to meet the requirement. In order to increase, the overall values of circuit gain (Ai)
and the input impedance, two transistors are connected in series in emitter follower configuration
such a circuit is known as Darlington amplifier. Note that emitter of the first transistor is
connected to the base of the second transistor and the collector terminals of the two transistors
are connected together. The result is that emitter current of the first transistor is base current of
the second transistor. Therefore, the current gain of the pair is equal to product of individual
current gains. The current gain of Darlington emitter follower is much higher than the current
gain of the emitter follower. But the voltage gain is unity
In Darlington connection of transistors, emitter of the first transistor is directly connected
to the base of the second transistor .Because of direct coupling dc output current of the first stage
is (1+hfe )Ib1.If Darlington connection for n transistor is considered, then due to direct coupling
the dc output current for last stage is (1+hfe ) n times Ib1 .Due to very large amplification factor
even two stage Darlington connection has large output current and output stage may have to be a
power stage.
DESIGN:
(i) Selection of
(ii) Selection of
Now,
Let
(ii) Selection of
Where
TABULATION:
Vin=
S.No
Frequency (Hz)
Output Voltage(V)
Gain 20 log
Vo
(dB)
Vin
PROCEDURE

II.
Plotting the frequency response characteristics
RESULT
Thus the Darlington amplifier amplifier is designed and its characteristics are measured as,
Bandwidth (B.W.)
CIRCUIT DIAGRAM:
Measurement of Transfer characteristics:
Measurement of Differential gain (Ad )
Measurement of common mode gain (Ac )
EX.NO:
DATE:
DIFFERENTIAL AMPLIFIER
AIM:
To Design and implement a differential amplifier circuit using BJT for given
specifications and measure its CMRR& transfer characteristics
APPARATUS REQUIRED:
Transistor (BC107), Resistor, Capacitor, AFO, CRO and RPS
THEORY:
The differential amplifier is a basic stage of an integrated operational amplifier. It is used
to amplify the difference between 2 signals. It has excellent stability, high versatility and
immunity to noise. In a practical differential amplifier, the output depends not only upon the
difference of the 2 signals but also depends upon the common mode signal. Transistor Q1 and Q2
have matched characteristics. The values of R C1 and R C2 are equal. R E1 and R E2 are also
equal and this differential amplifier is called emitter coupled differential amplifier. The output is
taken between the two output terminals. For the differential mode operation the input is taken
from two different sources and the common mode operation the applied signals are taken from
the same source. Common Mode Rejection Ratio (CMRR) is an important parameter of the
differential amplifier.
Formula Used:
CMRR=20log (Ad/Ac) dB
Where
Ac=common mode output voltage/input voltage
Ad=differential mode output voltage/input voltage
DESIGN:
(i)Selection of
For the single ended output, the differential mode gain
(ii)Selection of
(iii)Calculation:
TABULATION:
Measurement for transfer characteristics
S.No
Input
Voltage(Vin)
Output Voltage(Vd1)
Output Voltage(Vd2)
TABULATION:
Measurement for CMRR
S.No
Frequency (Hz)
Output Voltage(V)
Gain 20 log
Vo
(dB)
Vin
PROCEDURE
CMMR
2. The input signal is applied to circuit and output signal is measured in CRO
PROCEDURE
Transfer characteristic
1. Connect the circuit diagram as shown in Fig
2. Using dual power supply vary the input voltage from -3vto+3v
3. Note down the corresponding output voltage vd1 and vd2
4. Plot the transfer characteristics
RESULT:
Thus the differential amplifier is designed and its characteristics are measured.
CIRCUIT DIAGRAM:
EX.NO:
DATE:
TWO STAGE RC COUPLED AMPLIFIER (CASCADE AMPLIFIER)
AIM:
To Design two stages RC coupled amplifier for given specifications circuit using BJT for
given specifications and measures its gain & frequency response.
APPARATUS REQUIRED:
Transistor (BC107), Resistor, Capacitor, AFO, CRO and RPS
THEORY:
The output from a single stage amplifier is usually insufficient to drive an o/p device. To
achieve more gain, the o/p of one stage is given as the input to the other stage which forms
multistage amplifier. If the two stages are coupled by R and C, then the amplifier is called RC
coupled amplifier. The performance of an amplifier can be determined from the following terms.
Gain:The gain is defined as ratio of output to input. The gain of multistage amplifier is equal to the product of gains of individual stages.
Frequency Response:At low frequencies (<50HZ) the reactance of coupling capacitor cc is high and hence very small
part of signal will pass from one stage to next stage. This increases the loading effect of next
stage and reduces the voltage gain. At high frequencies, capacitance reduces. Due to this base
emitter junction is low which increases the base current. This reduces the amplification factor. At
mid frequencies, the voltage gain of the amplifier is constant. In this range, as frequency
increases, reactance of CC reduces which tends to increase the gain. At the same time, lower
reactances means higher reactance of first stage and hence lower gain, these two factors cancel
each other resulting in a uniform gain at mid frequency
DESIGN:
For the Second stage:
(i) Selection of
Let
(ii) Selection of
(iii)Selection of
For the first stage:
(iv)
Selection of
Where
(v) Selection of
(vi)
Selection of
(vii) Selection of
Where
Where
MODEL GRAPH:
TABULATION:
Measurement for transfer characteristics
Vin=
S.No
Frequency (Hz)
Output Voltage(V)
Gain 20 log
Vo
(dB)
Vin
PROCEDURE
1. Connect the circuit diagram as shown in Fig
II.Plotting the frequency response characteristics

RESULT
Thus the two stages RC coupled amplifier amplifier is designed and its characteristics are
measured as,
Bandwidth (B.W.)
CIRCUIT DIAGRAM:
MODEL GRAPH
CLASS A POWER AMPLIFIER
AIM
To Design Class A power amplifier for given specifications and measures its efficiency
and maximum power.
APPARATUS REQUIRED:
Transistor (SL100), Power Meter, Resistor, Capacitor, AFO, CRO and RPS
THEORY
An input transducer signal is generally small (a few milli volts from a cassette or CD
input or a few micro volts from an antenna) and needs to be amplified sufficiently to operate an
output device (speaker or other power handling device). A voltage amplifier provides voltage
amplification primarily to increase the voltage of the input signal. Large-signal or power
amplifiers, on the other hand, primarily provide sufficient power to an output load to drive a
speaker or other power device, typically a few watts to tens of watts. The main features of a
large-signal amplifier are the circuit's power efficiency, the maximum amount of power that the
circuit is capable of handling, and the impedance matching to the output device.
Power amplifiers are mainly used to deliver more power to the load. To deliver more
power it requires large input signals, so generally power amplifiers are preceded by a series of
voltage amplifiers. In class-A power amplifiers, Q-point is located in the middle of DC-load line.
So output current flows for complete cycle of input signal. Under zero signal condition,
maximum power dissipation occurs across the transistor. As the input signal amplitude increases
power dissipation reduces. The maximum theoretical efficiency is 25%.
DESIGN:
(i) Selection of
(ii) Selection of
(iii)Selection of
TABULATION
Pin =
S.No
Frequency
(Hz)
Output Power
(V)
Gain = 20 log
Po
dB
Pin
PROCEDURE
I.
2. Set Input Voltage (Vin )using AFO (signal generator). Keeping input voltage constant,
vary the frequency from 1Hz to 1MHz in regular steps. Calculate the input power Pin.
3. Note down the corresponding output power Po.
RESULT
The class-A amplifier is designed, constructed and the output waveform is observed. The
maximum power gain and the efficiency are determined.
EX. NO:
DESIGN AND IMPLEMENTATION OF CODE CONVERTER
DATE:
AIM:
To design and implement 4-bit
(i)
Binary to gray code converter
Gray to binary code converter (iii)
i
i
(iv)
BCD to excess-3 code converter

Excess-3 to BCD code converter
APPARATUS REQUIRED:
S.No.
COMPONENT
SPECIFICATION
1.
2.
3.
4.
5.
X-OR GATE
AND GATE
OR GATE
NOT GATE
IC TRAINER KIT
IC 7486
IC 7408
IC 7432
IC 7404
-
6.
PATCH CORDS
QTY.
1
1
1
1
1
As per
Required
THEORY:
The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the
two systems if each uses different codes for same information. Thus, code converter is a circuit
that makes the two systems compatible even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses four bits to
represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted
code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible even though each uses a
different binary code. To convert from binary code to Excess-3 code, the input lines must supply
the bit combination of elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps represents one of the four
outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions derived
by the maps. These are various other possibilities for a logic diagram that implements this
circuit. Now the OR gate whose output is C+D has been used to implement partially each of three
outputs.
LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR
TRUTH TABLE:
Binary input
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Gray code output
B2
B1
B0
G3
G2
G1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
G0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
K-Map for G3:
G3 = B3
K-Map for G 2:
K-Map for G1:
K-Map for G0:
LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR
TRUTH TABLE:
|
Gray Code
Binary Code
G3
G2
G1
G0
B3
B2
B1
B0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
K-Map for B3:
B3 = G3
K-Map for B2:
K-Map for B1:
K-Map for B0:
LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR
TRUTH TABLE:
BCD input
Excess 3 output
B3
B2
B1
B0
G3
G2
G1
G0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
x
0
1
1
1
1
0
0
0
0
1
x
x
x
x
x
x
1
0
0
1
1
0
0
1
1
0
x
x
x
x
x
x
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
K-Map for E3 :
E3 = B3 + B2 (B0 + B1)
K-Map for E 2:
K-Map for E1:
K-Map for E0:
LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR
TRUTH TABLE:
Excess 3 Input
BCD Output
B3
B2
B1
B0
G3
G2
G1
G0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
K-Map for A:
A = X1 X2 + X3 X4 X1
K-Map for B:
K-Map for C:
K-Map for D:
PROCEDURE:
(i)
Connections were given as per circuit diagram.
(ii)
Logical inputs were given as per truth table
(iii)
Observe the logical output and verify with the truth tables.
RESULT:
Thus the different types of code converters are designed, and its truth tables are verified.
EXPT. NO:
:
DATE
DESIGN OF 4-BIT BINARY ADDER AND SUBTRACTOR&BCD ADDER
AIM:
To design and implement 4-bit adder and subtractor& BCD Adder using IC 7483.
APPARATUS REQUIRED:
S.No.
1.
2.
3.
3.
4.
COMPONENT
IC
EX-OR GATE
NOT GATE
IC TRAINER KIT
SPECIFICATION
IC 7483
IC 7486
IC 7404
-
PATCH CORD
QTY.
1
1
1
1
As per
Required
THEORY:
4 BIT BINARY ADDERS:
A binary adder is a digital circuit that produces the arithmetic sum of two binar y
numbers. It can be constructed with full adders connected in cascade, with the output carry from
each full adder connected to the input carry of next full adder in chain. The augends bits of A
and the addend bits of B are designated by subscript numbers from right to left, with subscript
0 d e n o t i n g the least significant bits. The carries are connected in chain through the full adder.
The input carry to the adder is C0 and it ripples through the full adder to the output carry C4.
4-BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed between each data
input B and the corresponding input of full adder. The input carry C0 must be equal to 1 when
performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one common
binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit.
When M=1, it becomes subtractor.
4 BIT BCD ADDERS:
Consider the arithmetic addition of two decimal digits in BCD, together with an input carry
from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater
than 19, the 1 in the sum being an input carry. The output of two decimal digits must be
represented in BCD and should appear in the form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits,
together with the input carry, are first added in the top 4 bit adder to produce the binary sum.
PIN DIAGRAM FOR IC 7483:
LOGIC DIAGRAM:
4-BIT BINARY ADDER
LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR
LOGIC DIAGRAM:
4-BIT BINARY ADDER/SUBTRACTOR
TRUTHTABLE:
Input Data A
Input Data B
Addition
A4 A3 A2 A1 B4 B3 B2 B1 C
1
1
1
Subtraction
S4 S3 S2 S1 B
D4 D3 D2 D1
BCD adder
PROCEDURE:
(i)Connections were given as per circuit diagram.
(ii)Logical inputs were given as per truth table
(iii)Observe the logical output and verify with the truth tables.
RESULT:
Thus the 4 bit binary adder and subtractor are designed and implemented
successfully using IC 7483
EX. NO:
DESIGN AND IMPLEMENTATION OF MULTIPLEXER

AND DEMULTIPLEXER
DATE:
AIM:
To design and implement multiplexer and demultiplexer using logic gates
APPARATUS REQUIRED:
S.No.
1
2
3
4
5
COMPONENT
3 I/P AND GATE
OR GATE
NOT GATE
IC TRAINER KIT
PATCH CORD
SPECIFICATION
IC 7411
IC 7432
IC 7404
-
QTY.
2
1
1
1
As per
Required
THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single output
line. The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input line and n selection lines whose bit combination determine
which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information
from one line and distributes it to a given number of output lines. For this reason, the
demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will
pass through the selected gate to the associated data output line.
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:
FUNCTION TABLE:
S1
S0
INPUTS Y
D0 D0 S1 S0
D1 D1 S1 S0
D2 D2 S1 S0
D3 D3 S1 S0
Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0
LOGIC DIAGRAM FOR MULTIPLEXER:
TRUTH TABLE:
S1
S0
Y = OUTPUT
D0
D1
D2
D3
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXERS:
FUNCTION TABLE:
S1
S0
INPUT
X D0 = X S1 S0
X D1 = X S1 S0
X D2 = X S1 S0
X D3 = X S1 S0
Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0
LOGIC DIAGRAM FOR DEMULTIPLEXER:
TRUTH TABLE:
INPUT
OUTPUT
S1
S0
I/P
D0
D1
D2
D3
LAB MANUAL/EC 6311-ANALOG AND DIGITAL CIRCUITS LAB
PROCEDURE:
(i)Connections are given as per circuit diagram.
(ii)Logical inputs are given as per circuit diagram.
(iii)Observe the output and verify the truth table.
RESULT:
Thus the Multiplexer and Demultiplexer is designed and its truth table verified
successfully
62
EX. NO. :
DATE:
AIM:
DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER
To design and implement encoder and decoder using logic gates and
studyof IC 7445 and IC 74147.
APPARATUS REQUIRED:
S.No.
1.
2.
3.
2.
3.
COMPONENT
3 I/P NAND GATE
OR GATE
NOT GATE
IC TRAINER KIT
PATCH CORDS
SPECIFICATION QTY.
IC 7410
2
IC 7432
3
IC 7404
1
1
27
THEORY:
ENCODER:
An encoder is digital circuits that perform inverse operation of a

decoder. An encoder has 2n input lines and n output lines. In encoder the
output lines generates the binary code corresponding to the input value. In
octal to binary encoder it has eight inputs, one for each octal digit and three
output that generate the corresponding binary code. In encoder it is assumed
that only one input has a value of one at any given time otherwise the circuit
is meaningless. It has an ambiguila that when all inputs are zero the outputs
are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuits which
converts coded input into coded output where input and output codes are
different. The input code generally has fewer bits than the output code. Each
input code word produces a different output code word i.e there is one to one
mapping can be expressed in truth table. In the block diagram of decoder
circuit the encoded information is present as n input producing 2n possible
63
outputs. 2n output values are from 0 through out 2n 1.

BCD TO DECIMAL
DECODER
64
LOGIC DIAGRAM FOR ENCODER:
TRUTH TABLE:
INPUT
OUTPUT
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1
65

LOGIC DIAGRAM FOR DECODER:
TRUTH TABLE:
INPUT
OUTPUT
D0
D1
D2
D3
66
PROCEDURE:
(i)
Connections are given as per circuit diagram.
(ii)
Logical inputs are given as per circuit diagram.
(iii)
Observe the output and verify the truth table.
RESULT:
Thus the Encoder and Decoder is designed and its truth table verified successfully
67
EX. NO.:
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS AND

ASYNCHRONOUS COUNTER
DATE:
AIM:
To design and verify Synchronous and Asynchronous counter
APPARATUS REQUIRED:
S.No.
1.
2.
3.
4.
COMPONENT
JK FLIP FLOP
NAND GATE
IC TRAINER KIT
PATCH CORDS
SPECIFICATION
IC 7476
IC 7408
-
QTY.
2
1
1
As per
Required
THEORY:
A counter is a register capable of counting number of clock pulse arriving at
its clock input. Counter represents the number of clock pulses arrived. A specified
sequence of states appears as counter output. This is the main difference between a
register and a counter. There are two types of counter, synchronous and
asynchronous. In synchronous common clock is given to all flip flop and in
asynchronous first flip flop is clocked by external pulse and then each successive flip
flop is clocked by Q or Q output of previous stage. A soon the clock of second stage
is triggered by output of first stage. Because of inherent propagation delay time all
flip flops are not activated at same time which results in asynchronous operation.
68
LOGIC DIAGRAM:
SYNCHRONOUS COUNTER
IC7408
1
3
2
12
CLK
K
10
16
IC7476
P RE
15
CLK
K
14
14
11
C LR
CLK
IC7476
P RE
P RE
16
15
IC7476
C LR
DATA IN
C LR
PRESET
CLOCK
CLEAR
A2
A1
A0
TRUTH TABLE:
CLK
QA
QB
QC
69
LOGIC DIAGRAM FOR 4 BIT ASYNCHRONOUS COUNTER:
TRUTH TABLE:
CLK
QA
QB
QC
QD
10
11
12
13
14
15
70
ASYNCHRONOUS UP/DOWN COUNTER:
TRUTH TABLE:
71
SYNCHRONOUS 3-BIT UP/DOWN COUNTER
TRUTH TABLE:
72
PROCEDURE:
(i)
(ii)
(iii)
RESULT:
Thus the synchronous and Asynchronous counter are designed and verified
successfully.
73
DESIGN AND IMPLEMENTATION OF SHIFT REGISTER
EX. NO:
DATE:
AIM:
To design and implement
(i)Serial in serial out
(ii)Serial in parallel out
(iii)Parallel in serial out
(iv)Parallel in parallel out
APPARATUS REQUIRED:
S.No.
1.
2.
3.
4.
COMPONENT
D FLIP FLOP
OR GATE
IC TRAINER KIT
PATCH CORDS
SPECIFICATION
IC 7474
IC 7432
-
QTY.
2
1
1
As per
Required
THEORY:
A register is capable of shifting its binary information in one or both directions
is known as shift register. The logical configuration of shift register consist of a DFlip flop cascaded with output of one flip flop connected to input of next flip flop. All
flip flops receive common clock pulses which causes the shift in the output of the flip
flop.
The simplest possible shift register is one that uses only flip flop. The output
of a given flip flop is connected to the input of next flip flop of the register. Each
clock pulse shifts the content of register one bit position to right.
PIN DIAGRAM:
74

LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:
TRUTH TABLE:
CLK
Serial in
Serial out
75
LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:
TRUTH TABLE:
CLK
OUTPUT
DATA
QA
QB
QC
QD
76

LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:
TRUTH TABLE:
CLK
Q3
Q2
Q1
Q0
O/P
77

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:
TRUTH TABLE:
CLK
DATA INPUT
OUTPUT
DA
DB
DC
DD
QA
QB
QC
QD
78
PROCEDURE:
(i)
(ii)
(iii)
RESULT:
Thus the shift registers are constructed and verified successfully
79
DESIGN OF ADDER AND SUBTRACTOR USING

VERILOGHARDWARE DESCRIPTION LANGUAGE
(CONTENT BEYOND)
AIM:
To write the HDL program for designing adder and subtractor circuit and
Simulate it.
SOFTWARE USED:
XILINX ISE Simulator
THEORY:
HALF ADDER:
From the verbal explanation of a half adder, we find that this circuit needs two
binary inputs and two binary outputs. The input variables designate the augends and
addend bits; the output variables produce the sum and carry. We assign symbol a
and b to the inputs and S (for sum) and C (for carry) to the outputs. The truth table
for the half adder is listed in table. The C output is 1 only when both inputs are 1.
The S output represents the least significant bit of the sum.
The simplified Boolean functions for the two outputs can be obtained directly
from the truth table. The logic diagram of the half adder implemented in sum of
products is shown in figure. It can be also implemented with an exclusive-OR and
an AND gate as shown in figure. This from is used to show that two half adders can
be used to construct a full adder.
80
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of three
bits. It consists of three inputs and two outputs. Two of the input variables, denoted
by a and b, represent the two significant bits to be added. The third input c
represents the carry from the previous lower significant position. Two outputs are
necessary because the arithmetic sum of three binary digits ranges in value from 0 to
3, and binary 2 or 3 need two digits. The two outputs are designated by the symbols
S for sum and D for carry. The binary variable S gives the value of the least
significant bit of the sum. The binary variable D gives the output carry. The truth
table of the full adder is listed in table. The eight rows under the input variables
designate all possible combinations of the variables.
The output variables are
determined from the arithmetic sum of the input bits. When all input bits are 0, the
output is 0. The S output is equal to 1 when only one input is equal to 1 or when all
three inputs are equal to 1. The D output has a carry of 1 if two or three inputs are
equal to 1.
The input and output bits of the combinational circuit different
interpretations at various stages of the problem. Physically, the binary signals of the
inputs are considered binary digits to be added arithmetically to form a two-digit sum
at the output. On the other hand, the same binary values are considered as variables
of Boolean functions when expressed in the truth table or when the circuit is
implemented with logic gates. The maps for the output of the full adder are shown in
below.
81
HALF ADDER:
LOGIC DIAGRAM:
TRUTH TABLE:
A
CARRY
SUM
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
PROGRAM FOR HALF ADDER:

module halfadder (a,b,sum,carry);
input a,b;
output sum,carry;
xor(sum,a,b);
and(carry,a,b);
endmodule
82
FULL ADDER:
LOGIC DIAGRAM:
FULL ADDER USING TWO HALF ADDER:
TRUTH TABLE:
A
CARRY
SUM
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
PROGRAM FOR FULL ADDER:

module fulladder(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
wire p,q,r;
xor(s,a,b,cin);
and(p,a,b);
and(q, b,cin);
and(r,a,cin);
or(cout,p,q,r);
endmodule
83
HALF SUBTRACTOR:
LOGIC DIAGRAM:
TRUTH TABLE:
A
BORROW
DIFFERENCE
0
0
1
1
0
1
0
1
0
1
0
0
0
1
1
0
PROGRAM FOR HALF SUBTRACTOR:

module halfsubtractor(a,b,diff,borrow);
input a,b;
output diff,borrow;
xor(diff,a,b);
not(a1,a)
and(borrow,a1,b);
endmodule
84
FULL SUBTRACTOR:
LOGIC DIAGRAM:
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
TRUTH TABLE:
A
BORROW
DIFFERENCE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
PROGRAM FOR FULL SUBTRACTOR:

module fullsubtractor(a,b,cin,diff,bout);
input a,b,cin;
output diff,bout;
wire p,q,r;
xor(s,a,b,cin);
not (a1,a)
and(p,a1,b);
and(q,b,cin);
and(r,a,cin);
or(cout,p,q,r);
endmodule
85
PROCEDURE:
i)
ii)
iii)
iv)
v)
vi)
vii)
viii)
ix)
x)
xi)
xii)
xiii)
xiv)
Open project navigator.

Go to the file and click the new project
Type the project name as synthesis
The property wizard is open to check all properties such as
product, categories, family, device etc. then click next
Create new source wizard appears then click next
Project summary is displayed then click next
Go to the project and click new source
Then type the full name half adder as well as select verilog
module then click next
Define module window here we assign the input and output of
half adder, clicks next and click finish
Type the program and save it
Make sure that the source is in BEHAVIOUR
Then click the ISE simulator and view the signal window
Force the input data corresponding circuit
Simulate the program using ISE simulator
RESULT:
Thus the verilog HDL code for adder and subtractor are simulated successfully using
XILINX ISE simulator
86
DESIGN OF MULTIPLEXER AND DE-MULTIPLEXER

USING VERILOG HARDWARE DESCRIPTION LANGUAGE
(CONTENT BEYOND)
AIM:
To write the HDL program for designing multiplexer and de-multiplexer

Circuit &simulate it.
SOFTWARE USED:
XILINX ISE Simulator
THEORY:
MULTIPLEXER:
A digital multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally, there are 2^n
inputs lines and n selection lines whose bit combinations determine which input is
selected.
In a 4 to 1 line multiplexer, the four input lines, I0 to I3 is applied to one input
of an AND gate. Selection lines S1 and S0 are decoded to select a particular AND
gate. A multiplexer is also called a data selector, since it selects one of many inputs
and steers the binary information to the output line.
DEMULTIPLEXER:
The demultiplexer does the reverse operation of a multiplexer. It can be used
to separate the multiplexed signal into individual signals, the select i n p u t code
determines to which output the data input will be transmitted. The number of output
lines is n and the number of select lines is m, where n=2^m. The
input
data
is
transmitted to one of the output di by means of select signals a, b. The 4-bit adder
adds the input a & b and produces the 4-bit sum as the output.
87
LOGIC DIAGRAM FOR MULTIPLEXER:
TRUTH TABLE:
S1
S0
Y = OUTPUT
D0
D1
D2
D3
PROGRAM FOR MULTIPLEXER:

module mux(d0,d1,d2,d3,s0,s1,f);
input d0,d1,d2,d3,s0,s1;
output f;
wire ns1,ns0,p,q,r,s;
not (ns1,s1);
not(ns0,s0);
and(p,ns0,ns1,i0);
and(q,s0,ns1,i1);
and(r,ns0, s1,i2);
and(s,s0, s1,i3);
or(f,p,q,r,s);
endmodule
88
LOGIC DIAGRAM FOR DEMULTIPLEXER:
TRUTH TABLE:
INPUT
OUTPUT
S1
S0
I/P
D0
D1
D2
D3
PROGRAM FOR DE-MULTIPLEXER:
module demux(a,b,s,do,d1,d2,d3);
input a,b,s;
output d0,d1,d2,d3;
wire a1,b1; not
(a1,a);
not(b1,b);
and(d0,b1,a1,s);
and(d1,b,a1,s);
and(d2,b1,a,s);
and(d3,b,a,s);
endmodule
89
PROCEDURE:
i)
ii)
iv)
v)
vii)
viii)
ix)
x)
xi)
xii)
xiv)
Open project navigator.

Go to the file and click the new project iii)
Type the project name as synthesis
The property wizard is open to check all properties such as product,
categories, family, device etc. then click next
Create new source wizard appears then click next vi)
Project summary is displayed then click next
Go to the project and click new source
Then type the full name half adder as well as select verilog module
then click next
Define module window here we assign the input and output of half
adder, clicks next and click finish
Type the program and save it
Make sure that the source is in BEHAVIOUR
Then click the ISE simulator and view the signal window xiii)
Force the input data corresponding circuit
Simulate the program using ISE simulator
RESULT:
Thus the verilog HDL code for Multiplexer and Demultiplexer are simulated
Successfully using XILINX ISE simulator
90

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K.L.N.

FOR III SEMESTER

EC6311-Analog and Digital Circuits Laboratory

Academic Year: 2015-2016

Name of the Experiment

Half Wave and Full Wave Rectifiers, Filters, Power supplies

LIST OF DIGITAL EXPERIMENTS

Fig 1 Half Wave Rectifier without filter

Fig 2 Half Wave Rectifier with filter

Fig 3 Power Supply Using Bridge Rectifier

RECTIFIERS, FILTERS AND POWER SUPPLIES

Fig 4 Input & Output waveform of Half-wave rectifier

1. Connect the circuit diagram as shown in Fig 1.

Power supply- Output DC

COMMON EMITTER AMPLIFIER USING VOLTAGE DIVIDER BIAS

Maximum Voltage gain (Av)

3-dB Voltage gain (Av @ 3dB)

Gain Bandwidth product (GBW)

COMMON SOURCE AMPLIFIER

FET, Resistors, Capacitors, AFO, CRO and RPS

4. Plot the graph: Gain (dB) Vs Frequency (Hz).

Maximum Voltage gain (Av)

3-dB Voltage gain (Av @ 3dB)

4. Plot the graph: Gain (dB) Vs Frequency (Hz).

Maximum Voltage gain (Av)

3-dB Voltage gain (Av @ 3dB)

Gain Bandwidth product (GBW)

Measurement of Differential gain (Ad )

Measurement of common mode gain (Ac )

For the single ended output, the differential mode gain

TWO STAGE RC COUPLED AMPLIFIER (CASCADE AMPLIFIER)

Transistor (BC107), Resistor, Capacitor, AFO, CRO and RPS

For the first stage:

II.Plotting the frequency response characteristics

Maximum Voltage gain (Av)

3-dB Voltage gain (Av @ 3dB)

Gain Bandwidth product (GBW)

CLASS A POWER AMPLIFIER

Measurement for frequency response characteristics

1. Connect the circuit diagram as shown in Fig 1.

DESIGN AND IMPLEMENTATION OF CODE CONVERTER

Binary to gray code converter

Gray to binary code converter (iii)

BCD to excess-3 code converter

Gray code output

K-Map for G3:

K-Map for G1:

K-Map for G0:

K-Map for B3:

K-Map for B1:

K-Map for B0:

K-Map for E1:

K-Map for E0:

Connections were given as per circuit diagram.

Logical inputs were given as per truth table

DESIGN OF 4-BIT BINARY ADDER AND SUBTRACTOR&BCD ADDER

PIN DIAGRAM FOR IC 7483:

DESIGN AND IMPLEMENTATION OF MULTIPLEXER

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

LOGIC DIAGRAM FOR MULTIPLEXER:

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXERS:

LOGIC DIAGRAM FOR DEMULTIPLEXER:

LAB MANUAL/EC 6311-ANALOG AND DIGITAL CIRCUITS LAB