Escolar Documentos
Profissional Documentos
Cultura Documentos
TITLE:
NAME:
Stephen Watt
DATE DUE:
DATE RECEIVED:
13.7
= 10 log (10 10 (4)),
where R is the symbol bit rate and B is the bandwidth (or 1/T for digital systems) the corresponding SNR
necessary to maintain the desired bit error rate is calculated to be 19.7 dB.
[Question 1.3] The bit period, TB, is equal to the inverse of the bit stream frequency of 1 Mbps, so the bit
period is equal to 1 s (shown in Figure 3).
Figure 4 Even and odd bit waveforms for 16-QAM, 1Mbps data rate
3
[Question 1.7] The constructed receiver demodulates the signal using commercial off-the-shelf (COTS)
components. The SKY67101-396LF LNA was chosen for its low noise figure of 0.57 dB and operating
frequency from 0.4 1.2 GHz. This LNA operating frequency must be in the range of the image reject BPF
used in the receiver. An ideal image reject BPF with 2 dB of loss and a 2 MHz bandwidth was used after the
LNA component to remove the image, which has an offset of twice the intermediate frequency (IF) from the
desired channel signal. The ADL5801 RF mixer was used to down-convert the signal to baseband. The local
oscillator (LO) was modelled using and ideal tone source. Finally, a HMC960LP4E power amplifier was used
to amplify the IF signal for detection. See attached Appendix for component datasheets. From the received
signal spectrum it is apparent that the commercial components functioned well, yielding an SNR of 47 dB
which meets the EVM and BER requirement.
Figure 8 Modulated signal constellation before transmit channel (left) and after PGA (right)
5
[Question 1.9] See the attached pages for the full system schematic for the Part A simulations.
Figure 9 Constellation diagram w/ 0.5 dB amplitude mismatch (left) and resulting SNR
[Question 2.2] Next a 1 IQ phase mismatch was introduced to the transmission system to examine the resulting
BER and EVM. As shown in Figure 11, the effect of the 1 IQ imbalance is minimal and the BER, EVM, and
SNR specifications are still met.
To exaggerate the effect of IQ phase mismatch, a 20 mismatch was introduced to the transmission circuit and
the constellation diagram is plotted in Figure 12. It is apparent that the phase mismatch introduces a rotational
distortion to the constellation that is proportional to the level of mismatch.
Figure 13 Configuring phase noise in the receiver LO source (left) resulting signal constellation
[Question 4.1] The system is shown to tolerate up to a 1.4 dB IQ amplitude mismatch while still meeting the
BER/SNR specification, as shown in Figure 14.
BER
ID=BER5
VARNAME="AMPLITUDE"
VALUES=stepped(0,6,0.5)
OUTFL=""
BER
Figure 14 Varying the IQ amplitude mismatch and measuring BER (< 1.4 dB meets spec)
[Question 4.2] The system is shown to tolerate up to a 2.75 IQ phase mismatch while still meeting the
BER/SNR specification, as shown in Figure 15.
[Question 4.3] Next the IQ amplitude and phase mismatch were set to zero and an 850 MHz jamming signal
was introduced at the receiver input. The receiver system is shown to tolerate up to a -59.42 dBm jamming
signal while still meeting the BER/SNR specification, as shown in Figure 16.
BER
ID=BER5
VARNAME="PHASE"
VALUES=stepped(0,20,2)
OUTFL=""
BER
Figure 15 Varying the IQ phase mismatch and measuring BER (< 2.75 meets spec)
BER
ID=BER5
VARNAME="JAM_POWER"
VALUES=stepped(-80,-30,5)
OUTFL=""
BER
Figure 16 Varying the 850 MHz jamming signal power and measuring BER (< -59.42 dBm meets spec)
- IQ Imbalance
- AGWN
- Path Loss
- Jamming Signal
From 16-QAM IQ
Modulator
From Rx PGA
From IQ Modulator
DATA SHEET
RF_OUT/VDD
RF_IN
FEEDBACK
Features
Active
Bias
RFGND
VIN
S1942
Description
Skyworks Green products are compliant with
all applicable legislation and are halogen-free.
For additional information, refer to Skyworks
Denition of Green, document number
SQ04-0074.
N/C
N/C
RFIN
RFOUT/VDD
RFGND
N/C
VIN
FEEDBACK
S1943
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
201266I Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice July 10, 2014
High IP3,
10 MHz to 6 GHz, Active Mixer
ADL5801
Data Sheet
FEATURES
23
22
21
20
18
VPRF
17
GND
16
RFIP
LOIN 4
15
RFIN
GND
14
GND
GND
13
VPDT
GND
GND
ADL5801
LOIP 3
V2I
BIAS
APPLICATIONS
Cellular base station receivers
Radio link downconverters
Broadband block conversion
Instrumentation
19
DET
10
11
12
08079-001
Broadband upconverter/downconverter
Power conversion gain of 1.8 dB
Broadband RF, LO, and IF ports
SSB noise figure (NF) of 9.75 dB
Input IP3: 28.5 dBm
Input P1dB: 13.3 dBm
Typical LO drive: 0 dBm
Single-supply operation: 5 V at 130 mA
Adjustable bias for low power operation
Exposed paddle, 4 mm 4 mm, 24-lead LFCSP package
Figure 1.
GENERAL DESCRIPTION
The ADL5801 uses a high linearity, doubly balanced, active
mixer core with integrated LO buffer amplifier to provide high
dynamic range frequency conversion from 10 MHz to 6 GHz.
The mixer benefits from a proprietary linearization architecture
that provides enhanced input IP3 performance when subject to
high input levels. A bias adjust feature allows the input linearity,
SSB noise figure, and dc current to be optimized using a single
control pin. An optional input power detector is provided for
adaptive bias control. The high input linearity allows the device
to be used in demanding cellular applications where in-band
blocking signals may otherwise result in degradation in dynamic
performance. The adaptive bias feature allows the part to provide
high input IP3 performance when presented with large blocking
signals. When blockers are removed, the ADL5801 can automatically bias down to provide low noise figure and low power
consumption.
Rev. E
The balanced active mixer arrangement provides superb LO-toRF and LO-to-IF leakage, typically better than 40 dBm. The IF
outputs are designed to provide a typical voltage conversion
gain of 7.8 dB when loaded into a 200 load. The broad
frequency range of the open-collector IF outputs allows the
ADL5801 to be applied as an upconverter for various transmit
applications.
The ADL5801 is fabricated using a SiGe high performance IC
process. The device is available in a compact 4 mm 4 mm,
24-lead LFCSP package and operates over a 40C to +85C
temperature range. An evaluation board is also available.
Document Feedback
HMC960LP4E
v01.1212
Features
Low Noise: 6 dB NF
Variable Gain: 0 to 40 dB
Diversity Receivers
ADC Drivers
Functional Diagram
General Description
The HMC960LP4E is a digitally programmable dual
channel variable gain amplifier. It supports discrete
gain steps from 0 to 40 dB in precise 0.5 dB steps.
It features a glitch free architecture to provide
exceptionally smooth gain transitions. The device
has matched gain paths which provide excellent
quadrature balance over a wide signal bandwidth.
The HMC960LP4E provides an SPI programmable
input impedance of 100 differential or 400
differential (default).
Externally controlled common mode output feature
enables the HMC960LP4E to provide a flexible output
interface to other parts in the signal path.
Gain can be controlled via either a parallel interface
(GC[6:0]) or via the read/write serial port (SPI).
Housed in a compact 4x4mm (LP4) SMT QFN
package, the HMC960LP4E requires minimal external
components and provides a low cost alternative to
more complicated switched amplifier architectures.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel 978-250-3373 fax Order On-line at www.hittite.com
Application Support: apps@hittite.com