Analog & Digital Student Lab Manual

EC6311 Analog and Digital Lab
RAJALAKSHMI INSTITUTE OF TECHNOLOGY

Kuthambakkam - Chennai
ANNA UNIVERSITY
Regulation - 2013
DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING
EC6311-Analog and Digital Communication Laboratory
(II Year B.E - ECE, III Semester)
Prepared by,
Mr.K.Sivakumar, AP(SS)/ECE
Ms.V.Subashini, AP/ECE
STAFF-IN CHARGE
Semester 03
of Technology
HOD/ECE
Department of ECE
PRINCIPAL
Rajalakshmi Institute
Page 1
SYLLABUS
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of Technology
Department of ECE
Page 2

EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY
LIST OF EXPERIMENTS
LIST OF ANALOG EXPERIMENTS:
1. Frequency Response of CE / CB / CC amplifier
2. Frequency response of CS Amplifiers
3. Darlington Amplifier
4. Differential Amplifiers- Transfer characteristic.
5. CMRR Measurement
6. Cascode / Cascade amplifier
7. Class A Amplifier
8. Class B amplifier
9. Fullwave rectifier and Halfwave rectifier
10. Determination of bandwidth of single stage and multistage amplifiers
11. Spice Simulation of Common Emitter and Common Source amplifiers
LIST OF DIGITAL EXPERIMENTS
Introduction
Study Experiment-Verification of Logic Gates & Boolean Theorems and Laws
12. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa
13. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
14. Design and implementation of Multiplexer and De-multiplexer using logic gates
15. Design and implementation of encoder and decoder using logic gates
16. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
17. Design and implementation of 3-bit synchronous up/down counter
18. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops
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Department of ECE
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LAB SCHEDULE
SL NO
LIST OF EXPERIMENTS
LIST OF ANALOG EXPERIMENTS
1.
2.
3.
4.
5.
6.
7.
Introduction
- Study of electronic components [Active and Passive].
- Study of Regulated Power supply, Signal Generator, Function Generator
and CRO.
- Study of transistor parameters using Transistor Data Sheets.
Design and Analysis of Common Emitter Amplifier
- To Determine a. DC characters tics, b. AC characteristics, c. Gain,
d. Bandwidth, e. Gain- Bandwidth Product, f. SPICE Simulation of
Amplifier(Additional)
Design and Analysis of Common Collector Amplifier
- To Determine a. DC characteristics, b. AC characteristics, c. Gain,
Design and Analysis of Common Base Amplifier
- To Determine a. DC characteristics, b. AC characteristics, c. Gain,
Design and Analysis of Darlington Amplifier
- To Determine a. DC characteristics, b. AC characteristics, c. Gain
Design and Analysis of Common Source Amplifier
Amplifier (Additional)
Design and Analysis of Cascade Amplifier
Design and Analysis of Cascode Amplifier
8.
Design and Analysis of Class A amplifier
9.
Design and Analysis of Class B amplifier
10.
Design and Analysis of Half-wave rectifier
11.
Design and Analysis of Full-wave rectifier
12.
Design and Analysis of Differential Amplifier

- To Determine a. Transfer characteristics, b. CMRR
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13.
Pspice Simulation of Common Emitter Amplifier

a. Gain, b. Bandwidth
14.
Pspice Simulation of Common source Amplifier

a. Gain, b. Bandwidth
LIST OF DIGITAL EXPERIMENTS
15.
Introduction
- Study of Digital IC's using IC data sheets
- Study of IC trainer Kit
Study Experiment-Verification of Logic Gates & Boolean Theorems and
Laws
16.
Design and implementation of code converters using logic gates

(i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa
17.
Design and implementation of 4 bit binary Adder/ Subtractor and

BCD adder using IC 7483
18.
Design and implementation of Multiplexer and De-multiplexer using logic

gates
19.
Design and implementation of encoder and decoder using logic gates
20.
Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12

Ripple counters
21.
Design and implementation of 3-bit synchronous up/down counter
Implementation of SISO, SIPO, PISO and PIPO shift registers using Flipflops
CONTENT BEYOND SYLLABUS
23.
Bridge Rectifier
24.
Seven Segment Display
22.
INDEX
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S. No
Date
Name of the Experiment
Page No.
Sign
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
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17.
18.
19.
20.
21.
22.
23.
Common Emitter Amplifier circuit diagram

CE Amplifier without Feedback :
CE Amplifier with Feedback:
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COMMON EMITTER AMPLIFIER

EXPERIMENT:
01
DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using voltage divider
bias and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product
2. REQUIREMENTS:
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S.n
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BC 107
(0-3)MHz
30MHz
(0-30)V
Resistor [Passive]
2
Component
Watt , + 1%
Tolerence
Capacitor [Passive]
Signal
4
5
Generator[SG]
Equipment
Regulated power
supply
7
8
CRO
Bread Board
Accessories
Connecting Wires
Single strand
as
required
DESIGN PROCEDURE:
Given specifications:
VCC= 10V, IC=1.2mA, AV= 30, hFE= 100
(i) To calculate RC:
(ii) To calculate R1&R2:
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(iii) Input coupling capacitor :
(iv) Output coupling capacitor:
3. THEORY:
A common emitter amplifier is type of BJT amplifier which increases the
voltage level of the applied input signal Vin at output of collector.
The CE amplifier typically has a relatively high input resistance (1 - 10 K)
and a fairly high output resistance. Therefore it is generally used to drive
medium to high resistance loads. It is typically used in applications where a
small voltage signal needs to be amplified to a large voltage signal like radio
receivers.
The input signal Vin is applied to base emitter junction of the transistor and
amplifier output Vo is taken across collector terminal. Transistor is
maintained at the active region by using the resistors R1,R2 and Rc. A very
small change in base current produces a much larger change in collector
current. The output Vo of the common emitter amplifier is 180 degrees out
of phase with the applied the input signal V in.
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier
using AC analysis.
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3. Set the input voltage Vin=V
from 0Hz to 1MHz in
MSH
/2 and vary the input signal frequency
incremental steps and note down the corresponding
output voltage Vo for at least 20 different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi) dB
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph
taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f2-f1
where f1 lower cut-off frequency
f2 upper cut-off frequency
a.
DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
ii)
iii)
Set Vin = 0 by reducing the amplitude of the input signal from

signal generator
Open circuit the capacitors since it blocks DC voltage
Set VCC= +10v and measure the voltage drop across the
Resistor VRC, voltage across Collector- Emitter Junction VCE
iv)
and Voltage drop across base emitter junction. V BE

Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
= _______ (REVERSE BIAS)
4. Ic( Ic = (Vcc VCE ) / Rc) =________

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Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
b. Maximum signal handling capacity :

It is the process to find the maximum input voltage that can be
handled by the amplifier, so that it amplifies the input signal without any
distortion.
Procedure:
i.
Apply input signal Vin = 20 mV of 1Khz frequency to the
amplifier using the signal generator between base emitter
junction of the transistor. Find the sinusoidal output using
ii.
CRO across RL.

By increasing
the
amplitude
maximum input voltage V
MSH
of
the
input
signal
find
across VBE at which the
sinusoidal signal gets distorted during the process which can

be seen in the CRO. The amplitude obtained at this point is
maximum voltage that can be applied to the transistor for
efficient operating of transistor.
V
MSH
= _________ volts
MODEL GRAPH:
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4. TABULATION [Without Feedback ] :

Input voltage (Vin=V
S. NO
/2) =____________V
MSH
FREQUENCY
OUTPUT VOLTAGE
[Hz]
[ VO] in Volts
GAIN= 20 log Vo/Vin

dB
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
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11.
12.
13.
14.
15.
16.
With Feedback :
S. NO
/2) =____________ V
MSH
FREQUENCY
OUTPUT
[Hz]
VOLTAGE [ VO] in
Volts
GAIN= 20 log ( vo/vin )

dB
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
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15.
16.
WORKSHEET
5. RESULT:
INFERENCE:
The Common Emitter Amplifier was constructed and the following results
were determined:
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
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c) Gain-Bandwidth product :
CONCLUSION:
Common Collector Amplifier Circuit Diagram:
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MODEL GRAPH:
COMMON COLLECTOR AMPLIFIER

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EXPERIMENT: 02
DATE:
1. OBJECTIVE:
To Design and Construct a Common collector Amplifier and to determine
its:
a.
b.
c.
d.
e.
2.
DC Characteristics
Gain -Bandwidth Product using frequency response curve
REQUIREMENTS:
Requiremen
S.No
Name
Components
Transistor [Active]
Resistor [Passive]
Capacitor [Passive]
Signal Generator
Equipment
[SG]
CRO
Range
Quantity
BC 107
0-3MHz
0-30MHz
0-30 V
Single strand
as required
Regulated power
supply
Accessories
Bread Board
Connecting Wires
Design of Common collector amplifier:

VCC= 15V, IC=1.2mA, hie = 2.1k hFE= 75 hib= 27.6
(i)
To calculate Zb ( Device input impedance )

Zb = hie + hfe ( RE || RL)
Assume RE = 4.7 K and RL= 3.3 K
Zb = 2.1k + 75 (4.7 K || 3.3 K) = __________
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(ii)
To calculate Zi ( Input Impedance )

Zi = R1 || R2 || Zb
Assume R1= R2= 10k
Zi = _______
(iii) To Calculate Voltage gain Av :

Av = [ ( RE || RL ) / ( hib + ( RE || RL) ) ]
Av = _____
3.
THEORY:
A common collector amplifier is a unity gain BJT amplifier used for
impedance matching and as a buffer amplifier.

Circuit Operation :
When a positive half-cycle of the input signal is applied
to Base emitter junction of transistor the forward bias voltage V be is increased,

which in turn increases the base current I b of transistor. Since emitter current Ie
is directly proportional to Ib the voltage drop across the Emitter Ve= IeRe is
increased, hence, output voltage Vo is increased, thus, we get positive half-cycle
of the output. It means that a positive-going input signal results in a positive
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going output signal and, consequently, the input and output signals are in phase
with each other. Similarly the negative half cycle of input signal produces
negative going output signal.
Characteristics of a CC Amplifier
1. high input impedance (20-500 K )
2. low output impedance (50-1000 )
3. high current gain of (1 + ) i.e. 50 500
4. voltage gain of less than 1 (unity)
5. power gain of 10 to 20 dB
6. no phase reversal of the input signal
4. PROCEDURE:
1.
Connect the circuit as per the circuit diagram
2.
Determine the Q-point of the CE amplifier using DC analysis.
3.
Determine Maximum input voltage that can be applied to CE amplifier
using AC analysis.
3. Set the input voltage Vin=V MSH /2 and vary the input signal frequency
from 0Hz to 1MHz in incremental steps and note down the corresponding
5. The voltage gain is calculated as Av = 20log (V0/Vin)
taking
Where f1 - lower cut-off frequency
f2 - upper cut-off frequency
a. DC ANALYSIS:
Steps:
i)
Set Vin = 0 by reducing the amplitude of the input signal
from signal generator
ii)
iii)
iv)
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1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )
distortion.
Procedure:
i.
Apply input signal Vin = 1 V of 1Khz frequency to the CC
CRO across RL.
ii.
By increasing the amplitude of the input signal find
maximum input voltage V MSH across VBE at which the
V
MSH
= _________ volts
5. TABULATION
S. NO
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MSH
FREQUENCY
[Hz]
/2) =____________ volts

OUTPUT
VOLTAGE
GAIN= 20 log vo/vin dB
[ VO] in Volts
Department of ECE
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1.
0
2.
100
3.
500
4.
600
5.
800
6.
900
7.
1 KHz
8.
100 KHz
9.
500 KHz
10.
11.
600 KHz
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
WORKSHEET
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6. RESULT:
INFERENCE:
The common collector amplifier was constructed and input resistance and gain
were determined. The results are found to be as given below
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a) Gain of the amplifier (in dB) :
b) Bandwidth of the amplifier (in Hz) :
c) Gain-Bandwidth product (GBWP) :
CONCLUSION:
Common Base Amplifier Circuit Diagram:
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MODEL GRAPH:
COMMON BASE AMPLIFIER
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EXPERIMENT:03
DATE:
1. OBJECTIVE:
To Design and Construct a Common Base Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
2. REQUIREMENTS:
S.N
o.
Requirement
Name
Range
Transistor [Active]
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
power (0-30)V
1
1
Accessories
8
Connecting Wires
Single strand
as required
DESIGN PROCEDURE:
Given Transistor specifications:
hie = 2.1k ; hfe = 75 ; hfb =0.987
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i) To find Device input impedance :
hib = ( hie / (1+ hfe))
hib = ____
ii) To find Circuit input impedance (Zi) :
iii) To find Circuit output impedance (Zo) :
iv) To find Voltage Gain (Av) :
3. THEORY:
A common base amplifier is type of BJT amplifier which increases the
The Common base amplifier typically has good voltage gain and relatively
high output impedance. But the Common base amplifier unlike CE amplifier has
very low input impedance which makes it unsuitable for most voltage amplifier. It
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is typically used used as an active load for a cascode amplifier and also as a
current follower circuit.
Circuit Opeartion:
A positive-going signal voltage at the input of a CB pushes the transistor
emitter in a positive direction while the base voltage remains fixed, hence Vbe
reduces. The reduction in V BE results in reduction in V RC, consequently VCE
increases. The rise in collector voltage effectively rises the output voltage. The
positive going pulse at the input produces a positive-going output, hence the
there is no phase shift from input to output in CB circuit. In the same way the
negative-going input produces a negative-going output.
4. PROCEDURE:
2. Determine the Q-point of the CB amplifier using DC analysis.
using
AC analysis.
output voltage Vo for atleast 20 different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi)
taking
where f1 lower cut-off frequency
f2 upper cut-off frequency
a. DC ANALYSIS:
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Steps:
i)
ii)
iii)
iv)

1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )
distortion.
Procedure:
i.
CRO across RL.
ii.
V
MSH
= _________ volts
5. TABULATION
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MSH
/ 2) =____________V
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Page 30
S. NO
FREQUENCY
[Hz]
17.
18.
100
19.
500
20.
600
21.
800
22.
GAIN= 20 log Vo/ vin

dB
900
23.
1 KHz
24.
100 KHz
25.
500 KHz
26.
600 KHz
27.
OUTPUT
VOLTAGE
[ VO] in Volts
700 KHz
28.
800 KHz
29.
900 KHz
30.
1 MHz
31.
1.1 MHz
32.
1.5 MHz
WORKSHEET
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6. RESULT:
INFERENCE:
The Common base amplifier was constructed and input resistance and gain were
determined. The results are found to be as given below
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CONCLUSION:
Darlington Amplifier Circuit Diagram
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MODEL GRAPH:
DARLINGTON AMPLIFIER
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EXPERIMENT:04
DATE:
1. OBJECTIVE:
To Design and Construct a BJT amplifier using Darlington pair and to
determine its:
a.
b.
c.
d.
e.
DC Characteristics
2. REQUIREMENTS:
S.N
o.
Requirement
Name
Range
Transistor [Active]
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
power (0-30)V
Bread Board
1
1
Accessories
8
Connecting Wires
Single strand
as required
DESIGN PROCEDURE:
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VCC= 12V, IC=1.2mA, AV= 30, f 1 = 300 HZ, f2 = 500KHZ, hFE= 150
(ii) To calculate R1&R2:
(iii) To Find Cin :
(iv) To Find CO :
3. THEORY:
The Darlington transistor (often called a Darlington pair) is compound
structure consisting of two bipolar transistors connected in such a way that the
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First transistor does current amplification of input signal and then it will be fed
to the second transistor which performs voltage amplification.
This configuration gives a much higher gain than each transistor taken
separately and, in the case of integrated devices, can take less space than two
individual transistors because they can use a shared collector. The Darlington
amplifier typically has a relatively high input resistance (1 - 10 K) and a fairly
high output resistance. Therefore it is generally used to drive medium to high
resistance loads. It is typically used in applications where a small voltage signal
needs to be amplified to a large voltage signal like radio receivers.
4. PROCEDURE:
2. Determine the Q-point of the Darlington amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to Darlington
amplifier using AC
analysis.
taking
where f1 - lower cut-off frequency
a. DC ANALYSIS:
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Steps:
i)
ii)
iii)
iv)

1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )
distortion.
Procedure:
i.
junction of the transistor.Find the sinusoidal output using CRO
across RL.
ii.
sinusoidal signal gets distorted during the processwhich can
V
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MSH
= _________ volts
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5. TABULATION
S. NO
FREQUENCY
[Hz]
/2) =____________ V
MSH
OUTPUT
VOLTAGE
GAIN= 20 log Vo/Vin

dB
[ VO] in Volts
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
0
100
500
600
800
900
1 KHz
100 KHz
500 KHz
600 KHz
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
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WORKSHEET
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6. RESULT:
INFERENCE:
The Darlington amplifier was constructed and the results are found to be
a. Gain of the amplifier :
b. Bandwidth of the amplifier :
c. Gain-Bandwidth product :
CONCLUSION:
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Common Source Amplifier Circuit Diagram
MODEL GRAPH:
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COMMON SOURCE AMPLIFIER

EXPERIMENT:05
DATE:
1. OBJECTIVE:
To Design and Construct a Common source
bootstrapped gate resistance and to determine its:
a.
b.
c.
d.
e.
2.
amplifier
using
the
DC Characteristics
REQUIREMENTS:
S.N
o.
Requirement
Name
Range
Transistor [Active]
Quantity
BFW10
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
power (0-30)V
1
1
Accessories
8
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Connecting Wires
Department of ECE
Single strand
as required
Page 43
DESIGN ANALYSIS :
Given :
VDD = 20 V, IDSS = 5mA, ID = 1.5 mA,
i) To Find the voltage across the Gate-source region (V GS)
VGS = ID RS
ii) To find Voltage Across Drain to Source (VDS)
iii) To Find input impedance :
iv) To Find output impedance :
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3. THEORY
There are three basic types of FET amplifier or FET transistor namely
common source amplifier, common gate amplifier and source follower amplifier.
The common-source (CS) amplifier may be viewed as a transconductance
amplifier or as a voltage amplifier.
i) As a transconductance amplifier, the input voltage is seen as modulating
the current going to the load.
ii) As a voltage amplifier, input voltage modulates the amount of current
flowing through the FET, changing the voltage across the output resistance
according to Ohm's law.
However, the FET device's output resistance typically is not high enough
for a reasonable transconductance amplifier (ideally infinite), nor low enough for
a decent voltage amplifier (ideally zero). Another major drawback is the
amplifier's limited high-frequency response. Therefore, in practice the output
often is routed through either a voltage follower (common-drain or CD stage), or
a current follower (common-gate or CG stage), to obtain more favorable output
and frequency characteristics
4. PROCEDURE:
2. Determine the Q-point of the CS amplifier using DC analysis.
3.
Determine Maximum input voltage that can be applied to CE amplifier
using
AC analysis.
taking
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a. DC ANALYSIS:

Steps:
i)
ii)
iii)
iv)

1. VGS
= ____________
2. VDS
= ____________
3 ID
= _______

distortion.
Procedure:
i.
ii.
Apply input signal Vin = 1 V of 1Khz frequency to the CS

CRO across RL.
V
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MSH
= _________ volts
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5. TABULATION
S. NO
/2) =____________V
MSH
FREQUENCY
[Hz]
OUTPUT
VOLTAGE
GAIN= 20 log Vo/Vin

dB
[ VO] in Volts
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
0
100
500
600
800
900
1 KHz
100 KHz
500 KHz
600 KHz
700 KHz
12.
800 KHz
13.
900 KHz
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14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
WORKSHEET
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Department of ECE
Page 48
6. RESULT:
INFERENCE:
The common Source amplifier was constructed and input resistance and gain
were determined. The results are found to be as given below
a) Gain of the amplifier (in db) :
b) Bandwidth of the amplifier (in HZ) :
c) Gain-Bandwidth product (GBWP) :
CONCLUSION:
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Page 49
Cascade amplifier Circuit Diagram
MODEL GRAPH:
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CASCADE AMPLIFIER
EXPERIMENT:06
DATE:
1. OBJECTIVE:
To Design and Construct a Cascade Amplifier and to determine its:
a.
b.
c.
d.
e.
2.
DC Characteristics
REQUIREMENTS:
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Department of ECE
Page 51

S.N
o.
Requirement
Name
Range
Transistor [Active]
Quantity
BC 107
Components
2
Resistor [Passive]
Capacitor [Passive]
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Equipment
power (0-30)V
Bread Board
1
1
Accessories
8
Connecting Wires
Single strand
as required
DESIGN PROCEDURE:
VCC= 14 V, IC1=1.2mA, RL = 40K hFE= 100
(i) To calculate R5 :
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(ii) To calculate R6 :
(iii) To calculate R1, R2 , R3 & R4:
3. THEORY:
A cascade is type of multistage amplifier where two or more single stage
amplifiers are connected serially. Many times the primary requirement of the
amplifier cannot be achieved with single stage amplifier, because Of the
limitation of the transistor parameters. In such situations more than one
amplifier stages are cascaded such that input and output stages provide
impedance matching requirements with some amplification and remaining
middle stages provide most of the amplification. These types of amplifier circuits
are employed in designing microphone and loudspeaker.
4. PROCEDURE:
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Page 53

2. Determine the Q-point of the amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using
AC analysis.
taking
a. DC ANALYSIS:

Steps:
v)
vi)
vii)
viii)

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1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )

distortion.
Procedure:
iii.
across RL.
iv.
V
MSH
= _________ volts
5. TABULATION
S. NO
1.
2.
Semester 03
of Technology
/2) =____________ volts
MSH
FREQUENCY
[Hz]
OUTPUT
VOLTAGE
[ VO] in Volts
GAIN= 20 log Vo/Vin

dB
0
100
Department of ECE
Page 55

3.
4.
5.
6.
7.
8.
9.
10.
11.
500
600
800
900
1 KHz
100 KHz
500 KHz
600 KHz
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
WORKSHEET
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6. RESULT:
INFERENCE:
The Cascade amplifier was constructed and input resistance and gain were
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Page 57

CONCLUSION:
Cascode amplifier Circuit Diagram
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Department of ECE
Page 58
MODEL GRAPH:
CASCODE AMPLIFIER
EXPERIMENT: 07
Semester 03
of Technology
DATE:
Department of ECE
Page 59

1. OBJECTIVE:
To Design and Construct a Cascode Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
2. REQUIREMENTS:
S.N
o.
Requirement
Name
Range
Quantity
Transistor [Active]
BC 107
Resistor [Passive]
61k, 10k, 1k,

4.7k
Capacitor [Passive]
10f, 100f
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Components
1,1,1,2
2,1
Equipment
power (0-30)V
Bread Board
1
1
Accessories
8
Connecting Wires
Single strand
as required
DESIGN PROCEDURE:
VCC= 20V, IC =1.2mA, AV= 30, , RL = 90K ;
Transistor Parameters: hFE= 50 , hie = 1.2K and hib= 24
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(ii) To calculate RE:
(iii) To Calculate Bias Resistors R1, R2, R3 :
Determination of Capacitor Values:

To Find C1 :
To Find C2 :
To Find C3 :
To Find C4 :
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Page 61
THEORY:
The cascode configuration has one of two configurations of multistage
amplifier. In each case the collector of the leading transistor is connected to the
emitter of the following transistor. The arrangement of the two transistors is
shown in the circuit diagram. The cascode amplifier consists of CE stage
connected in series with CB stage. The arrangement provides a relatively high
input impedance with low voltage gain for the first stage to ensure the input
miller capacitance is at a minimum, whereas the following CB stage provides an
excellent high frequency response.
Features:
1. It provides high voltage gain and has high input impedance.
2. It provides high stability and has high output impedance
PROCEDURE:
2. Determine the Q-point of the CE amplifier using DC analysis.
using AC analysis.
from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage V o for
atleast 20 different
values for the considered range.
taking frequency on xaxis and gain in dB on y-axis.,
where
f1 - lower cut-off frequency

a. DC ANALYSIS:
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Steps:
ix)
x)
xi)
xii)

1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )
distortion.
Procedure:
v.
across RL.
vi.
V
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MSH
= _________ volts
Department of ECE
Page 63

5. TABULATION
S. NO
/2) =____________ V
MSH
FREQUENCY
[Hz]
OUTPUT
VOLTAGE
GAIN= 20 log Vo/Vin

dB
[ VO] in Volts
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
0
100
500
600
800
900
1 KHz
100 KHz
500 KHz
600 KHz
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
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Page 64
WORKSHEET
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Page 65
6. RESULT:
INFERENCE:
The Cascode amplifier was constructed and input resistance and gain were
CONCLUSION:
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Page 66
Circuit Diagram
WITHOUT FILTER:
WITH FILTER:
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HALF WAVE RECTIFIER

Exp.No:
Date
AIM:
To construct half wave rectifier with and without filter and to draw their input and output
waveforms and find out ripple factor.
S.No.
1.
2.
3.
4.
5
6
7
8
9
Requirement List
Components
Equipments
Other Accessories
Name
Transformer
Diode
Resistor
Capacitor
Regulated power supply
Signal Generator
CRO
Bread Board
Connecting Wires
Range
230 V / 6-0-(-6)
IN4007
1 k
100F
(0-30)V
(0-3)MHz
30 MHz
Single strand
Quantity
1
1
1
1
1
1
1
1
as reqd.
Requirements:
THEORY:
Half wave rectifier:
A rectifier is a circuit, which uses one or more diodes to convert A.C voltage into D.C voltage. In this
rectifier during the positive half cycle of the A.C input voltage, the diode is forward biased and
conducts for all voltages greater than the offset voltage of the semiconductor material used. The
voltage produced across the load resistor has same shape as that of the positive input half cycle of A.C
input voltage.
During the negative half cycle, the diode is reverse biased and it does not conduct. So there is no
current flow or voltage drop across load resistor. The net result is that only the positive half cycle of
the input voltage appears at the output.
FORMULA USED:
Ripple Factor =
Where Im is the peak current
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MODEL GRAPH:
TABULATION
HALF WAVE RECTIFIER:
INPUT VOLTAGE = 12V (peak peak)

Without filter
Output signal
Amplitude(V)
With filter
Time period
Output signal
Amplitude(V)
Time period
CALCULATION OF RIPPLE FACTOR AND EFFICIENCY
Ripple Factor
Ripple factor is defined as the ratio of rms value of ac component to the dc
component in the output.
Ripple factor
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Vav the average or the dc content of the voltage across the load is given by
RMS voltage at the load resistance can be calculated as
Ripple Factor
Efficiency
Efficiency, is the ratio of the dc output power to ac input power
Thus
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Page 70
PROCEDURE:
1.
2.
3.
4.
Connect the circuit as per the circuit diagram.

Apply a.c input using transformer.
Measure the amplitude and time period for the input and output waveforms.
Calculate ripple factor and effiency
RESULT:
Thus the half wave rectifier was constructed and its input and output waveforms are
drawn. The ripple factor of capacitive filter is calculated as
Ripple factor=
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Page 71
Circuit Diagram
FULLWAVE RECTIFIER WITHOUT FILTER
FULLWAVE RECTIFIER WITH FILTER
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Page 72
Requirement List
S.No.
1.
2.
3.
4.
5
6
7
8
Components
Equipments
Other Accessories
Exp. No
Name
Transformer
Diode
Resistor
Capacitor
Signal Generator
CRO
Bread Board
Range
230 V / 6-0-(-6)
IN4007
1 k
100f
(0-30)V
(0-3)MHz
30 MHz
-
Connecting Wires
Single strand
FULL WAVE RECTIFIER
Quantity
1
2
1
2
1
1
1
1
as reqd.
Date:
AIM:
To construct a full wave rectifier and to calculate the ripple factor.
REQUIREMENTS
THEORY:
The full wave rectifier conducts for both the positive and negative half cycles of the input ac
supply. In order to rectify both the half cycles of the ac input, two diodes are used in this circuit. The
diodes feed a common load RL with the help of a centre tapped transformer. The ac voltage is applied
through a suitable power transformer with proper turns ratio. The rectifiers dc output is obtained
across the load. The dc load current for the full wave rectifier is twice that of the half wave rectifier.
The lowest ripple factor is twice that of the full wave rectifier. The efficiency of full wave rectification
is twice that of half wave rectification. The ripple factor also for the full wave rectifier is less
compared to the half wave rectifier.
FORMULA USED:
Ripple Factor =
[(Im/2) / (2*Im /)] 2-1
Where Im is the peak current
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MODEL GRAPH
TABULATOIN:
INPUT VOLTAGE = 12V (peak peak)

Without filter
Output signal
Amplitude(V)
With filter
Time period
Output signal
Amplitude(V)
Time period
CALCULATION OF RIPPLE FACTOR AND EFFICIENCY
Ripple Factor
The ripple factor for a Full Wave Rectifier is given by
Semester 03
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Department of ECE
Page 74
The average voltage or the dc voltage available across the load resistance is
RMS value of the voltage at the load resistance is
Efficiency
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Efficiency, is the ratio of dc output power to ac input power
The maximum efficiency of a Full Wave Rectifier is 81.2%.
PROCEDURE:
1. Connections are given as per the circuit diagram wiyhout filter.
2. Note the amplitude and time period of the input signal at the secondary winding of the
transformer and rectified output.
3. Repeat the same steps with the filter and measure Vdc.
4. Calculate the ripple factor.
5. Draw the graph for voltage versus time.
CONCLUSION
Thus, the full wave rectifier was constructed and the ripple factor was calculated as Ripple
factor =
CLASS A CIRCUIT DIAGRAM
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Page 76
MODEL WAVEFORM
V in = 50mV
V out = 10V (p-p)
Vin = Vmsh/2 = 100mV/2 = 50mV

Vout = 10V
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Department of ECE
Page 77

CLASS - A POWER AMPLIFIER
Exp. No.:
Date:
AIM:
To construct a Class A power amplifier and observe the waveform and to compute maximum
power dissipation and efficiency.
REQUIREMENTS:
S.No.
1.
2.
3.
4.
5.
6.
7.
Name
Transistor
Resistor
Capacitor
Signal Generator
CRO
Bread Board
Range
SL100
61k,10K,1K, 2.2K
10F, 10F, 100F
(0-3)MHz
30MHz
(0-30)V
Quantity
1
1,1,2,1
1,1,1
1
1
1
1
THEORY:
The power amplifier is said to be Class A amplifier if the Q point and the input signal
are selected such that the output signal is obtained for a full input signal cycle.
For all values of input signal, the transistor remains in the active region and never enters into
cut-off or saturation region. When an a.c signal is applied, the collector voltage varies sinusoidally
hence the collector current also varies sinusoidally. The collector current flows for 360 0 (full cycle) of
the input signal. i e the angle of the collector current flow is 360 0 .
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Observation:
Keep the input voltage constant, Vin = Vmsh/2 = 100mV/2 = 50mV
Vout = 10V
DC analysis
Vbe = 0.6
hfe = 165
Ic = (Vcc Vce)/ Rc =
Vce =
To find Max Efficiency
% max = (Pout(AC)) / (Pin (DC)) x 100 %

= [(Vcc2 /8RC) / (Vcc2 /2RC)] x 100%
% max = 25 % (theoretical)
% max = 23 % (practical)
To find Max power dissipation
Power dissipation = Pin (DC) Pout(AC)
=
=
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Page 79
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set Vi =50 mv, using the signal generator.
3. Keeping the input voltage constant, vary the frequency from 10 Hz to 1M Hz in regular steps and
note down the corresponding output voltage.
4. Plot the graph; Gain (dB) vs Frequency(Hz).
CONCLUSION:
Thus the Class A power amplifier was constructed. The following parameters were calculated:
`
Semester 03
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a) Maximum power dissipation =

b) Efficiency=
Department of ECE
Page 80
CIRCUIT DIAGRAM
With Distortion
Without Distortion
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Department of ECE
Page 81
CLASS B COMPLEMENTARY SYMMETRY POWER AMPLIFIER

S.No.
1.
2.
3.
4.
4.
5.
6.
7.
Requirement List
Components
Equipments
Name
Transistor
Resistors
capacitor
DIODE
Signal Generator
CRO
Bread Board
Other Accessories
8.
Connecting Wires
Exp. No.
Range
SL100,SK100
4.7k, 15 k
100F
IN4007
(0-30)V
(0-3)MHz
30 MHz
-
Quantity
1,1
2,1
2
2
1
1
1
1
Single strand
as reqd.
Date:
AIM:
To construct a Class B complementary symmetry power amplifier and observe the waveforms
with and without cross-over distortion and to compute maximum power delivered and efficiency.
REQUIREMENTS:
THEORY:
A power amplifier is said to be Class B amplifier if the Q-point and the input signal are
selected such that the output signal is obtained only for one half cycle for a full input cycle. The Qpoint is selected on the X-axis. Hence, the transistor remains in the active region only for the positive
half of the input signal.
There are two types of Class B power amplifiers: Push Pull amplifier and complementary symmetry
amplifier. In the complementary symmetry amplifier, one n-p-n and another p-n-p transistor is used.
The matched pair of transistor are used in the common collector configuration. In the positive half
cycle of the input signal, the n-p-n transistor is driven into active region and starts conducting and in
negative half cycle, the p-n-p transistor is driven into conduction. However there is a period between
the crossing of the half cycles of the input signals, for which none of the transistor is active and
output, is zero
FORMULA:
Input power, Pin=2VccIm/

Output power, Pout=VmIm/2
Power Gain or efficiency, =/4*(Vm/Vcc)* 100
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Department of ECE
Page 82
Theoretical Calculation
= AC (output) / DC (Input) = Pac / Pdc
Pac = Vrms x Irms = Vm/2 x Im/2
Pac = VmIm / 2
Pdc = Vcc x Idc
Idc = Im /
Pdc = (Vcc x Im/)
Since two transistors involved
Pdc = (2Vcc x Im/)
= [(VmIm/2) / (2VccIm/)]
for max output Vm = Vcc
= /4 = 0.7854
% = 78.54%
Practical Efficiency
= [(VmIm/2) / (2VccIm/)]
= /4 x (Vm/Vcc) x 100
=
%=
To find max power dissipation
Pd = 0.4 x Pac (max)
= 0.4 x (Vcc2/2RL)
=
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Page 83

Pd =
OBSERVATION
Input Voltage = 12V (p-P)
Amplitude (volts)
Time Period (ms)
With Distortion
Without Distortion
MODEL GRAPH
PROCEDURE:
1. Connections are given as per the circuit diagram without diodes.
2. Observe the waveforms and note the amplitude and time period of the input signal and
distorted waveforms.
3. Connections are made with diodes.
4. Observe the waveforms and note the amplitude and time period of the input signal and
output signal.
5. Draw the waveforms for the readings.
6. Calculate the maximum output power and efficiency.
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Department of ECE
Page 84

Hence the nature of the output signal gets distorted and no longer remains the same as the
input. This distortion is called cross-over distortion. Due to this distortion, each transistor conducts for
less than half cycle rather than the complete half cycle. To overcome this distortion, we add 2 diodes
to provide a fixed bias and eliminate cross-over distortion.
CONCLUSION:
Thus the Class B complementary symmetry power amplifier was constructed to observe
cross-over distortion and the circuit was modified to avoid the distortion. The following parameters
were calculated:
a)Maximum power dissipation =
b)Efficiency=
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Department of ECE
Page 85
Differential amplifier Circuit Diagram

Common Mode :
Differential Mode :
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Department of ECE
Page 86
DIFFERENTIAL AMPLIFIER
Exp. No.:
Date:
1. OBJECTIVE:
To Design and Construct a Differential Amplifier using BJT
determine its:
a.
b.
c.
d.
2.
and to
Transfer Characteristics
Gain of the amplifier in common mode
Gain of the amplifier in differential mode
CMRR (Common Mode Rejection Ratio)
REQUIREMENTS:
S.N
o.
Requirement
Name
Range
Transistor [Active]
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
power (0-30)V
1
1
Accessories
8
Connecting Wires
Single strand
as required
3. THEORY:
A differential amplifier is a type of electronic amplifier that amplifies
the difference between two voltages but does not amplify the particular
Semester 03
of Technology
Department of ECE
Page 87

voltages. The
need
for
differential
amplifier
arises
in
many
physical
measurements where response from D.C to many MHZ is required. It is also

used in input stage of integrated amplifier.
DESIGN PROCEDURE:
VCC= 12V, IC=1.2mA, V CE = 5V
MODEL GRAPH:
Differential amplifier Transfer Characteristics:
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Department of ECE
Page 88
The output signal in differential amplifier is proportional to the difference

between the two input signals.
Vo = Ad (V1 V2 ).
Where V1,V2 are the input voltages and Ad is the differential gain.
If V1 = V2, then output voltage is zero. A non zero output voltage is
obtained if V1 and V2 are not equal.
i)
ii)
iii)
The difference mode input voltage is defined as V d = (V1-V2)

The common mode input voltage is defined as the V cm= (V1+V2)/2
The CMRR is defined as the ratio of the differential gain Ad to
common mode gain Ac and is generally expressed in dB.
CMRR= 20 log10 ( Ad / Ac)
4. PROCEDURE:
2. Determine the Q-point of the Differential amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using
AC analysis.
4. Determine the Transfer characteristics of Differential amplifier by plotting
the graph for normalized differential input voltage [ (Vb1 V b2) / VT ] vs.
Normalized collector current [ Ic / Io].
5. Calculate the voltage gain of differential amplifier for differential mode
as Ad = 20log (V0/Vi) , Where Vi = V1 V2
6. Calculate the voltage gain of differential amplifier for Common mode
as AC = 20log (V0/Vi) , Where Vi = (V1+ V2 / 2 )
7. Find the Common mode rejection ratio of differential amplifier using the
formula given below.
CMRR= 20 log10 ( Ad/Ac)
Where Ad- Differential mode gain in dB
Ac Common Mode gain in dB
Semester 03
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Department of ECE
Page 89
a. DC ANALYSIS:

Steps:
i)
ii)
iii)
iv)

1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the operating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
distortion.
Procedure:
vii.
CRO across RL.
viii.
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Department of ECE
Page 90

V
MSH
= _________ volts
5. TABULATION
a. Transfer Characteristics Calculation:
S.no
Input Voltage
Vi = (Vb1 Vb2) in Volts
Output Current
Ic2 in Ampere
1.
2.
3.
4.
5.
6.
b. CMRR Calculation:
To Find Differential Gain (Ad ) :
S. NO
INPUT
VOLTAGE
in volts
OUTPUT VOLTAGE [
VO] in Volts
Differntial gain in dB
Ad = 20log (V0/Vi)
Where Vi = Vi1 Vi2
33.
Vi1
34.
Vi2
To Find Common Mode Gain (AC ) :

S. NO
INPUT
VOLTAGE
in volts
OUTPUT VOLTAGE
[ VO] in Volts
Common mode gain in

dB
AC = 20log (V0/Vi)
where Vi = (V1+ V2 /
2)
1.
Vi1
2.
Vi2
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Page 91
6. RESULT:
INFERENCE:
The Differential amplifier was constructed and input resistance and gain were
d) Trans-Conductance of Differential amplifier ( in millisiemens) :
e) Differential mode gain in dB
f) Common Mode Gain in dB
g) CMRR in dB
CONCLUSION:
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Department of ECE
Page 92
WORKSHEET
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Department of ECE
Page 93
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Department of ECE
Page 94
SPICE SIMULATION USING PSPICE Common

Emitter Amplifier circuit diagram
CE Amplifier without Feedback :
CE Amplifier with Feedback:
Semester 03
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Department of ECE
Page 95

COMMON EMITTER AMPLIFIER
EXPERIMENT:
DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using Pspice
simulation tool and to determine its:
a. Gain of the amplifier
b. Bandwidth of the amplifier
c. Gain -Bandwidth Product
2. REQUIREMENTS:
S.n
o
Requirements
Quantity
PC
Pspice Software
THEORY:
A common emitter amplifer is type of BJT amplifier which increases the
The CE amplifier typically has a relatively high input resistance (1 - 10 K)
and a fairly high output resistance. Therefore it is generally used to drive
medium to high resistance loads. It is typically used in applications where a
small voltage signal needs to be amplified to a large voltage signal like radio
receivers.
The input signal Vin is applied to base emitter junction of the transistor and
amplifier output Vo is taken across collector terminal. Transistor is
maintained at the active region by using the resistors R1,R2 and Rc. A very
small change in base current produces a much larger change in collector
current. The output Vo of the common emitter amplifier is 180 degrees out
of phase with the applied the input signal V in.
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Department of ECE
Page 96

WORKSHEET
Semester 03
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Department of ECE
Page 97

3. PROCEDURE:
1. Click on the start menu and select the pspice simulation
software
menu and place
2. Select the parts required for the circuit from the parts
them in the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output
waveforms
MODEL GRAPH:
4.RESULT:
INFERENCE:
The Common Emitter Amplifier was simulated and the following results
were determined:
CONCLUSION:
Semester 03
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Department of ECE
Page 98
Common source Amplifier circuit diagram

CS Amplifier:
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Department of ECE
Page 99
COMMON SOURCE AMPLIFIER

EXPERIMENT:
DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using Pspice
simulation tool and to determine its:
a. Gain of the amplifier
b. Bandwidth of the amplifier
c. Gain -Bandwidth Product
2. REQUIREMENTS:
S. No
1
2
THEORY:
Requirements
PC
Pspice
Software
Quantity
1
-
There are three basic types of FET amplifier or FET transistor namely
common source amplifier, common gate amplifier and source follower amplifier.
The common-source (CS) amplifier may be viewed as a transconductance
amplifier or as a voltage amplifier.
i) As a transconductance amplifier, the input voltage is seen as modulating
the current going to the load.
ii) As a voltage amplifier, input voltage modulates the amount of current
flowing through the FET, changing the voltage across the output resistance
according to Ohm's law.
However, the FET device's output resistance typically is not high enough
for a reasonable transconductance amplifier (ideally infinite), nor low enough for
a decent voltage amplifier (ideally zero). Another major drawback is the
amplifier's limited high-frequency response. Therefore, in practice the output
often is routed through either a voltage follower (common-drain or CD stage), or
a current follower (common-gate or CG stage), to obtain more favorable output
and frequency characteristics
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WORKSHEET
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3. PROCEDURE:
1. Click on the start menu and select the pspice simulation
software
menu and place
2. Select the parts required for the circuit from the parts
them in the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output
waveforms
MODEL GRAPH:
4.RESULT:
INFERENCE:
The Common Emitter Amplifier was simulated and the following results
were determined:
CONCLUSION:
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WORKSHEET
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DIGITAL EXPERIMENTS
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Introduction
There are 3 hours allocated to a laboratory session in Digital Electronics. It is a
necessary part of the course at which attendance is compulsory.
Here are some guidelines to help you perform the experiments and to submit the
reports:
1. Read all instructions carefully and carry them all out.
2. Ask a demonstrator if you are unsure of anything.
3. Record actual results (comment on them if they are unexpected!)
4. Write up full and suitable conclusions for each experiment.
5. If you have any doubt about the safety of any procedure, contact the
demonstrator beforehand.
The Bread board

The breadboard consists of two terminal strips and two bus strips (often broken
in the centre). Each bus strip has two rows of contacts. Each of the two rows of
contacts are a node. That is, each contact along a row on a bus strip is
connected together (inside the breadboard). Bus strips are used primarily for
power supply connections, but are also used for any node requiring a large
number of connections. Each terminal strip has 60 rows and 5 columns of
contacts on each side of the centre gap. Each row of 5 contacts is a node.
You will build your circuits on the terminal strips by inserting the leads of circuit
components into the contact receptacles and making connections with 22-26
gauge wire. There are wire cutter/strippers and a spool of wire in the lab. It is a
good practice to wire +5V and 0V power supply connections to separate bus
strips.
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The breadboard. The lines indicate connected holes.

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs
(Integrated circuits) used during the experiments. Incorrect connection of power
to the ICs could result in them exploding or becoming very hot - with the
possible serious injury occurring to the people working on the
experiment! Ensure that the power supply polarity and all components
and connections are correct before switching on power.
Building the Circuit
Throughout these experiments we will use TTL chips to build circuits. The steps
for wiring a circuit should be completed in the order described below:
1. Turn the power (Trainer Kit) off before you build anything!
2. Make sure the power is off before you build anything!
3. Connect the +5V and ground (GND) leads of the power supply to the
power and ground bus strips on your breadboard.
4. Plug the chips you will be using into the breadboard. Point all the chips
in the same direction with pin 1 at the upper-left corner. (Pin 1 is often
identified by a dot or a notch next to it on the chip package)
5. Connect +5V and GND pins of each chip to the power and ground bus
strips on the breadboard.
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6. Select a connection on your schematic and place a piece of hook-up
wire between corresponding pins of the chips on your breadboard. It is
better to make the short connections before the longer ones. Mark
each connection on your schematic as you go, so as not to try to make
the same connection again at a later stage.
7. Get one of your group members to check the connections, before you
turn the power on.
8. If an error is made and is not spotted before you turn the power on.
Turn the power off immediately before you begin to rewire the circuit.
9. At the end of the laboratory session, collect you hook-up wires, chips
and all equipment and return them to the demonstrator.
10.Tidy the area that you were working in and leave it in the same
condition as it was before you started.
Common Causes of Problems
1. Not connecting the ground and/or power pins for all chips.
2. Not turning on the power supply before checking the operation of the
circuit.
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates
6. Modifying the circuit with the power on.
In all experiments, you will be expected to obtain all instruments, leads,
components at the start of the experiment and return them to their proper place
after you have finished the experiment. Please inform the demonstrator or
technician if you locate faulty equipment. If you damage a chip, inform a
demonstrator, don't put it back in the box of chips for somebody else to use.
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Digital ICs Pin Diagrams
NAND Gate
NOR Gate
NOT Gate
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OR Gate
AND Gate
Ex - OR Gate
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Expt. No:
STUDY AND VERIFICATION OF LOGIC GATES &

BOOLEAN THEOREMS AND LAWS
Date:
AIM:
To study various logic gates and Boolean Theorems And Laws to verify the
truth table.
COMPONENTS / EQUIPMENTS REQUIRED:
S. No.
Components /
Equipments
Specificatio
n
Quantity
1.
Digital IC trainer kit
---
2.
AND Gate
IC7408
3.
OR Gate
IC7432
4.
NOT Gate
IC7404
5.
NAND Gate
IC7400
6.
NOR Gate
IC7402
7.
Ex-Or Gate
IC7486
8.
Connecting Wires
---
Sufficient Numbers
THEORY:
AND gate: The AND gate is a digital logic gate that implements logical
conjunction - it behaves according to the truth table given. A HIGH output (1)
results only if both the inputs to the AND gate are HIGH (1). If neither or only
one input to the AND gate is HIGH, a LOW output results. In another sense, the
function of AND effectively finds the minimum between two binary digits.
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OR gate : The OR gate is a digital logic gate that implements logical
disjunction - it behaves according to the truth table to the right. A HIGH output
(1) results if one or both the inputs to the gate are HIGH (1). If neither input
is HIGH, a LOW output (0) results. In another sense, the function of OR
effectively finds the maximum between two binary digits.
NOT gate: In digital logic, an inverter or NOT gate is a logic gate
which implements logical negation. The truth table is shown. This represents
perfect switching behavior, which is the defining assumption in Digital
electronics. In practice, actual devices have electrical characteristics that must
be carefully considered when designing inverters. In fact, the non-ideal
transition region behavior of a CMOS inverter makes it useful in analog
electronics as a class A amplifier.
NAND gate: The Negated AND, NO AND or NAND gate is the opposite
of the digital AND gate, and behaves in a manner that corresponds to the
opposite of AND gate, as shown in the truth table. A LOW output results only if
both the inputs to the gate are HIGH. If one or both inputs are LOW, a HIGH
output results. The NAND gate is a universal gate in the sense that any
boolean function can be implemented by NAND gates. NAND gates can also be
made with more than two inputs, yielding an output of LOW if all of the inputs
are HIGH, and an output of HIGH if any of the inputs is LOW.
NOR gate
: The NOR gate is a digital logic gate that implements
logical NOR - it behaves according to the truth table to the right. A HIGH
output (1) results if both the inputs to the gate are LOW (0). If one or both input
is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the
OR operator. NOR is a functionally complete operationcombinations of NOR
gates can be combined to generate any other logical function. By contrast,
the OR operator is monotonic as it can only change LOW to HIGH but not vice
versa.
EX- OR gate: The XOR gate (sometimes EOR gate) is a digital logic
gate that implements an exclusive disjunction; that is, it behaves according to
the truth table shown on the right. A true output (1) results if one, and only
one, of the inputs to the gate is true (1). If both inputs are false (0) and both are
true (1), a false output (0) results. A way to remember XOR is "one or the other
but not both.
LOGIC DIARGAM:
AND Gate:
Logic Diagram:
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OR Gate:
Truth Table:
Logic Diagram
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Truth Table:
Page 112
Y=A+B
NOT Gate:
Logic Diagram:
Truth Table:
NAND Gate:
Truth
Y=A
Y= (AB)
NOR Gate:
Logic Diagram:
DeMorgan's Theorem:
Table:
Logic Diagram
Ex-OR Gate:
Truth Table:
Logic Diagram
Truth Table:
DeMorgan's theorems are extremely useful in simplifying expressions in which a product or

sum of variables is inverted. The two theorems are:
(A+B)' = A'.B'
(A.B)' = A' +B'
Commutative Law:
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A.B = B.A
A+B = B+A
Associative Law:
A. (B.C) = (A.B). C
Observations:
Commutative Law:
Law:
Associative
A(BC)
(AB)
C
DeMorgans Law:
A
(A+B
)
A.B
PROCEDURE:
1. Give the connections as per the pin diagram (AND gate).
2. Switch on the trainer kit.
3. Apply the binary inputs at the appropriate terminal and observe the
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corresponding output.
4. Verify the truth table.
5. Repeat the above procedure for other (OR, NOT, NAND, NOR and Ex-Or)
gates.
INFERENCE AND CONCLUSION:

The logic of AND, OR, NOT, NAND, NOR and EX-OR gates and Boolean
theorems were studied and their truth tables were verified.
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DESIGN AND IMPLEMENTATION OF CODE CONVERTERS

EXPERIMENT:
DATE:
1. OBJECTIVE:
To design and verify the truth table of the following code converters
a.
b.
c.
d.
Binary to Gray converter

Gray to Binary converter &
BCD to Excess3 &
Excess3 to BCD.
2. REQUIREMENTS:
S. No.
1.
2.
Components /
Equipments
Specifications
Quantity
---
Digital IC trainer
NOT, AND, OR, Ex-OR
Gate Connecting wires
IC7404,7408,7432,
7486
1 in each
3. THEORY:
Binary to GRAY Converter:
By representing the ten decimal digits with a four bit Gray code, we
have another form of BCD code. The Gray code however can be extended to
any number of bits and conversion between binary code and Gray code is
sometimes useful. The following rules apply for conversion:
1. The MSB in the Gray code is the same as the corresponding bit in the binary
number.
2. Going from left to right, add each adjacent pair of binary bits to get the
next Gray code bit. Disregard carries.
GRAY to Binary Converter:
To convert from Gray code to binary code, A similar method is used, at
there are some differences. The following rules apply:
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1. The MSB in the binary code is the same as the corresponding digit in the Gray
code
2. Add each binary digit generated to the gray digit in the next adjacent
position Disregard carries.
TRUTH TABLE FOR BINARY TO GRAY CODE CONVERTER:

|
Binary input
output
B3
B2
B1
B0
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Gray code
G2
G1
G0
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K-Map for G3:
K-Map for G2:
K-Map for G1:
K-Map for G0:
Binary to GRAY Logic Diagram :
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TRUTH TABLE FOR GRAY CODE TO BINARY CONVERTOR:

|
Gray Code
G3
G2
G1
G0
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Binary Code
B2
B1
B0
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K-Map for B3:

for B2:
K-Map
K-Map for B1:

for B0:
K-Map
GRAY to Binary LOGIC DIAGRAM
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TRUTH TABLE FOR BCD TO EXCESS-3 CONVERTOR:

|
|
BCD input
B3
B2
B1
B0
Excess 3 output
G3
K-Map for E3:

for E2:
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G2
G1
G0
K-Map
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K-Map for E1:

for E0:
K-Map
BCD TO EXCESS-3 Convertor Logic Diagram
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TRUTH TABLE FOR EXCESS-3 TO BCD CONVERTOR:

|
|
Excess 3 Input
B3
B2
B1
B0
BCD Output
G3
K-Map for A:
G2
G1
G0
K-Map
for B:
K-Map for C:
K-Map
for D:
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EXCESS-3 TO BCD convertor Logic diagram:
4. PROCEDURE:
1. Connections are given as per the circuit diagram (Binary to GRAY).
2. Switch on the power supply.
3. Verify the truth table given for different inputs.
4. Repeat the above procedures for other converters.
5. Results:
INFERENCE:
Thus the truth tables for Binary to Gray, Gray to Binary and BCD to
Excess3 converters were verified.
CONCLUSION:
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DESIGN AND IMPLEMENTATION OF 4 BIT BINARY ADDER / SUBTRACTOR

USING IC 7483
EXPERIMENT:
DATE:
1. OBJECTIVE:
To study the 4 bit binary adder/subtractor using IC7483.
2. REQUIREMENTS:
S.No
.
Name of the apparatus
Specificati
ons
Quantity
Digital Trainer kit
OR gate
IC 7432
AND gate
IC 7408
Binary Adder / Subtractor
IC 7483
Connecting wires
some
3. THEORY:
The full adder/sub tractors are capable of adding/subtracting only two
single digit binary numbers along with a carry input. But in practice we need to
add/subtract binary numbers, which are much longer than just one bit. To
add/subtract two n-bit binary numbers we need to use the n-bit parallel
subtractor/adder.
Binary adder:
IC type 7483 is a 4-bit binary parallel
adder/subtractor .The two 4-bit input binary numbers are A1 through A4 and B1
through B4. The sum is obtained from S1 through S4. C0 is the input carry and
C4 the output carry. Test the 4-bit binary adder 7483 by connecting the power
supply and ground terminals. Then connect the four A inputs to a fixed binary
numbers such as 1001 and the B inputs and the input carry to five toggle
switches. The five outputs are applied to indicator lamps. Perform the addition of
a few binary numbers and check that the output sum and output carry give the
proper values. Show that when the input carry is equal to 1, it adds 1 to the
output sum.
Binary subtractor :
The subtraction of two binary numbers can be done by
taking the 2s complement of the subtrahend and adding it to the minuend. The
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2s complement can be obtained by taking the 1s complement and adding. To
perform A-B, we complement the four bits of B, add them to the four bits of A,
and add 1 through the input carry. The four XOR gates complement the bits of B
when the mode select M=1(because x 0 x ) and leave the bits of B unchanged
when M=0(because x 0 x ) .Thus , when the mode select M is equal to 1, the
input carry C0 is equal 1 and the sum output is A plus the 2s complement of B.
when M is equal to 0, the input carry is equal to 0 and the sum generates A+B.
Functional symbol for IC 7483:
Operand1 C0
C4
Operand2
B3 B2 B1 B0
O/P
Pin Diagram of IC7483:
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Circuit Diagram for 4-bit Binary adder/subtractor:
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4-BIT BINARY ADDER:
4-BIT BINARY SUBTRACTOR
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TRUTH TABLE FOR BCD ADDER:

BCD SUM
CARRY
S4
S3
S2
S1
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K MAP
Y = S4 (S3 + S2)
LOGIC DIAGRAM OF BCD ADDER
4. PROCEDURE:
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1. Connections are given as per the circuit diagram.
2. Set mode M =0 such that the circuit will operate in addition mode.
3. Set the Value of inputs A as 1001 and B as 1001 note the sum and output
carry.
4. Repeat the same step in step 3 by keeping M=1 such that circuit will
operate in subtraction mode.
5. RESULTS:
INFERENCE:
Thus the 4 bit Binary Adder / Subtractor using IC7483 is been
implemented for both addition and subtraction and the corresponding truth
tables are verified.
CONCLUSION:
DESIGN AND IMPLEMENTATION

OF
MULTIPLEXER AND DEMULTIPLEXER USING LOGIC GATES
EXPERIMENT: 11
DATE:
1. OBJECTIVE:
To design and implement multiplexer and demultiplexer using logic gates
2. REQUIREMENTS :
S.No
.
Specificati
on
Quantity
Digital Trainer kit
OR gate
IC7432
AND gate
IC7411
NOT gate
IC7404
Connecting wires
3. THEORY:
Multiplexer:
It has a group of data inputs and a group of control inputs. The
control inputs are used to select one of the data inputs and connected to the
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output terminal. It selects one information out of many information lines and
directed to a single output line.
Demultiplexer:
Demultiplexers perform the opposite function of multiplexers. They
transfer a small number of information units (usually one unit) over a
larger number of channels under the control of selection signals. Fig shows
a 1-line to 2-line Demultiplexer circuit. Construct this circuit; connect an
LED to each of the outputs D0 and D1. Set the select signal S to logic 1 or
logic 0, and toggle the input I between logic 1 and logic 0. Which output
followed the input when S = 1 and S = 0.
4:1 MULTIPLEXER:
BLOCK DIAGRAM
Circuit Diagram:
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Truth Table:
1:4 DEMULTIPLEXER:
BLOCK DIAGRAM
Circuit Diagram:
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Truth Table:
TRUTH TABLE:
8X1 Multiplexer
LOGIC DIAGRAM FOR 8:1 MULTIPLEXER:
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1X8 De-Multiplexer:
LOGIC DIAGRAM FOR 1X8 DEMULTIPLEXER:
TRUTH TABLE
1:8 DEMULTIPLEXER:
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PIN DIAGRAM FOR IC 74150:
PIN DIAGRAM FOR IC 74154:
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4. PROCEDURE:
1. Connections are given as per in the circuit diagram.
2. Inputs are given through the logic switches.
3. Outputs are noted and verified with truth table
5.
RESULTS
INFERENCE :
Thus the truth table of multiplexer and demultiplexer was studied and
verified using logic gates.
CONCLUSION:
6. VIVA QUESTIONS:
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1.
2.
3.
4.
5.
6.
What is a multiplexer?
What are the applications of multiplexer?
What is the difference between multiplexer & demultiplexer?
In 2n: 1 multiplexer how many selection lines are used?
Draw a 2 to 1 multiplexer circuit
Draw a 1 to 2 demultiplexer circuit.
DESIGN AND IMPLEMENTATION OF ENCODER
EXPERIMENT:
DATE:
1. OBJECTIVE:
To construct and verify the 8 X 3 Encoder using logic gates.
2. REQUIREMENTS:
S. No
Components /
Equipments
Specificati
on
Quantity
1.
2.
OR Gate
IC7432
3.
Connecting Wires
Sufficient Numbers
3. THEORY:
Digital Computers, Microprocessors and other digital systems are
binary operated whereas our language of communication is in decimal
numbers and alphabetical characters only. Therefore, the need arises for
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interfacing between digital system and human operators. To accomplish this
task, Encoder is used.
Encoder
Lgic Diagram:
Truth Table:
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Outputs:
4. PROCEDURE:
1. Construct the circuit as per the diagram
3. Apply the necessary input and observe the outputs to verify the truth
table.
5.
RESULTS:
INFERENCE:
Thus an 8 x 3 encoder is constructed and verified.
CONCLUSION:
6. REVIEW QUESTIONS:
1. Draw the basic block diagram of a practical decoder.
2. What is the need for decoder?
3. Name the procedure involved in decoding.
4. Give some practical applications where decoding is necessary.
5. List the advantages of decoding.
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DESIGN AND IMPLEMENTATION OF DECODER

EXPERIMENT:
DATE:
1. OBJECTIVE :
To construct and verify the decoder .
2. REQUIREMENTS :
Components /
Equipments
Specification
1.
AND,OR Gate
IC7408,IC7432
2.
IC Trainer Kit
---
3.
Connecting Wires
---
Required
numbers
S. No.
Quantity
Truth Table:
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Circuit Diagram:
3. PROCEDURE:
1.
2.
3.
4.
Connect the circuit as per circuit diagram.

Apply the inputs to the IC7447(A,B,C&D).
Observe the output and verify the result.
RESULTS:
INFERENCE :
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A decoder / driver unit along with 7 segment display unit is
constructed and the results were verified.
CONCLUSION:
6.
REVIEW QUESTIONS:
1. Draw the basic block diagram of a practical decoder.
2. What is the need for decoder?
3. Name the procedure involved in decoding.
4. Give some practical applications where decoding is necessary.
5. List the advantages of decoding.
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTER

EXPERIMENT:
DATE:
1. OBJECTIVE:
To construct and verify the synchronous up/down counters.
2. REQUIREMENTS:
Specification
Quantity
1.
Components /
Equipments
----
2.
JK Flip-Flop, AND Gate
IC 7473,7408
2,1
3.
Connecting wires
----
Sufficient Nos
S. No.
3. THEORY:
Synchronous Counter
Clock input is applied simultaneously to all flip-flops. The output of the first
FLIP-FLOP is connected to the input of second FLIP-FLOP and so on.
Design of synchronous counter
Step 1: Find the number of flip-flops required. For an n-bit counter, nflip-flops is
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required.
Step 2: Write the count sequence in tabular form.
Step 3: Determine the flip-flop inputs, which must be present for the
desired next State from the present state using excitation table of
flip-flops.
Step 4: Prepare K-map for each flip-flop input in terms of flip-flop output
as input
Variables. Simplify the K-map and obtain the minimized expressions.
Step 5: Connect the circuit using the flip-flops.
CIRCUIT DIAGRAM:
Design of 3-bit synchronous up:
Design of 3-bit synchronous down counter:
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Pin Diagram
Truth Table:
3 Bit Synchronous
UP Counter
3 Bit Synchronous
DOWN Counter
Clock
Q2
Q1
Q0
Cloc
k
Q2
Q1
Q0
4. PROCEDURE:
1. The connections are made as per the circuit diagram.
3. The input is given at the appropriate terminal and corresponding
output is observed and truth table is verified.
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5. RESULTS:
INFERENCE:
Thus the counters were constructed and their truth tables verified.
CONCLUSION:
6. REVIEW QUESTIONS
1. Name any four flip-flop used to construct the counter.
2. Draw the basic block diagram of a practical 4-bit counter.
3. What is MOD 5 counter?
4. What is the need for counters?
5. Give some practical applications of counters.
IMPLEMENTATION OF SISO, SIPO, PISO AND PIPO SHIFT REGISTERS
EXPERIMENT:
DATE:
1. OBJECTIVE:
To implement the 4 bit shift register using flip flops and to study the
operations in the following modes.
(i)
(ii)
(iii)
(iv)
Serial in serial out

Serial in parallel out
Parallel in parallel out
Parallel in serial out
2. REQUIREMENTS:
S.No
.
Digital Trainer kit
D Flip Flop
Connecting wires
Range
Quantity
1
IC 7474
2
some
3. THEORY:
SHIFT REGISTER:
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A register is a device capable of storing a bit. The data can be serial
or parallel. The register can convert a data from serial to parallel and vice versa
shifting then digits to left and right is the important aspect for arithmetic
operations,
A register capable of shifting its binary information either to the right or
to the left is called a shift register. An N bit shift register consists of N flip-flops
and the gates that control the shift operation. A shift register can be used in four
different configurations depending upon the way in which the data are entered
into and taken out of it. These four configurations are:
a.
b.
c.
d.
Serial-input, Serial-output
Parallel-input, Serial-output
Serial-input, parallel-output
Parallel-output, parallel-output
The serial input is a single line going to the input of the leftmost flip-flop of
the register. The serial output is a single line from the output of the rightmost
flip-flop of the register, so that the bits stored in the register can come out
through this line one at a time.
The parallel output consists of N lines, one for each of the flip-flops in the
register, so the information stored in the register can be inspected through these
lines all at once.
PIN DIAGRAM:
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Logic Diagram for Serial in Serial out:
Logic Diagram for Serial in Parallel Out:
Logic Diagram for Parallel In Parallel Out
Logic Diagram for Parallel in Serial out
Semester 03
of Technology
Department of ECE
Page 148
TRUTH TABLE FOR SHIFT REGISTERS:
4. PROCEDURE:
1.
circuit.
2.
set inputs.
3.
4.
5.
The flip-flop is connected using connecting wires as shown in the

The flip flop are then reset to zero internally with the help of reset to
The bits are shifted in by giving suitable clock input.
Thus the truth table is then verified.
RESULTS:
INFERENCE:
Thus the operation of 4 bit shift register for SISO, SIPO, and
PIPO was studied and verified.
Semester 03
of Technology
Department of ECE
Page 149

CONCLUSION:
Semester 03
of Technology
Department of ECE
Page 150

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EC6311 Analog and Digital Lab

RAJALAKSHMI INSTITUTE OF TECHNOLOGY

EC6311 Analog and Digital Lab

EC6311 Analog and Digital Lab

EC6311 Analog and Digital Lab

EC6311 Analog and Digital Lab

Design and Analysis of Class A amplifier

Design and Analysis of Class B amplifier

Design and Analysis of Half-wave rectifier

Design and Analysis of Full-wave rectifier

Design and Analysis of Differential Amplifier

EC6311 Analog and Digital Lab

Pspice Simulation of Common Emitter Amplifier

Pspice Simulation of Common source Amplifier

Design and implementation of code converters using logic gates

Design and implementation of 4 bit binary Adder/ Subtractor and

Design and implementation of Multiplexer and De-multiplexer using logic

Design and implementation of encoder and decoder using logic gates

Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12

Design and implementation of 3-bit synchronous up/down counter

EC6311 Analog and Digital Lab

Name of the Experiment

EC6311 Analog and Digital Lab

Common Emitter Amplifier circuit diagram

CE Amplifier with Feedback:

EC6311 Analog and Digital Lab

COMMON EMITTER AMPLIFIER

EC6311 Analog and Digital Lab

(ii) To calculate R1&R2:

EC6311 Analog and Digital Lab

(iii) Input coupling capacitor :

(iv) Output coupling capacitor:

EC6311 Analog and Digital Lab

/2 and vary the input signal frequency

incremental steps and note down the corresponding

Set Vin = 0 by reducing the amplitude of the input signal from

and Voltage drop across base emitter junction. V BE

= _______ (REVERSE BIAS)

4. Ic( Ic = (Vcc VCE ) / Rc) =________

EC6311 Analog and Digital Lab

b. Maximum signal handling capacity :

CRO across RL.

maximum input voltage V

across VBE at which the

sinusoidal signal gets distorted during the process which can

EC6311 Analog and Digital Lab

4. TABULATION [Without Feedback ] :

GAIN= 20 log Vo/Vin

EC6311 Analog and Digital Lab

GAIN= 20 log ( vo/vin )

EC6311 Analog and Digital Lab

EC6311 Analog and Digital Lab

Common Collector Amplifier Circuit Diagram:

EC6311 Analog and Digital Lab

COMMON COLLECTOR AMPLIFIER

EC6311 Analog and Digital Lab

Design of Common collector amplifier:

To calculate Zb ( Device input impedance )

EC6311 Analog and Digital Lab

To calculate Zi ( Input Impedance )

(iii) To Calculate Voltage gain Av :

impedance matching and as a buffer amplifier.

When a positive half-cycle of the input signal is applied

to Base emitter junction of transistor the forward bias voltage V be is increased,

Analog & Digital Student Lab Manual

Analog & Digital Student Lab Manual