IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO.

1, JANUARY 2007

169

Z -Source Current-Type Inverters: Digital

Modulation and Logic Implementation

Poh Chiang Loh, Member, IEEE, D. Mahinda Vilathgamuwa, Senior Member, IEEE,
Chandana Jayampathi Gajanayake, Li Tyan Wong, and Chiew Ping Ang

AbstractTraditionally, current source (CS) inverters have

been adopted for use in medium and high power industry applications. These inverters, however, support only currentbuck
dcac power conversion and need a relatively complex modulator,
as compared to conventional voltage source (VS) inverters. To
address these limitations, this paper presents an integration of
the buckboost -source power conversion concept to the CS
inverter topology to develop single- and three-phase -source CS
inverters. For their efficient control, the paper starts by evaluating different carrier-based reference formulations to identify
different inverter state placement possibilities. The paper then
proceeds to design appropriate reference-to-switch assignments
or logic equations for mapping out the correct CS gating signals,
allowing a simple carrier-based modulator to control a -source
CS inverter with complications such as commutation difficulties
and many-to-many state assignments readily resolved. The
developed system can be implemented using a digital signal
processor with an embedded VS pulse-width modulator and an
external programmable logic device, hence offering a competitive
solution for medium power single and three-phase buck-boost
power conversion. Theory, simulation, and experimental results
are presented in the paper.
Index TermsBuck-boost, current source (CS) inverters, digital
logic, pulsewidth modulation (PWM).

I. INTRODUCTION
NE of the commonly used inverter topologies for medium
and high power industry applications [1], [2] is the traditional current-source (CS) inverter. The CS inverter is known
to have the advantages of implicit output short-circuit protection and improved load harmonic filtering achieved by its ac
output capacitors. Despite these advantages, CS inverter suffers
from the limited capability of only dcac current-buck conversion and requires a relatively more complex pulsewidth modulator (PWM) [3]. The constraint of CS inverter allowing only
currentbuck power conversion makes it not suitable for low
voltage operation, and usually requires an addition of a controlled front-end buck rectifier for stepping down the dc link

Manuscript received August 16, 2005; revised January 17, 2006. This
paper was presented at the 40th IEEE IAS Annual Meeting Conference,
Kowloon, Hong Kong, October 26, 2005. This work was supported by the
Defense Science and Technology Agency, the Ministry of Defense (Singapore),
and Nanyang Technological University under Grants MD-NTU/05/04 and
SUG30/04. Recommended for publication by Associate Editor P. Barbosa.
P. C. Loh, D. M. Vilathgamuwa, C. J. Gajanayake, and C. P. Ang are with the
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore S639798 (e-mail: pcloh@ieee.org; emahinda@ntu.edu.sg;
chan0178@ntu.edu.sg).
L. T. Wong is with Citibank Singapore, Ltd., Singapore S639798.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2006.886618

voltage in order to achieve both buck and boost conversion.

Having a controlled rectifier would, however, complicate the inverter control and synchronization, and might not function well
under severely distorted supply conditions.
An alternative buckboost approach reported in [4] is to connect a uniquely designed -source impedance network between
the input power source and inverter circuit, and has since been
proven experimentally in [4][8] using a voltage-source (VS)
inverter. Based on similar concepts, a dual -source CS inverter
has also been described in [9], but was only briefly investigated
in simulation with many modulation, design and implementation issues left unresolved. These issues are now addressed in
this paper to provide readers with a thorough and comprehensive reference on single and three-phase -source CS inverter
modulation and digital logic implementation.
To assist in conceptual understanding, the paper starts by reviewing basic differences between traditional and -source CS
inverters, and presenting mathematical procedure for proving
the buck-boost capability of a -source CS inverter. The paper
then evaluates different reference formulations needed for carrier-based PWM, and presents generic logic equation designs
for mapping out the correct CS gating signals for both single and
three-phase -source CS inverters. Digital logic modules for resolving commutation difficulties and many-to-many state assignments are also presented using both linguistic statements
and logic equations to provide readers with a clear step-by-step
design procedure. Simulation and experimental results are presented for validating the theoretical concepts developed in the
paper.
II. PRINCIPLES OF OPERATION
The topologies of -source VS and CS inverters are shown
in Fig. 1(a) and (b), respectively, with a X-shaped impedance
and
) and canetwork, comprising of split-inductors (
pacitors ( and ), coupled between the input power source
and inverter circuit. For a VS inverter, this unique impedance
network allows the turning ON of both switches of the same
phase-leg (e.g., S1 and S4) simultaneously to boost the magnetic
energy stored in the dc-side inductors without short-circuiting
the dc capacitors (shoot-through state) [4][8]. This increase
in inductive energy is subsequently used to boost the voltage
across the ac load when the inverter reverts back to one of its
traditional (non-shoot-through) active or null switching states.
The -source network therefore allows the VS inverter to
boost its output voltage in addition to its traditional buck
functionality.
Similarly, unlike a traditional CS inverter where an upper and
a lower power switch are always turned ON to conduct the dc

0885-8993/$25.00 2007 IEEE

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Fig. 1. Topologies of

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007

Z -source:

(a) VS inverter and (b) CS inverter.

link current
, a -source CS inverter can assume an additional open-circuit state by turning OFF all switches without
breaking any inductive current. The impact of open-circuiting
the -source CS inverter can be explained by considering the
equivalent circuits in Fig. 2. During the open-circuit time interval , the inverter side of the -source network is opened by
turning OFF all switches (equivalent to switch OFF in Fig. 2).
At the same time, diode turns ON to conduct the excess curas observed later), and to allow magnetic
rent of (
and
to be transferred to electrostatic enenergy stored in
and . Assuming that
and
ergy stored in
, the circuit equations can be written as

(1)
When in the non-open-circuit state during interval , an
upper and a lower switch of the inverter conducts to connect the
line voltage across the ac filter capacitors, represented as voltage
source in Fig. 2, to the inverter side of the -source network
with diode on the source side reverse-biased. would have
a finite value if the upper and lower ON switches are from different phase-legs (active state, e.g., SW1 and SW2), and zero
if both switches are from the same phase-leg (null state, e.g.,
are
SW1 and SW4). Regardless of the value of , , and
and
charged during the non-open-circuit interval, while
release their stored energy to boost the inverter dc-link current
. The circuit equations for the -source impedance network
can now be rewritten as
(2)
Averaging the current through a -source capacitor over a
and assuming a lossless system,
switching period
, or ) and
the peak dc current , peak ac current (

Fig. 2. Equivalent representations of Z -source CS inverter when in (a) opencircuit and (b) non-open-circuit states.

output-to-input voltage ratio

can be written as
(3)
(4)
(5)

gives the ac output of a traditional CS

where the term
is its modulation ratio, and is the angle between
inverter,
the ac voltage and current. Obviously, (3)(5) show that the ac
output current and voltage of the -source CS inverter can be
boosted and bucked, respectively, by increasing (always 1).
III. MODULATION OF SINGLE-PHASE

-SOURCE CS INVERTER

While VS and CS inverters are not exact duals, they do have

much in common in a space-vector sense [3]. It would therefore be expected that modulation of VS and CS inverters can
be intelligently linked so that the more established VS modulator can be used for controlling a CS inverter with only minor
modifications needed. Based on this principle, this section starts
by reviewing single-phase -source VS modulation, and subsequently adapts the VS algorithms for controlling a single-phase
-source CS inverter.
A. Edge-Insertion Carrier-Based Modulation for Controlling
-Source VS Inverter
For a traditional single-phase VS inverter [comprising only
of S1, S3, S4, and S6 in Fig. 1(a)], two sinusoidal references
and
are needed for switching S1 and S3 independently with
their complements used for gating S4 S1) and S6 S3), as
illustrated at the top of Fig. 3 (state sequence and transitions
and
are also shown). To insert shoot-through states
at
for -source VS inverter control, a possible approach is to use

LOH et al.:

-SOURCE CURRENT-TYPE INVERTERS

Fig. 3. EIPWM of single-phase Z -source VS inverter.

two linear references, in addition to

and
(see bottom
of Fig. 3), for inserting two shoot-through states at the edges
of a half-carrier period [6], [7] (hence, the assigned name of
edge-insertion (EI) PWM). As illustrated in Fig. 3, the tasks
and
are still to control S1 and S3 independently
of
10 ,
to generate the same active time interval for S1 S3
while the additional upper (lower) reference line is for inserting
a shoot-through state at the start (end) of a half carrier period
when the carrier is above (below) the reference line. An important feature of the generated -source sequence is that the
inserted shoot-through states only reduce the durations of the
null states with the active interval kept constant. Since both
shoot-through and null states produce the same zero ac line voltages, the generated -source state sequence would still apply
the same normalized voltsec average across the externally connected ac load.
At first sight, EIPWM might appear to have the advantage of
easy implementation, but when physically constructed, it needs
additional digital logic to help the modulator decide on the appropriate shoot-through state to assume among the numerous
possible VS shoot-through combinations (e.g. {S1, S4} ON,
{S3, S6} ON or all switches ON). For the example drawn in
Fig. 3, shoot-through states are implemented by turning ON
only S1 and S4. Obviously, this shoot-through state selection
would result in unequal switching loss distribution since S1 and
S4 switch twice per half carrier period, while S3 and S6 switch
only once (giving a total of six device commutations per half

171

Fig. 4. MRPWM of single-phase Z -source VS inverter.

carrier cycle). Additional cyclic logic is therefore needed for

distributing the switching losses equally over a carrier period or
a longer time interval (e.g., half a fundamental cycle), and can
be implemented using external field programmable gate array
(FPGA) or erasable programmable logic device (EPLD).
B. Modified-Reference Carrier-Based Modulation for
Controlling -Source VS Inverter
An alternative method, termed as modified-reference (MR)
PWM, for inserting shoot-through states to the VS inverter state
sequence is to use four modified references for controlling the
four switches independently. The resultant reference set is ex2)
pressed as (normalized relative to

or
where

(6)

,
,
and
2). The relative placement and
switch assignment of (6) are shown in the lower half of Fig. 4.
For illustration of the shoot-through insertion process,
consider the two positive references
S1 and
S4 for
switching S1 and S4 of a phase-leg. Having the additional refer,
ence
S1 causes Gate S1 to turn ON earlier at
causes
Gate
S4
to
turn
OFF
at
the
origwhile reference
S4
inal time instant
. These switching actions obviously insert a

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007

TABLE I
SINGLE-PHASE Z -SOURCE VS TO CS STATE MAPPING

phase-leg shoot-through with S1 and S4 ON from

to
. Based on the same principle, a second shoot-through
state with the same time duration, and S3 and S6 ON is also into
by the two negative references
serted from
(equal shoot-through intervals would minimize the size of the
dc inductors [8]). Unlike the EIPWM method, MRPWM
inserts the shoot-through states immediately adjacent to the
10 with the active time duration again
active state S1 S3
maintained constant. This adjacent insertion has been designed
such that each power device switches only once per half carrier
period (giving a total of four, which is similar to that of a
conventional VS inverter and better than that of EIPWM),
allowing the modulator to achieve equal switch utilization
implicitly without the need for an external logic device.
C.

-Source VS

CS PWM Conversion

A good starting point when deriving PWM strategies for a

single-phase CS inverter [comprising only of SW1, SW3, SW4,
and SW6 in Fig. 1(b)] from VS modulation theories is to study
their generated switching states and output voltage/current, as
listed in Table I. Analyzing the first four row entries of the table,
it is obvious that the same VS PWM signals can be used for
gating a CS inverter in the non-open-circuit state by simply implementing the following one-to-one logic mapping:
SW1, SW4, SW3, SW6

S1, S3, S4, S6

(7)

On the other hand, when a VS shoot-through state is sensed,

all gating signals of the CS inverter must be turned OFF to
open-circuit its output terminals, as indicated in the fifth row
CS mapping equation
of Table I. The resultant generic VS
1 indicates a VS
can then be written as (where SVSHOOT
shoot-through state)
SVSHOOT
SW1 SW4 SW3 SW6

S1 S4 S3 S6
SVSHOOT S1 S3 S4 S6
(8)

Equation (8) can conveniently be implemented in an external

programmable logic device for generating the correct CS gating
signals when EIPWM is used with a minimum of six device
commutations per half carrier period. For MRPWM, a simple
reference-to-switch reassignment within the carrier-based
modulator would have implicitly implemented (8) without the
need for an external logic device, as illustrated in Fig. 5. In
and
the upper half of that figure, the same references of
can be used for controlling SW1 and SW4 (not SW3) of
a traditional CS inverter independently with their complements

Fig. 5. MRPWM of single-phase Z -source CS inverter.

used for switching SW3 SW1) and SW6 SW4). Modifications needed for controlling a -source CS inverter would
still involve the use of the four references in (6) with their
switch assignments and relative placements slightly modified,
as shown in the lower half of Fig. 5. In the figure, the upper
positive reference
SW3 is now used for switching SW3
0.5 , while the lower positive reference
OFF earlier at
. An open-circuit state
SW1 is for switching SW1 ON at
0.5
to
since during
is therefore introduced from
that interval, none of the upper switches are ON to conduct the
outgoing ac current. Based on the same reasoning, a second
0.5
to
is also introduced
open-circuit state from
by the negative references, confirming the implicit open-circuit
insertion of a MRPWM modulator with a minimum of four
device commutations per half carrier period after a simple
reference-to-switch reassignment is implemented.
IV. MODULATION OF THREE-PHASE

-SOURCE CS INVERTER

For three-phase inverter control, the approach taken in this

section is again to present PWM strategies for -source VS inverter before logically mapping them for -source CS inverter
control.
A. Edge-Insertion Carrier-Based Modulation for Controlling
-Source VS Inverter
Fig. 6 shows the reference placements for EI modulation of
a three-phase -source VS inverter. In the figure, a three-phase

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-SOURCE CURRENT-TYPE INVERTERS

173

Fig. 6. EIPWM of three-phase Z -source VS inverter.

Fig. 7. MRPWM of three-phase Z -source VS inverter.

set of sinusoidal references

is used for determining
the active state intervals and the two linear references are used
for inserting two shoot-through states within the null intervals
at the start and end of a half carrier cycle (giving a total of
eight device commutations per half carrier cycle). Again, the
normalized inverter voltsec average is not altered, and external
logic must be implemented for selecting the appropriate shootthrough state from the numerous alternatives available (e.g.,
{S1, S4} ON, {S3, S6} ON, or {S5, S2} ON) with the main
objective usually being to equalize the inverter switching losses
among the power devices.

constant to maintain the correct voltsec average. Specifically,

and
in Fig. 7 are for
inserting the first shoot-through state by turning ON S1 and S4,
and
are for the second
shoot-through state by turning ON S3 and S6, and
and
are for the last shoot-through
state by turning ON S5 and S2. Instead of three shoot-through
states, a modification to (9) can conveniently be implemented
and
to
and 0, respectively, for inby changing
serting only two shoot-through states within the null intervals
at the start and end of a half carrier cycle. The only difference
between the modified MRPWM and EIPWM is that the modified MRPWM inserts the two shoot-through states adjacent
to the ends of the total active interval, while EIPWM inserts
the shoot-through states adjacent to the edges of the half carrier
cycle. Another feature of the presented three-phase MRPWM
is that its adjacent insertion of shoot-through states always ensures six device commutations per half carrier period, regardless
of the number of shoot-through states (two or three) inserted,
with the switching losses implicitly distributed among the power
devices by the PWM modulator without having to implement
external equalization logic.

B. Modified Reference Carrier-Based Modulation for

Controlling -Source VS Inverter
MR modulation of a three-phase -source VS inverter is
shown in Fig. 7, where six modified references are used for
controlling the six inverter switches independently [8]. Mathematically, the modified references are expressed as

C.

or
where

(9)

,
,
,
are three sinusoidal
0.5
is the triplen offset
references and
used to maintain equal null durations at the start and end of a
half carrier period to achieve optimal harmonic performance
[8].
The relative placements of (9) are shown in the lower half of
Fig. 7, where three shoot-through states are inserted immediately adjacent to the active states with the active intervals kept

-Source VS

CS PWM Conversion

As for the single-phase system described earlier, some

external mapping logic is needed for converting the eight
non-shoot-through (active and null) VS switching states with
three instantaneous ON signals to the nine non-open-circuit CS states with two ON signals, and the numerous VS
shoot-through states to the single CS open-circuit state with
no switches conducting, as shown in Fig. 8. For active states,
direct one-to-one mapping exists, and therefore each CS
gating signal can be expressed in terms of the VS gating
signals without any additional constraining criteria needed.
As an example, consider the derivation of the CS SW1 signal
in Fig. 8, where SW1 is defined to turn ON when in active
states SC1 OR SC6, which also means SV1 OR SV6

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007

Fig. 8. Illustration of digital logic for three-phase Z -source VS to CS state mapping.

due to the one-to-one logic mapping. Logically, SW1 can

SC6
SV1
SV6
then be written as SW1 SC1
S1 S3 S5 S1 S3 S5
S1 S3
S1 S6. Following
the same reasoning, the set of logic equations for active state
mapping is given as
SW1
SW3
SW5

S1 S6
S2 S3
S4 S5

SW4
SW6
SW2

S3 S4
S5 S6
S1 S2

CS EIPWM or MRPWM can be expressed as

(10)

Before incorporating null mapping to (10), additional

logic criteria must be stated to select the appropriate null
mapping from the numerous many-to-many mappings
available. One common criterion is to minimize the number
of logic transitions per half carrier cycle, and a possible
mapping is shown in Table II, where the null selection is
determined by the sextant that the reference phasor is in,
as indicated by identifier {G1, G2}. With this null mapping, SW1 will also be turned ON when in SC7 AND
00, which in turn means SV0 OR
in sextant G1, G2
00. Logically, that means
SV7 AND in sextant G1, G2
SV0 SV7 G1 G2 SVNULL G1 G2, where
SW1
SVNULL S4 S6 S2 S1 S3 S5 is used to indicate a
null state. With the null mapping added, (10) is rewritten as
SW1
SW4
SW3
SW6
SW5
SW2

S1
S3
S2
S5
S4
S1

S6
S4
S3
S6
S5
S2

G1
G1
G1
G1
G1
G1

G2
G2
G2
G2
G2
G2

SVNULL
SVNULL
SVNULL
SVNULL
SVNULL
SVNULL

TABLE II
NULL MAPPING BASED ON RESIDING SEXTANT

(11)

Last, with the addition of the many-to-one mapping for

converting all VS shoot-through states to a single CS open-circuit state, the resultant generic Boolean equations for use with

SVSHOOT S1 S4 S3 S6 S2 S5
SW1 SVSHOOT S1 S6 G1 G2 SVNULL
SW4 SVSHOOT S3 S4 G1 G2 SVNULL
SW3 SVSHOOT S2 S3 G1 G2 SVNULL
SW6 SVSHOOT S5 S6 G1 G2 SVNULL
SW5 SVSHOOT S4 S5 G1 G2 SVNULL
SW2 SVSHOOT S1 S2 G1 G2 SVNULL (12)
which give an open-circuit state with all switches (SW1SW6)
1, and one of the non-open-circuit
OFF when SVSHOOT
0. Although (12) fully mapped out
states when SVSHOOT
the required CS gating signals, its use can still result in unwanted
switching when commutating across sextants in the null state.
As an example, assume that the CS inverter is initially in sex30
30 , and is about to cross over to sextant
tant
30
90 in the null state SC7. At the instant of cross
over, the sextant identifier {G1, G2} changes from {00} to {01},
which in turn causes the inverter to switch from SC7 to SC9.
This null-to-null switching involves turning OFF both SC1 and
SC4, and turning ON SC2 and SC5 (four transitions in total),
which should be avoided. A simple method to overcome this
complication is to latch the identifier {G1, G2} (using -latches
or flip-flops), preventing it from changing when in a null state
even when a sextant commutation occurs. The identifier is allowed to update only after a null-to-active state transition occurs. Effectiveness of this method in maintaining a minimum of

LOH et al.:

-SOURCE CURRENT-TYPE INVERTERS

175

Fig. 9. Block representation of implemented digital CS modulator.

six device commutations in every half carrier period is tested in

Section V using an experimental prototype.
D. Compensation for VS

CS Conversion Phase Lead

Notice from Fig. 8 that the CS vector diagram leads the VS

diagram by 30 . Using the digital mapping logic in Section IV-C
would then result in a three-phase set of line currents leading
their references by 30 . A convenient way for compensating this
phase-lead is to perform the following three-phase subtractions
,
120 and
assuming that
120

Fig. 10. Simulated filter capacitor voltage v , filtered current i and unfiltered
current i (top to bottom) of a single-phase Z -source CS inverter without open0 and M
0.6.
circuit state, T =T

(13)
where
lag
by 30 (the introduced
gain of 3 can conveniently be compensated by normalization).
as intermediate references for CS moduUsing
lation described above (see Fig. 9) would then result in a set of
by 30 , but in
three-phase line currents leading
as required.
phase with the original references
V. SIMULATION AND EXPERIMENTAL RESULTS
The performance of the derived generic CS switching logic
has been verified in Matlab/Simulink simulation for single and
three-phase -source CS inverters using both EIPWM and
MRPWM. The results obtained show that the generic logic
functions equally well with both EIPWM and MRPWM,
and to meet the given page limit, only results for the theoretically more complex MRPWM are presented here for
performance demonstration. Experimental verification using
the more commonly adopted three-phase CS inverter prototype
has also been performed. The prototype was implemented
by connecting an existing laboratory CS inverter (rated at
600 V, 50 A using Semikron semiconductor modules) to a
-source impedance network constructed using existing com40 mH (rated at 10 A) and
ponents of
15 F (rated at 450 V) with an input source
3 A powering the network. The ac output of the
of
network emulating a
inverter was in turn connected to a
filter and an external load implemented using
second-order
2 mH (rated at 10 A),
15 F (rated at 450 V) and a
resistive load bank adjusted to 15 . The resulting -source
CS inverter was switched digitally at 5 kHz using the control
arrangement shown in Fig. 9, where the digital signal processor
(DSP) with VS PWM peripheral was used for generating the

Fig. 11. Simulated filter capacitor voltage v , filtered current i and unfiltered
current i (top to bottom) of a single-phase Z -source CS inverter with open0.288 and M
0.6.
circuit state, T =T

VS gating signals and the external digital logic card was used
for converting the VS signals to CS signals using the generic
logic presented in the paper.
Figs. 10 and 11 show the single-phase inverter output wave0,
0.6) and with (
0.288,
forms without (
0.6) open-circuit states respectively. In the figures, the
peak inverter dc link current is boosted from 3 A to 7.1 A,
while the inverter ac output is boosted from 1.8 A to 4.2 A with
kept constant at 3 A, hence clearly confirming the currentbuck and boost functionalities of the -source CS inverter. Experimental waveforms obtained using the three-phase inverter
prototype are shown in Figs. 12 and 13 under the same operating conditions and with the same voltage boosting observed
at the inverter dc link and ac output. Another feature noted from
Figs. 1013 is that the voltage across the ac filter capacitor
(
, , or ) is also boosted during the shoot-through state
insertion. This can be explained by noting that with a larger
, , or ) flowing through the fixed
boosted current (
load (15 , 2 mH) used in this work, the corresponding load (or
filter capacitor) voltage is also boosted with more power conis kept constant, a corsumed. Since the dc source current
must happen
responding increase in average source voltage

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TABLE III
SUMMARY OF PRESENTED PWM TECHNIQUES FOR CONVENTIONAL AND Z -SOURCE CS INVERTERS

Fig. 12. Experimental filter capacitor voltage v (25 V/div), filtered current i
(2 A/div) and unfiltered current i (5 A/div) (top to bottom) of a three-phase
0 and M 0.6.
Z -source CS inverter without open-circuit state, T =T

Fig. 14. CS gate signals (level 1 for upper switches and level 0.5 for lower

30 with (shaded) open-circuit state, T =T
switches) during 30
0.288 and M
0.6.

 

Fig. 13. Experimental filter capacitor voltage v (50 V/div), filtered current i
(5 A/div) and unfiltered current i (10 A/div) (top to bottom) of a three-phase
Z -source CS inverter with open-circuit state, T =T
0.288 and M 0.6.

to supply the additional power consumed by the load. Despite

and , the principle of conthe increases in both voltages
to
versation of energy would force the voltage ratio of
be smaller when shoot-through states are inserted [see (5)]. The
smaller voltage ratio can in turn be viewed as a voltage-buck
operation when normalized with respect to the input voltage.
Next, for better illustrating the proper functioning of the designed generic CS mapping logic, Figs. 14 and 15 show the six
CS gating signals obtained internally on the digital logic card
30 and during sextant transition
when in sextant 30

Fig. 15. CS gate signals (level 1 for upper switches and level 0.5 for lower
switches) during transition from 30

90 to 90

150 with
0.288 and M
0.6.
(shaded) open-circuit state, T =T

 

 

LOH et al.:

-SOURCE CURRENT-TYPE INVERTERS

from 30
90 to 90
150 . Clearly, Fig. 14 shows
the use of only null state SC7 (SW1 and SW4 of Phase A ON simultaneously, see uppermost plot in Fig. 14) at the start and end
30 ,
of every half carrier cycle when in sextant 30
while Fig. 15 shows the avoidance of null-to-null state transition (SC9 SC8, see Table II), and hence unwanted switching
30 ms by using the -latch
during sextant commutation at
logic described in Section IV-C. The inverter starts to use the
new null state SC8 only from the next null interval onwards
150 .
when in 90
VI. CONCLUSION
This paper presents the development of single- and threephase -source CS inverters controlled using appropriate carrier-based reference formulations and synthesized digital logics
(see Table III for a summary of the various modulation logics
discussed). Some particular advantages of digital logic control
are that it allows the use of a VS modulator for controlling
a -source CS inverter with complications such as commutation difficulties, many-to-many state assignments , and digital sampling coordination resolved, and can be implemented
using a low-cost DSP with embedded VS PWM peripheral and
a programmable logic device. The practicality and proper functioning of the designed inverter have been confirmed in simulation and experimentally using a three-phase laboratory inverter
prototype.

177

[7] M. S. Shen and F. Z. Peng, Maximum constant boost control of

the Z -source inverter, in Proc. IEEE-IAS Annu. Meeting, 2004, pp.
142147.
[8] P. C. Loh, D. M. Vilathgamuwa, Y. S. Lai, G. T. Chua, and Y. W.
Li, Pulse-width modulation of Z -source inverters, in Proc. IEEE-IAS
Annu. Meeting, 2004, pp. 148155.
[9] X. P. Fang, Z. M. Qian, Q. Gao, B. Gu, F. Z. Peng, and X. M. Yuan,
Current mode Z -source inverter-fed ASD system, in Proc. IEEE
PESC04, 2004, pp. 28052809.
Poh Chiang Loh (S01M04) received the B.Eng (with honors) and M.Eng degrees from the National University of Singapore in 1998 and 2000, respectively,
and the Ph.D. degree from Monash University, Victoria, Australia, in 2002.
During the Summer of 2001, he was a Visiting Scholar with the Wisconsin
Electric Machine and Power Electronics Consortium, University of WisconsinMadison, where he worked on multilevel inverter control and its synchronized
implementation. From 2002 to 2003, he was a Project Engineer with the Defense Science and Technology Agency, Singapore, managing major defense infrastructure projects and exploring new technology for defense applications.
Since 2003, he has been an Assistant Professor with Nanyang Technological
University, Singapore, and in 2005, he was a Visiting Researcher at the University of Hong Kong, China, and Aalborg University, Aalborg, Denmark.

D. Mahinda Vilathgamuwa (S90M93SM99) received the B.Sc. degree

from the University of Moratuwa, Sri Lanka, in 1985 and the Ph.D. degree from
Cambridge University, Cambridge, U.K., in 1993, both in electrical engineering.
He joined the School of Electrical and Electronic Engineering, Nanyang
Technological University, Singapore, in 1993 as a Lecturer and he is now
an Associate Professor. He has published more than 80 research papers in
refereed journals and conferences. His research interests are power electronic
converters, electrical drives, and power quality.
Dr Vilathgamuwa is the co-Chairman of the Power Electronics and Drives
Systems Conference 2005 (PEDS05).

REFERENCES
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Chandana Jayampathi Gajanayake received the B.Sc. degree in electrical and

electronic engineering from the University of Peradeniya, Sri Lanka, in 2003
and is currently pursuing the Ph.D. degree in the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore.

Li Tyan Wong received the B.Eng. degree in electrical and electronic engineering from the Nanyang Technological University, Singapore, in 2005.
Since 2005, she has been with Citibank Singapore, Ltd., as a Financial Advisor.

Chiew Ping Ang received the B.Eng. degree in electrical and electronic engineering from the Nanyang Technological University, Singapore, in 2005.