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TDM Pulse Code Modulation

Transmitter and Receiver


Trainer ST2153 and ST2154

Operating Manual
Ver.1.1

An ISO 9001 : 2000 company

94-101, Electronic Complex Pardesipura,


Indore- 452010, India
Tel : 91-731- 2570301/02, 4211100
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ST2153 & ST2154

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ST2153 & ST2154

TDM Pulse Code Modulation Transmitter and Receiver Trainer ST2153 and
ST2154
Table of Contents
1.
2.
3.
4.
5.
6.
7.

8.

9.

10.

TDM PCM ST2153s Features


TDM PCM ST2153s Technical Specifications
ST2154s Features
ST2154s Technical Specifications
Pulse Modulation Techniques
Pulse Code Modulation
Digital Communication System

Experiment 1
Study of Error Check Codes
A/D Conversion

19

Experiment 2
Study of Analog to Digital Conversion
Digital Transmission

21

26

Experiment 3
Study of Control Signals and their Timings

23

Time Division Multiplexing

29

Experiment 4
Study of Time Division Multiplexing

32

Experiment 5
Study of Pseudo Random Sync Code Generator

33

Experiment 6
Study of Three Modes of Transmission

35

Experiment 7
Computer Communication using RS232 interface via ST2153 &
ST2154

44

Experiment 8
Multi point to multipoint communication using RS232 interface
via ST2153 & ST2154

46

11.
12.
13.
14.

4
4
5
5
6
9
12
16

Experiment 9
Point to multipoint communication using RS232 interface via
ST2153 & ST2154
Switched Faults
Setting up the Receivers clock regeneration circuit
Warranty
List of Accessories

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50
52
53
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ST2153 & ST2154

ST2153 :

Features
Crystal Controlled Clock.
On-board Sine wave generator (Synchronized).

2 TDM Analog Channels.

PCM Transmitter.

Fast & Slow modes for real time operation and data flow examination.

Error check code options (odd-even parity, Hamming Code).

4 Switched faults allow different Error Check Options.

PC-PC Communication via RS232 interface.


Technical Specifications

Crystal Frequency

12 MHz

On Board Analog Signal

1 KHz, 2 KHz (sine wave synchronized to


sampling pulse Adjustable amplitude and
separate variable DC level)

Input Channels

Two

Multiplexing

Time Division Multiplexing

Modulation

Pulse Code Modulation

Sync Signal

Pseudo random sync code generator

Error Check Code

'Off'-Odd - Even - Hamming

Operating Mode

Fast: 240 KHz / channel (approximately)


Slow: 1Hz/ channel (approximately)

PC -PC communication

Using 2 channels via RS232

Port

9 Pin D type connector - 2Nos

Baud Rate

Selectable from 300 to 2400

Test Points

49 in numbers

Interconnections

4 mm Sockets

Power Supply

230 V 10%, 50 Hz

Power Consumption

4 VA (approximately)

Dimensions (mm)

W 420 x H100 x D255

Weight

2.5 Kgs. (approximately)

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ST2154 :
Features

Input accepts two channel multiplexed data.

On board De-multiplexed PCM Receiver.

On board Low Pass Filter.

Fast & Slow modes for real time operation and data flow examination.

On board PLL for clock regeneration.

On board sync code detector.

Error check code options.

Odd or Even Parity-Single bit error detection.

Hamming code single bit error detection and correction.

4 Switched faults allow different error check code option.

PC-PC Communication via RS232 interface.


Technical Specifications

Input Channel

Time Division Multiplexed Serial Input

Demodulation

Pulse code Demodulation

Clock Regeneration

By phase Locked loop

Operating Speeds

Fast 240 KHz/Channel, Slow 1Hz/ Channel

Error Detection (Single bit) :

'Off'-Odd- Even parity& Hamming code

Error Correction

Hamming code

PC- PC communication

using 2 channels via RS232

Port

9 pin D type connector-2 Nos

Baud rate

selectable from 300 to 2400

Test Points

56 in numbers

Interconnections

4 mm sockets

Power Requirement

230V +/- 10%, 50Hz, 4VA

Dimensions (mm)

W420 x H100 x D255

Weight

2.5 Kgs. (approximately)

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Pulse Modulation Techniques


Pulse code modulation, more popularly known as PCM is the most widely used digital
modulation system. It is a widely known fact that the analog modulation systems are
most prone to the noise present in the channel and receiver. As we will see further that
the digital modulation systems are far less sensitive to noise as compared to analog
modulation. The basis of digital modulation systems lies on pulse modulation i.e. a
particular characteristic of the pulse is varied in accordance with the information
signal.
Pulse Modulation System :
1.

Pulse Amplitude Modulation (PAM) :


In pulse amplitude modulation system the amplitude of the pulse is varied in
accordance with the instantaneous level of the modulating signal. Now days, the
PAM system is not generally used, but it forms the first stage of the other types
of pulse modulation.

2.

Pulse Width Modulation (PWM) :


In PWM system the width of the pulse is varied in accordance with the
instantaneous level of the modulating signal.

3.

Pulse Position Modulation (PPM) :


In PPM System, the position of the pulse relative to the zero reference level is
varied in accordance with the instantaneous level of the modulating signal.

4.

Pulse Code Modulation (PCM) :


In PCM System the amplitude of the sampled waveform at definite time
intervals is represented as a binary code. The first three techniques of the above
described systems are not truly digital but in fact are analog in nature. The very
fact that the variation of a particular pulse parameter is continuous rather than
being in the discrete steps makes the system analog in nature.

As a result of this, the PAM signals are vulnerable to noise & dispersion of the pulse.
The channel introduces noise on the signal from various sources. Also the receiver is
not noise free.
The pulses also suffer attenuation & dispersion as they pass through the channel. The
primary line constants (L, C, G, & R) limit the velocity at which a particular
frequency can travel. The result is different frequency travel at different velocities in
the medium. Therefore some frequency component of the square wave arrives later as
compared to the other. This causes widening of the pulse width. The phenomenon is
called 'dispersion. The combined effect of attenuation, dispersion & noise is so large
that the pulse is impaired & introduced at the receiver as shown in figure 1.

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Pulse Train distortion due to Channel Characteristics


Figure 1
Advantages of digital modulation system :
a.

Noise & Distortion :


Pulse which becomes distorted by the addition of noise can be reshaped at the
regenerators installed at pre-determined intervals along the link. Thus within
certain threshold the error will not creep in.

b.

Multiplexing :
The information once sampled & coded can be multiplexed in time domain, i.e.
the coded information from different sources can be sent, one after another, if it
can be re-routed to the corresponding channels at the receiver.
The information is coded in binary form, the source of information / sample,
becomes unimportant. Therefore many different sources such as telephone,
facsimile, telegraphy and video cap are transmitted over same channel &
circuitry.

c.

Store & forward (S & F) facility :


That information which has been binary coded in digital format can be easily
stored in the computer or memory elements, & information can be forwarded at
the desired time. It is required at the time of channel congestion. The message
can be stored in memory. Once the channel becomes clear, the message can be
forwarded to the called party.

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d.

Encryption & security :


The digital devices today are capable of high grade encryption. The data can not
be correctly interpreted if the receiver has no proper decoder. Hence the digital
communication can be highly secured.

e.

Power requirement :
To transmit the digital data over the same channel requires less signal power
than that would be required for same performance of the receiver for analog
systems.

Disadvantages of digital modulation communication system :


a.

Band with requirement :


The digital communication systems need very large bandwidth as compared to
its analog counter part.

b.

Complexity :
The digital transmitter & receivers is the complex due to the requirement of
highly reliable timing information. This adds to complexity as well as to the cost
of the communications system. With the advent of new technology, the digital
circuits / IC's are becoming more and more cheaper Still prices are slightly at the
higher side. But the advantage offered by the digital techniques far overweighs
this consideration.

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Pulse Code Modulation


Steps in Pulse Code Modulation :
Sampling :
The analog signal is sampled according to the Nyquist criteria. The nyquist criteria
states that for faithful reproduction of the band limited signal, the sampling rate must
be at least twice the highest frequency component present in the signal. For audio
signals the highest frequency component is 3.4 KHz.
So,

Sampling Frequency

2 fm
2 x 3.4 KHz
6.8 KHz

Practically, the sampling frequency is kept slightly more than the required rate. In
telephony the standard sampling rate is 8 KHz. Sample quantifies the instantaneous
value of the analog signal point at sampling point to obtain pulse amplitude output.
Allocation of Binary Codes :
Each binary word defines a particular narrow range of amplitude level. The sampled
value is then approximated to the nearest amplitude level. The sample is then assigned
a code corresponding to the amplitude level, which is then transmitted.
This process is called as Quantization & it is generally carried out by the A/D
converter.
See figure 2.

Figure 2

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ST2153 & ST2154

There are two important problems associated with quantization.


a.

Quantization noise :
As we have seen the signal is approximated to the nearest level (step). Since the
levels are discrete where as the signal is continuous, the discrepancy creeps in.
The difference between the analog signal value & its approximated one
(quantized one) is random & unpredictable. This is a sort of unwanted,
unpredictable, random signal which accompanies the information signal and is
termed as 'Quantization noise'.

Quantization noise can be reduced by increasing the number of levels, hence reducing
the approximation. But it can never be eliminated. Increasing the number of levels to
reduce quantization noise has the effect of increasing the number of bits. But nothing
comes without price. Increasing the number of bits to represent a sample increases the
system's bandwidth requirement
b.

Finite sampling time of A/D converter :


Another problem associated with quantization is that the A/D Converter
requires finite time to convert the analog information to digital data. The A/D
Converter requires that the value at its input, remain unchanged till the
conversion is complete. But in practice, the duration of sampled pulse is much
smaller than the A/D converter's sampling time. Refer page 18 & 19 A/D
conversion for details.

This problem can be overcome by using a sample & hold circuit prior to A/D
converter output. The sample & hold circuitry holds the sample value till the next
sample. The encoding method described above is called as uniform encoding i.e. the
quantization levels are uniform for all the amplitude range. But this method of
encoding has disadvantages of its own. The quantization noise plays havoc with the
low level signals because the % approximation compared to the signal amplitude is
very high. This causes a great amount of distortion at the receiver for low level
signals. Also the quieter part of music or speech could become severely distorted &
would make them unpleasant to listen.
To overcome this problem, a non-uniform encoding scheme is used. Here the
quantization levels are clear together for low level than they are for the high levels.
This has an effect of compression on the extreme ends of the signal. The input/output
characteristics for compression signal passed through a comparator network 'prior to
compression (See figure 3). This process is called compression.

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An input output characteristic providing compression


Figure 3
The opposite effect is utilized at the receiver to undo the effect of compression, is
termed as expanding. The two processes are combined are known as compounding
this feature is not provided on trainer but you should be aware of its existence. Some
error correcting codes & synchronization can also be transmitted along with the
information signal.
At receiver, the data is decoded by the D/A converter; the recovered samples are
filtered & reconstructed to provide the original waveform.
Various channels can be multiplexed in time domain i.e. the information data from
various sources are sequentially transmitted over the same transmission medium e.g.
Let us assume a 3 channel PCM system. The system samples 0-2 samples sequentially
providing 3 samples to be converted to 3 "n" bit words. These three n bit words forms
the basis of a frame. The frame contains these three n bit words also contains some
synchronization & reference positioning information.
On more complex multi-channel systems, control & routing information have to be
included. This information is termed as signaling information. If all these information
can not be fitted in a single frame, a separate channel is used for signaling &
synchronization information.
In Europe, a 30 channel PCM System is followed which is specified by CCITT
(International Radio Consultative Committee). Besides these channels, two separate
channels are used for signaling & synchronization information. Here the multi frame
consists of 16 frames.
Multi Frame :
When the number of bits in allocated channels is insufficient to cope with the
synchronization & signaling information then it is spread on defined channels over a
number of frames. This sequence of frames is known as a Multi Frames.
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Digital Communication System


Digital communication systems are less sensitive to noise as compared to their analog
counter part. This fact mostly makes the digital communication systems very popular.
Although the digital communication systems are mostly unaffected by noise, still
there is a probability that the bits are recognized wrongly at the receiver due to noise.
One important parameter which measures the unsuccessful recognition of data bits is
BER (bit error rate). A probability of bit error Pbe-(or BER as it is usually referred)
10 means that, on an average, 1 bit in every 1,00,000 will be in error, For acceptable
quality speech signals the BER/ Pbe should not be more than 10 while some data
transmission systems may require values of Pbe = 10 or less.
Reasons for induced errors in digital system :
a.

Impulse Noise :

It can be defined as a high noise level occurring for a very short time, producing
noise spikes superimposed upon the signal waveform. The source of impulse noise
may be lightning strike or sudden heavy current flow through a system or
electromagnetic radiation etc.
b.

Transmission medium characteristics :

As it has been mentioned earlier, the characteristic of the transmission medium causes
attenuation and dispersion, leading to the indecision pulse level recognition. This can
lead to errors.
c.

Late Switching :

The late switching by some ageing devices or due to loss of synchronization leads to
change in average level & this causes errors to permit us to detect the errors caused by
noise in some cases & to be able to correct them, the method of coding the signal is
adopted.
Coding accomplishes its purpose by deliberate introduction of redundancy in the
message. Their degree of success depends upon the redundancy which they introduce
e.g. Consider that we are transmitting information by means of binary PCM. Then we
transmit a stream of binary digits 0's or 1's. Our main concern is that we do not
confuse a 0 for a 1 or a '1' for a '0'. Suppose that when a '0' is to be transmitted we
transmit 000 & we transmit 111 to represent a digit 1. The other two 0's or 1's add no
information to the message & hence are redundant.
Suppose that the signal to noise ratio on the channel is such that we can be nearly
certain that not more than one error will be made in triplet. Then, if we received 001,
010, or 100, we would actually be certain that the transmitted data was actually 0.
Similarly, if we received 011, 101, or 110 we would be rather certain that the message
was actually 111. Thus the redundancy, deliberately introduced has enabled us to
detect and even correct the error.
But the introduction of redundancy can't guarantee that an error will either be
detectable or correctable. As noise is unpredictable, there is always a finite possibility
that those two errors may occur. In this case we will know that the error has occurred,
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but we will be inclined to read a '0' as a '1' & a '1' as a '0'.


Even There is an over possibility, however small, that all the three bits are in error. In
this case, not only we will misread the digits but we would not even suspect that an
error has been made. Thus we conclude that while coding allows us a great deal of
detection & correction it generally cannot detect or correct all errors. Detection of
errors allows the system to request re-transmission of data. But it does not really solve
the problem. However it does offer the system ability to record and evaluate system
error rate.
A better solution would be to introduce a method of error detection and correction.
The correction is done automatically by receiver. The degree of success depends upon
the redundancy which they introduce.
It is clear that if the redundant message is to be transmitted at the same rate as the
original binary signal, we shall have to transmit more no of bits in time TS otherwise
allocated to a single bit. And it is an established fact that the increase in bit rate may
increase the error rate. Hence the required increased bit rate will undo some of the
advantage that will accrue from redundancy coding. However coding yields a very
worthwhile net advantage. The price to be paid is increased hardware complexity both
for transmitter & receiver where encoding & decoding is affected respectively.
Many different types of codes have been developed and are in use. The commonly
used
Codes employed in ST2153 & ST2154 are :
a)

Parity Coding :

It is the simplest method of error coding. Parity is a method of encoding such that the
number of 1's in a codeword is either even or odd Signal parity is established as
follows. Each word is examined to determine whether it contains an odd or even
number of '1' bits.
If even parity is to be established (known as Even parity), a '1' bit is added to each
word containing odd '1' and a '0' bit is added to each word containing even '1 'so the
result is that all the code words contain an even number of 1 bits after encoding.
Similarly, the parity coding can ensure that the total number of '1's in the encoded
word is odd. In such number of '1's in the encoded word is odd. In such cases it is
called as odd parity.
Continuing with the example of even parity, after transmission, each code word is
examined to see if it contains an even number of 1 bits. If it does not, the presence of
an error is indicated. If it does, the parity bit remains and the data is passed to the
user.
Note that single bit parity code can detect single errors only and it cannot provide
error correction because there is no way of knowing which bit is in error.
It is for this reason that parity coding is normally only used on transmission systems
where the probability of error occurring is deemed to be low.

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b)

Hamming Coding :

Hamming coding, decode each word at the transmitter into a new code by stuffing the
word with extra redundant bits. As the name suggests, the redundant bits do not
convey information but also provides a method of allowing the receiver to decide
when an error has occurred & which bit is in error since the system is binary, the bit
in error is easily corrected.
Three bit hamming code provides single bit error detection and correction.
The ST2153 & ST2154 involves the use of 7 bit word. Therefore only four bits are
used for transmitting data if hamming code is selected. The format becomes.
D6

D5

D4

D3

C2

C1

C0

Where C2, C1 & C0 are Hamming Code Bits


The Hamming code was invented by R.W. Hamming. It uses three redundant bits, as
opposed to the single redundant bit needed by simple parity checking. But it provides
a facility of single bit error detection & correction.
Code Generation on Trainer
The code on this trainer is generated by addicting parity check bit to each group as
shown below :
Group 1

D6, D5, D4

Parity Bit - C2

Group 2

D6, D5, D3

Parity Bit - C1

Group 3

D6, D4, D3

Parity Bit C0

The Groups & Parity bit forms an even parity check group. If an error occurs in any of
the digits, the parity is lost & can be detected at receiver e.g. Let us encode binary
value D6, D5, D4, D3 of '1101'
Group 1
Group 2
Group 3

D6

D5

D4

C2

D6

D5

D3

C1

D6

D4

D3

C0

So, the data word after coding will be


D6

D5

D4

D3

C2

C1

C0

At the receiver, the four digits representing a particular quantized value are taken in as
three groups. The Error Detection/ Correction Logic carries out even parity checks on
the three groups.
Group 1

D6

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D5

D4

C2
14

ST2153 & ST2154

Group 2

D6

D5

D3

C1

Group 3

D6

D4

D3

C0

If none of them fails, then no error has occurred in transmission & all bit values are
valid. Suppose, a case, where the following parity check was carried out & the listed
groups failed.
Group 1
Group 2
Group 3

D6

D5

D4

C2

D6

D5

D3

C1

D6

D4

D3

C0

Failed
Failed
Passed

If we suppose only a signal bit corruption, the passing of Group 3 means that all D6,
D4, D3 & C0 are valid.
In the above two groups the only common element except D6, is D5. As D6 is
received correctly clear from Group 3 the only bit which can be in error is Bit 5 i.e.
D5. Since the corrupted bit has been detected, the receiver can now make changes in
D5 to convert it to other possible value i.e. '0'. Thus the data word is corrected to
0001010. The receiver now discards the redundant check bits (C2, C1 & C0) and
passes the valid data (0001) to the input of D/a converter table given below gives the
location of possible single bit errors.
Parity Check Results on ST2154
Group-l

Group-2

Group-3

Location of

D6 D5 D4 C2

D6 D5 D3 C1

D6 D3 C0

Error

PASS

PASS

PASS

No Error

PASS

PASS

FAIL

C0

PASS

PASS

PASS

C1

PASS

PASS

FAIL

D3

PASS

PASS

PASS

C2

PASS

PASS

FAIL

D4

PASS

PASS

PASS

D5

PASS

PASS

FAIL

D6

Recommended testing instruments needed for experiments in this work book


1.

Oscilloscope 20 MHz, Dual Trace, ALT Trigger with bandwidth

2.

Oscilloscope Probes X1 X10 etc.

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Experiment 1
Objective :
Study of Error Check Codes
Procedure :
1.

2.

3.

Set Up the following initial conditions on ST2153 :


a)

Mode Switch in FAST Position.

b)

DC l & DC 2 amplitude controls in function generator block in fully


clockwise position.

c)

Set ~1 KHz & 2 KHz signal levels in function generator block to 10Vpp.

d)

Pseudo random sync code generator switched On.

e)

Error check code selector switches A & B in A = 0 & B =0 Position ('Off'


Mode).

f)

All switched faults 'Off'.

Set Up the following initial conditions on ST2154 :


a)

Mode Switch in FAST Position.

b)

Pseudo random sync code generator switched On.

c)

Error check code selector switches A & B in A = 0 & B =0 positions ('Off'


Mode).

d)

All switched faults 'Off'.

e)

Pulse generator delay adjusts control in fully clockwise position.

Make the following connections on ST2153 (See Figure 4) :


a)

DC l Output to CH 0 input (TP 10).

b)

CH 0 Input (TP10) to CH 1 input (TP12).


This ensures that the two channels contain the same information.

4.

5.

Make the following connections on ST2154 (See figure 4) :


a)

PCM data input (TP1) to clock regeneration circuit input (TP3).

b)

Output of clock regeneration circuit (TP8) to RX clock input (TP46).

Make the following connections between ST2153 & ST2154 see Figure.4.
a)

PCM output (TP44) of ST2153 to PCM data input (TP1) of ST2154.

b)

Connect the grounds of both the trainers.

6.

Turn On the power. Ensure that the frequency of the VCO in the receiver
clock regeneration circuit has been correctly adjusted

7.

Connect
a)

Channel 1 of oscilloscope to (TP10) on ST2153.

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8.

b)

Channel 2 of oscilloscope to (TP33) on ST2154.

c)

Vary DC l and note that the data is transferred correctly between the two
trainers. You can verify that the data in the A/D converter Block of
ST2153 is always the same as the data in D/A converter Block of ST2154
also the output voltage of TP33 of ST2154 should be same as the input
voltage at TP10 of ST2153 for all DC input levels.

Select even parity with error check code selector switches A & B at A=0 & B=1
position, on both the trainers. Set up various codes from A/D Converter's output
LEDs some containing even no of l's & some odd. Check the error check code
generator output of ST2153. Data latch output (TP16 to 22) on ST2154 & D / A
Converter input (TP23 to 29) on ST2154. Notice the number of '1's in the
transmitted data streams. Is it ever Odd?
Note : ST2153 uses the least significant bit (LSB) of the 7 bit word to transmit
the parity bit. Its value is changed to achieve the correct parity for each word.

9.

Compare the output of the data latch led (TP16 to 22) with input to the D/A
Converter LED in each case. Once the error detection logic has decided whether
an error has occurred, it must pass the received code to the D/A converter. But
since D0 bit was used as parity bit, it is always forced to a '0'. Notice that the
quantized values on output of A/D Converter is not necessary but same to be
applied to D/ A Converter receiver end due to the action of error detection logic.

10.

Set up the error check selector A & B switches to A = 1 & B = 0 position on


both trainers to select the odd parity mode carry out steps 8 & 9 again, but odd
parity selected this time.

11.

Carry out the same experiment with 1 KHz sine wave applied at CH 0 & CH1
Input of ST2153. Adjust the 1 KHz amplitude level fully clock wise.

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Figure 4
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A/D Conversion
The PCM Transmitter samples the analog input, time division multiplex and many
such channels, quantizes it & code it by analog to digital conversion. As it is known,
the binary number system consists of binary digits '0' and '1'. The group of n bits is
called as word and is used to distinguish one code from the other. The range of
decimal numbers represented by such n bits code is equal to 2n (including 0) e.g. If we
take an 8 bit word, the number or different codes possible is equal to 28 = 256 i.e. we
have 0 to 255 code levels available.
This range can be used to indicate any range of voltage. The process of allocating the
binary values to each sample taken in PAM system is known as quantization. Every
binary number indicates one level. Since binary value changes in discrete steps & is
not continuous like analog waveform, some distortion creeps in at the time of value
assignment; this is discussed in forth coming parts. The range of binary values used is
the design feature of the system & depends upon the amplitude range of the signal and
the accuracy of the conversion to be achieved.
Most systems use an 8 bit word length which is practically found most suitable to
cover the sufficient range & provide the accuracy needed for speech signals. As with
all engineering processes, quantization produces its own problems & an engineering
compromise is then called for. The two major problems associated with quantization
are :
1)

One major problem associated with quantization is due to the discrete nature of
binary numbers which are used to represent continuously variable analog
waveform, It is not possible to represent all the analog values (which are infinite
in number) by limited binary words e.g. if in the figure 5, the analog value lies
in between the two voltages represented by 0011 & 0100 binary words, what
will happen?

Figure 5

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ST2153 & ST2154

In such cases the system allocate a binary number closest to the sample value. This
leads to distortion of the information signal & the approximation is random for
different voltage levels. Hence it is known as quantization noise. Quantization noise
can be reduced by increasing the number of bits used to represent a sample. But it can
never be eliminated. Increasing the number of bits in a word has an effect of
increasing the number of quantization levels.
2)

The second problem is associated with the finite time taken by the A/D
Converter to complete the translation from analog to binary code. An A/D
Converter requires that the sample value should remain unchanged till the
conversion is complete, but usually the duration of the sample pulse is much
smaller than the conversion time. This problem can be overcome by using a
sample and hold circuit prior to A/D input. The sample and hold circuit holds
the sample value for the A/D Conversion time. The quantization & Coding
process is carried by the A/D Converter. On ST2153 the A/D converter used is
AD670. It is an 8 bit A/D converter. The A/D conversions are controlled by
R/W, CS, & CE pins. The R/W pin directs the converter to read or start a
conversion. The CE & CS pins are tied to logic 0. The Status pin goes High
indicating that a conversion is in process. At the end of the conversion the Status
pin goes Low. On ST2153 the R/W pin is named as SC (TP7) and pin after
inversion is named as EC (TP8). This EC is used to latch the valid data into Dtype Flip-Flops (see circuit description in operating manual). Only 7 most
significant bits out of 8 data outputs are used on ST2153. The LSB (D0) is
ignored.

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Experiment 2
Objective :
Study of Analog to Digital Conversion
Procedure :
1.

2.

Ensure the following initial conditions on the ST2153.


a.

Mode switch in fast position.

b.

DC l & DC 2 Controls in function generator block, fully clockwise.

c.

~ 1 KHz & ~2 KHz signal controls set to 10Vpp.

d.

Pseudo - random sync code generator switched 'Off'.

e.

Error check code selector switches A & B in A = 0 & B= 0 position ('Off'


Mode).

f.

All switched faults 'Off'.

Connect on ST2153 :
a.

DC l output to CH 0 input

b.

DC 2 output to CH 1 input

3.

Turn On the power. With the help of digital voltmeter / oscilloscope, adjust
the DC l amplitude control until the DC 1 output measures 0V: The accuracy
should be within +/-20mV. Turn the DC 2 amplitude control, fully counter
clockwise.

4.

Observe the output on the A/D converter block LEDs (D0 to D6). The LEDs
represent the state of the binary PCM word allocated to the PAM sample being
processed.
An illuminated LED represent a '1' state, while non illuminated LED indicates a
'0' state. D6 is the MSB & D0 is the LSB. The LED output looks as follows.
D6

D5

D4

D3

D2

D1

D0

This output is the digital representation of 0V input to CH 0


5.

Adjust the DC1 amplitude control clockwise to increase the amplitude &
anticlockwise to decrease it. Try varying the DC input from + 5V to - 5V in
steps of 1V. Take care that the input value is within the specified range of +/20mV. Observe that the output for +5V is as follows :
D6

D5

D4

D3

D2

D1

D0

Where for the negative values it is less than 1000000 for -5V the output is as
follows
D6

D5

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D4

D3

D2

D1

D0
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ST2153 & ST2154

This is obtained at the approximately full anti-clockwise position of the DC


Control.
6.

Turn the DC 1 control fully anti-clockwise and repeat the above procedure by
varying DC 2 control. Check that the digital code for the set voltage value is
identical to that of the DC 1 setting.
Once again take the precaution of maintaining the set input within +/- 20mV
range of the specified voltage.

7.

Switch 'Off' the trainer. Disconnect the DC 1 & DC 2 supply from CH 0 & CH
1. Connect ~1 KHz signal to CH 0 & 2 KHz signal to CH 1 input.

8.

Trigger the dual trace oscilloscope externally by the CH 1 signal available at


TP12. Observe the signal at CH 0 & CH 1 sample output (TP5) with reference
to the SC Signal (TP7) on the second trace. Give a special attention to the phase
relation between the two signals.

9.

Now connect the oscilloscope channel 1 to CH 1 sample (TP6) sketch the three
waveforms with utmost importance to the relationship between the three
waveforms.

10.

Connect oscilloscope channel 1 input to SC test points (TP7) & oscilloscope


channel 2 input to EC test point (TP8).
Observe the phase relation between the two SC & EC test point. Notice that EC
goes high at the end of conversion & remains latched until next SC Pulse.

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Digital Transmission
There are two methods for sending digital data over a distance, namely
a.

Parallel transmission

b.

Serial transmission

In short distance communication like inside terminal equipment or two computer


terminals located near each other, the signals are passed in parallel, format over
parallel wires. Thus the signal in the form of a word is passed. This mode is faster.
For long distances, even more than few feets, this is uneconomical & inefficient way
of transmission. It is a wasteful of transmission media as each bit requires a separate
link. Therefore the digital signals are transmitted serially over a single link.
The two important parameters in serial signaling are
1.

The modulation rate or the signaling rate (in Bauds) &

2.

data transmission rate or bit rate (in Bits per second)

The signaling rate or modulation rate is defined as the maximum rate at which the
signal is switched between signaling rate (or number of symbols transmitted per
second).
The other way of defining modulation rate is that it is the reciprocal of the shortest
time for which the signal remains in any state. The modulation rate is measured in
Baud which is equal to one unit signal element per second. See figure 6.

Figure 6
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From figure 6 it is clear that


S = 1 / T 1 Bauds
e.g. if the shortest pulse duration is 5 ms, then the modulation rate is
S = 1 / 5 x 10-3 = 200 Bauds.
The data transmission rate is defined as the rate at which the data is transmitted over a
channel. Its unit is Bits / second (also written as bps). The data transmission rate is
calculated as
Bit rate = (1 / T1) x log 2 L bits / second.
Where T 1 is the duration of unit signal element and L is the number of levels or the
signaling states. The two terms are often confused in computing because of the use of
binary (0 or 1 state) system.
Signaling rate S = 1 / T 1 Bauds
While the data transmission rate is
Bit rate = 1 / T 1 log 2 2 = 1 / T 1 bits second
If we use 4 state signaling the data transmission rate becomes
Bit rate = 1 / T 1 log 24 = 1 / T 1 x 2 = 2 (1/T 1) = 2 (signaling rate)
i.e. it is twice the signaling (modulating rate)
Bit rate = 1/T 1 log 2 4 = 2/T1 log 22 = 2/T 1 bits/second
In this case the Bit rate is twice the modulation rate. Similarly, the data on out board
is transmitted serially by loading it into the shift register.
The ST2153 uses two 4 bits parallel to serial converter (shift Register). They are
arranged as shown in figure 7. Each shift register can shift only 4 bits and make it a 7
bit register.
The operation of the shift register is shown in figure 8.
As you can notice from figure 8 whatever is on parallel inputs (A, B, C, D) is
reflected as parallel outputs (QA, QB, QC, QD). When S/L is low & there is a
positive (rising) edge of clock pulse. When S/L is high the subsequent shifting occurs
on each positive edge of clock pulse.

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The ST2153's A/D Converter outputs data in parallel format which is change into
serial format by the shift register. This is known as parallel to serial conversion.

Shift Register Organization


Figure 7

Figure 8

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Experiment 3
Objective :
Study of Control Signals and their Timings
Procedure :
1.
Set up the following initial conditions on ST2153 :
a.
Mode switch in fast position
b.
DC 1 & DC 2 Controls in function generator block fully clock wise
c.
~1 KHz & -2 KHz control levels set to give 10Vpp.
d.
Pseudo random sync code generator on / 'Off' switch in 'Off' Position.
e.
Error check code generator switches A & B m A= 0 & B = 0 Position
('Off' Mode).
f.
All switched faults 'Off'.
2.
Make the following connections as shown in figure 9:
I. DC 1
TO
CH 0
II. DC 2
TO
CH 1
3.
Turn On the power.
Adjust the DC1 amplitude control such that the voltage measured at TP10 (CH
0) with the help of DMM / oscilloscope is + 3 Volts.
Adjust the DC 2 amplitude control so that the voltage at TP12 (CH 1) is 2 V.
4.
The LED outputs of A/D Converter & shift register are a combination of the
two input voltages. Also since the trainer is working in fast mode, it is
impossible to detect the code.
5.
As stated earlier, the two channels are sampled at different time.
Approximately, after 10 seconds, when the system has settled down to slow
mode, observe the LEDs of A/D converter Block.
Notice that a particular combination of LEDs is lit in the A/D converter Block
for approximately 7 seconds.
These LEDs represent the latched output from the A/D Converter for every
sample of CH 0 & CH 1 Channels. Note the output of the A/D Converter,
Note : You may find the A/D Converter's output may not be identical every time you
switch the circuit from fast to slow mode for the same DC Control setting. This is due
to the slight change in voltage at Sample / Hold circuit at the time of switching.
However the change in code will only be 1 Bit.

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Figure 9
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ST2153 & ST2154

6.

7.

The parallel data from the A/D Converter is then loaded in the shift register
which converts in serial output. Connect the oscilloscope at following points :
a)
Oscilloscope channel 1 to TX. clock output (TP3)
b)
Oscilloscope channel 2 to S/L test point (TP9)
c)
External trigger to TX. to output (TP4)
You may have to adjust the oscilloscope trigger levels to obtain a stable display.
Observe the interdependence of S/L, TX clock output and the shift register
outputs as shown by their respective LEDs. Record the waveforms. The timing
diagram for the process is shown in figure 10.

System Timing Diagram for ST2153


Figure 10

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Time Division Multiplexing


Time division multiplexing is a technique of transmitting more than one information
on the same channel. As can be noticed from the figure 11 below the samples consists
of short pulses followed by another pulse after a long time interval. This no-activity
time intervals can be used to include samples from the other channels as well. This
means that several information signals can be transmitted over a single channel by
sending samples from different information sources at different moments in time. This
technique is known as time division multiplexing or TDM. TDM is widely used in
digital communication systems to increase the efficiency of the transmitting medium.
TDM can be achieved by electronically switching the samples such that they inter
leave sequentially at a correct instant in time without mutual interference. The basic 4
channel TDM is shown in figure 12
The switches S1 & S2 are rotating in the shown direction in a synchronized manner,
where S1 is sampling channel to the transmission media. The timing of the two
switches is very important to ensure that the samples of one channel are received only
by the corresponding channel at the receiver. This synchronization between S1 & S2
must be established by some means for reliable communication. One such method is
to send synchronization code (information) along itself to the transmitter all the time.
In practice, the switches S1 & S2 are simulated electronically.

Pulse Amplitude Modulated wave with large time Intervals between samples
Figure 11
On ST2153, the sequence of operation is synchronized to the transmitter clock TX.
Clock (TP3). The time occupied by each clock pulse is called a Bit. The sequence of
operation is repeated after every 15 bits. The complete cycle of 15 bits is called timing
frame. The start of the timing frame is denoted by the TX.TO signal (TP4) which goes
high during the bit time 0. The various bits reserved for the data appearing in the
middle of each transmitter clock cycle is shown in figure the figure 12 shows the
complete timing frame
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Principle of 4-Channel TDM System


Figure 12
Bit 0 : This bit is reserved for the synchronization of information generated by the
Pseudo random sync code generator block More about its operation in the later
section. When the Pseudo Random Sync Code is switched 'Off' a '0' is transmitted.
Bit 1 to 7 : These carry a 7 bit data word corresponding to the last sample taken from
the analog channel CH 0. Remember that the trainer transmits the lowest significant
bit (LSB) first. This time interval during which the coded information regarding the
analog information is transmitted is called the timeslot. Since the present timeslot
corresponds to channel 0 it is known as timeslot 0.
Bit 8 to 14 : This timeslot termed timeslot 1 contains the 7 bit word corresponding to
the last sample taken of analog channel1. As with channel 0 the least significant bit is
transmitted first. The receiver requires two signals for its correct operation & reliable
communication, namely.
a. Receiver clock operating at the same frequency as that of the ST2153 clock.
b. Synchronization signal, which allows the receiver to synchronizes its
clock/operation with the transmitters clock operation. All these requirements can
be achieved by transmitting two essential information signals :
I.
II.

A Transmit clock signal.


A Frame synchronization signal.

The simplest method is to transmit the synchronization information & the clock over a
separate transmission link. This results in a simplest receiver. It is used in data
communication LAN (Local Area Network) & in telemetry systems. However it is a
waste of media & is not economical for long distance communications.

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The ST2153 provides these two signals at TX. Clock output (TP3) & TX.TO output
(TP4). In this mode the Pseudo random sync code generator & detector (on ST2154)
are switched 'Off'.
The second technique is to transmit the synchronization code along with transmitted
data to be sufficiently different from the information samples.
The ST2153 involves the use of a pseudo-random sync code generator. These codes
are bit streams of '0's & '1's whose occurrence is detected by some rules. The Pseudo Random Sync Code gets its name from the fact that the occurrence of '0's & '1 's in the
stream is random for a portion of sequence i.e. there is equal probability of occurrence
of '0' and '1 '. This portion of sequence is 15 bit long on ST2153.
On the receiver the pseudo-random sync code detector recognizes the Pseudo random
code & use it to identify, which incoming data bit is associated with which transmitter
timeslot The advantage of this technique is that if the synchronization is temporarily
lost, due to noise corruption, it can be re-established as the signal clears. Hence there
is minimal loss of transmitted information. Also this technique also reduces the
separate link required for the synchronization signal of transmission.
Mode 1 : Mode 1 is TDM system of three transmission links between transmitter &
receiver. They are information, TX clock & TX.TO (synchronization) signal links.
The Pseudo random sync code generator & Detector are switched 'Off' in this case.
Mode 2 : Mode 2 is TDM system of two transmission links between transmitter &
receiver. These are information & TX clock signal links. The synchronization is
established by sync codes transmitted along with the data stream. No need to say that
the pseudo random sync generator & detector are switched On.
Mode 3 : Mode 3 is TDM system of one link between transmitter & receiver, namely
the link carrying information. Synchronization is again established by the sync codes.
The clock signal is regenerated by the phase locked loop (PLL) circuit at the receiver
from the transition of the information data bits.

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Experiment 4
Objective :
Study of Time Division Multiplexing
Procedure :
1.

Set up the following initial conditions on ST2153:


a)

Mode Switch in fast position

b)

DC 1 & DC2 Controls in function generator block fully clockwise.

c)

~ 1 KHz and ~2 KHz control levels set to give 10Vpp.

d)

Pseudo - random sync code generator on/'Off' switch in 'Off' Position.

e)

Error check code generator switch A & B in A=0 & B=0 position ('Off'
Mode)

f)

All switched faults 'Off'.

2.

First, connect only the 1 KHz output to CH 0

3.

Turn ON the power. Check that the PAM output of 1 KHz sine wave is
available at TP15 of the ST2153.

4.

Connect channel 1 of the oscilloscope to TP10 & channel 2 of the oscilloscope


to TP15. Observe the timing & phase relation between the sampling signal
TP10 & the sampled waveform at TP15.

5.

Turn 'Off' the power supply. Now connect also the 2 KHz supply to CH 1.

6.

Connect channel 1 of the oscilloscope to TP12 & channel 2 of the oscilloscope


to TP15.

7.

Observe & explain the timing relation between the signals at TP10, 5, 6, 12&15.

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Experiment 5
Objective :
Study of Pseudo Random Sync Code Generator
Procedure :
1.
Ensure the following initial conditions on ST2153 :
a)
Mode Switch in fast position.
b)
DC l & DC 2 Controls in function generator block, fully clockwise.
c)
~ 1 KHz & ~2 KHz signal control set at 10Vpp.
d)
Pseudo random sync code generator switched 'Off'.
e)
All switched faults 'Off'.
f)
Error check code selector switches, A & B in A=0 & B=0 position (Off
Mode).
2.
Ensure the following initial conditions on ST2154
3.
Mode switch in fast position.
a)
Pseudo random sync code detector switched Off.

4.

5.

6.

7.
8.

9.

b)
Error check code selector Switches A=0 & B=0 Position. (Off Mode)
c)
All four switched faults 'Off'.
d)
Pulse generator delay adjust control fully clockwise.
Make following connection on board of ST2153 :
1 KHz
To
CH 0 Input
2 KHz
To
CH 1 Input
Make the following connections between ST2153 & ST2154.
ST2153
ST2154
TX. Clock output TP3
RX clock input TP46
TX. To output TP4
RX sync input TP47
PCM output TP44
PCM input TP1
Display channel CH 0 Input (TP10) on oscilloscope channel 1 & use it to trigger
the oscilloscope. Display the ST2153 PCM output (TP44) on channel 2 of the
oscilloscope.
Vary the amplitude of the 1 KHz & 2 KHz sine wave signal & note that the
transmitted data changes.
Also observe the two input signals TP10 & TP12 of ST2153 with the received
sine wave samples TP32 & 35 of ST2154 and at the respective low pass filter
outputs CH 0 & CH 1 (TP33 & 36) of ST2154.
Vary the amplitude of ~1 KHz & ~2 KHz signals at the ST2153. Observe how
the output at receiver changes. Set a value of 4Vpp for channel 0. Note what is
the output voltage of the received signal.

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10.

11.

12.
13.
14.
15.
16.

17.

18.
19.

20.

21.

Turn Off the power. Rearrange the connections between ST2153 & ST2154 as
follows.
ST2153
ST2154
TX. clock output
RX clock input
PCM output
PCM input
Connect
Channel 1 of the oscilloscope to TP12 on ST2153.
Channel 2 of the oscilloscope to TP36 on ST2154.
Turn On the power. Notice the waveforms & confirm that they are different.
Vary the setting of ~2 KHz signal & observe the waveform at TP36. Explain
the reason behind the mismatch.
Turn 'Off' the power. Connect TX.TO output from ST2153 to RX sync input on
ST2154.
Turn On the power. Now notice the two waveforms again. Do you notice any
change? Why it has happened?
Now you must have observed the importance of synchronization. But now the
synchronization has been established because of the separate link between
ST2153 & ST2154.
Turn 'Off' the power Remove the link between RX.SYNC & TX.TO. Turn On
the trainer. Observe the two mismatched waveforms. Now turn On the pseudo
random sync code generator on ST2153. Do you notice any change in the
observed waveform at TP36 on ST2154.
Turn the pseudo random sync code detector on ST2154 ON. Notice the changes
observed waveform at TP36 of ST2154.
To be able to perceive the pattern of the sync code generated, connect the
oscilloscope probes to TP4 (TX.TO output & TP42) (Pseudo random sync code
generator output).
Notice the sync coded output for a high level occurrence at the TX to output. If
necessary switch the two trainers to slow mode.
Notice the sync Bit counter LED, in pseudo random sync code detector Block of
ST2154 is On in FAST Mode. This is an indication that the receiver has
identified the transmitted bit time 0 & is using it for all its timing operations.
This also confirms that the two are in 'Frame Synchronization'.
Observe the TX.TO (TP4) output signal on ST2153 & RX.TO (TP48) output
signal on ST2154. They should be identical when frame synchronization has
been achieved.
Switch 'Off' the pseudo random sync code generator. Notice that the sync bit
counter LED goes 'Off' indicating that the synchronization has been lost. Notice
at the same time that the sync error counter led goes On. Note the LED
indication may be faint. There fore observe carefully. This goes to show that
synchronization has been lost.

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Experiment 6
Objective :
Study of Three Modes of Transmission
Procedure :
1.

2.

3.

Set up following initial conditions on the ST2153:


a)

Mode Switch in fast Position.

b)

DC l & DC 2 Controls in function generator block fully clockwise.

c)

Pseudo random sync code generator switched 'Off'.

d)

Error check code selector switches A & B in A=0 & B=0 Position.

e)

All switched faults 'Off'.

Set up following initial conditions on ST2154 :


a)

Mode Switch in fast Position.

b)

Pseudo random sync code detector switched 'Off'.

c)

Error check code selector switches A & B in A=0 & B=0 position.

d)

All switched faults 'Off'.

e)

Pulse generator delay adjusts control in fully clockwise position.

Make connections as shown in figure 13.


a. On ST2153 :
I. ~ KHz Signal to CH 0 Input.
II. ~2 KHz Signal to CH 1 Input.
b. Between ST2153 & Receiver trainer
ST2153

ST2154

TX. Clock output

RX. Clock input

TX.TO output

RX sync input

PCM output

PCM data input

4.

Turn On the power. Observe that the 1 KHz sine wave input appears at TP10
(CH 0 Input) & 2 KHz sine wave input appears at TP12 (CH 1 Input).

5.

Connect
Channel 1 of oscilloscope to CH 0 Input (TP10)
Channel 2 of oscilloscope to PCM output (TP44)
Trigger the oscilloscope with CH 0 input. Observe the two waveforms. Vary the
ST2153's ~1 KHZ and ~2 KHz controls (which vary the amplitude of the two
sine waves) and note how the transmitter data changes.

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ST2153 & ST2154

6.

Set the amplitude of each sine wave to 8Vpp.


Display CH 0 (TP33) & CH 1 (TP36) of ST2154 on two channels of the
oscilloscope. Notice that the two outputs are identical to that transmitter by the
transmitter. Observe the receiver channel output with the corresponding
transmitter channel input on a dual trace oscilloscope. The output may get
flattened at peaks if the input sinusoidal signal voltage exceeds 10Vpp. This is
because the input exceeds the dynamic range of the A/D Converter. Vary the
amplitude of the input signal observe that the same changes are reflected at the
receiver.

7.

Turn 'Off' the trainer. Make following connection on ST2153 :


a. DC.1 to CH 0
b. CH 0 to CH 1

8.

Turn On the power. Vary the DC.1 control. Observe on the oscilloscope at
TP10. The amplitude should vary between -5 to + 5V. Variation of the input
voltage from -5V to +5V will cause the output of A/D Converter to vary from
00 Hex to 7F Hex. The A/D converter 7 Bit word output can be monitored on
LEDs provided in the A/D converter block.
Observe that the D/A Converter LED contain the same data for a particular set
of input amplitude. Notice the output waveform at CH 0 (TP33) or CH 1 (TP36)
of ST2154.

9.

The sequence of operation on ST2153 is fully synchronized to the TX. Clock


signal. This clock signal can be monitored at TP3. Each clock cycle is known as
timeslot. The operations of the trainer repeat after 15 timeslots. These 15
timeslots are collectively called 'Timing Frame'. The start of the timing frame or
Bit 0 is indicated by high level at TX.TO output (TP4). The data appears at the
output logic block at the start of each timeslot. The output logic block adds a
half timeslot delay to it. Thus the output (TP44) of output logic block contains
transitions halfway through each timeslot. The information appearing at the
middle of the timeslots is as follows.
BIT 0 : This carries the synchronization information (sync. code). The Pseudo
random sync code generator outputs a single bit in this timeslot. Since the
length of the code is 15 bits, the Sync code repeats after 15 timing frames. At
this instance the pseudo random sync code generator is 'Off', a '0' is transmitted
in this timeslot.
BIT 1 to 7 : These bits carry the 7 Bit data word of the last sample taken from
the channel o. Notice that the least significant bit (LSB) is transmitted first.
BIT 8 to 14 : These bits carry the 7 bit data word of the last sample taken from
channel 1. In this case also the least significant bit is transmitted first.
Observe the PCM output (TP44) with respect to the input signal to output logic
block (TP43) & with TX. Clock signal (TP3).

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Figure 13
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ST2153 & ST2154

10.

As it has been discussed earlier, for correct operation the receiver needs to be
clocked" at the same rate as the transmitter & it should be able to decide which
timeslot is for which information transmit TX clock & TX.TO signals on
separate links. TX clock signals clocks the receiver at the same rate where as
the TX. TO signal helps the receiver to identify the timeslot 0.

11.

The three wire connections can be reduced to two wires by developing the
ST2153's ability to transmit the synchronization information along the data.
Similarly, the receiver must be able to detect & distinguish these sync bits from
the normal information bits.
This ability is imparted by the Pseudo random sync code generator & detector
present on ST2153 & receiver trainer respectively. The pseudo random sync
code is a sequence of 15 bits generated by the pseudo random sync code
generator.
0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 .............................................................. Repeating.
One bit of this sequence is transmitted in every frame at timeslot 0. The receiver
detects it & uses it to decide which timeslot is for which frame.

12.

The above mode is termed as 'connecting Mode 2'. The ST2153 / Receiver can
be configured in this mode as shown in figure 14.
a. Switch the boards to FAST mode.
b. Remove the link connecting TX.TO (TP 4) & RX sync (TP 47).
c. Switch On the pseudo random sync code generator on ST2153.
d. Switch On the pseudo random sync code detector on ST2154.
e. Connect DC 1 to CH 0 & CH 0 to CH 1

13.

14.

Vary DC 1 and note that the LEDs on the A/D converter block on ST2153 &
D.A. converter of ST2154 always carries the same code.
Also observe that the sync bit counter led in the pseudo random sync code
detector block is On. This signifies that the receiver knows the transmitted
timeslot & can identify them. We say that the receiver is 'Frame Synchronized'
to the transmitter. Once the transmitter & receiver is frame synchronized, the
TX.TO & RX.TO signals are identical. You can observe the two waveform at
TP4 of ST2153 & at TP48 of ST2154 respectively.
Switch 'Off' the pseudo random sync code generator. Notice that the A/D
converter block output observed on LEDs is not similar to the D/ A Converter
Block input. We say that the receiver has lost the frame synchronization. The
Receiver indicates this by turning 'Off' the sync bit counter led in pseudo
random sync code detector block.

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Figure 14
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15.

If you desire to examine the timing of data flow & control signal in detail,
switch the ST2153 & receiver into slow mode.

16.

The number of connecting links can be reduced further to one by configuring


the ST2153 & receiver in connecting Mode 3. The only connecting link
between transmitter & receiver is the data/information link. The receiver
establishes the synchronization from pseudo random sync code transmitted
along with the P.C.M. data. In this case it has to regenerate the clock signal as
well. The receiver does this by on board phase locked loop circuit which
regenerates the clock from the transitions of the data bit whose timing with
respect to the clock signal is fixed.
Configure the ST2153 & receiver as shown in figure 15 and ensure the
following statements :
a. Both trainers are switched in FAST Mode.
b. Link between TX clock (TP3) & RX clock (TP46) has been removed.
c. PCM data input (TP1) on ST2154 is connected to the input (TP3) of phase
locked loop circuit on the same trainer.
d. The phase locked loop output (TP8) is connected to the RX clock input
(TP46) on the ST2154.

17.

18.

19.

20.

Before operating in connecting Mode 3 it may be necessary to trim the voltage


controlled oscillator (VCO) frequency, so that the regenerated clock remains in
synchronization with the incoming data even when few transitions occur. (This
happens when there is a long stream of '0's to '1's in the. NRZ (L) waveform).
Follow the procedures given below to trim the VCO frequency :
a. Turn the DC1 control in the function generator block on ST2153 fully
clockwise.
b. Slowly, turn the VCO frequency adjust control on ST2154 until the sync bit
counter led in the pseudo random sync code detector Block turns On.
c. Repeat the above steps till position of the control is found such that the sync
bit counter led remains On for both fully clock wise & anticlockwise
positions of the DC1 Control.
At the ST2153, remove the CH 0 & CH 1 inputs & connect.
a. ~ 1 KHz Signal to CH 0 input.
b. ~ 2 KHz Signal to CH 1 input.
Note : Turn 'Off' the power when new connections are made or disconnected.
Adjust the outputs of the two generators to 8Vpp by the amplitude controls
provided in the Function generator block. You can observe the two signals at
TP10 & 12).
Observe the ST2154 analog outputs (TP33 & 36). Verify that the two outputs
are identical to that applied at the transmitter's inputs.

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ST2153 & ST2154

21.

The trainers have on board error check generator & detector (on ST2153 &
ST2154 respectively). This provides an opportunity to detect & if possible to
correct the erroneous trainer data. The Error check code generator replaces
some least significant bits of the 7 Bit word with some error check bits. The
following error check options are available on board :
a. 'Off' : The error check generator is 'Off' when this mode is selected by
switching the A & B switches in the error check code generator block in
ST2153 in A = 0 & B = 0 position.
No error check code is inserted in the 7 Bit word. The word format is
D6 D5
D3
D2
D1
D0
Where D6-D0 are the A/D Converters latched outputs.
b. Even Parity : This option is selected by placing A & B switches in the error
check code generator block in ST2153. In A = 0 & B=1 position. The least
significant bit of the 7 bit word is replaced by a single parity bit.
The word format is :
D6 D5
D4
D3
D2
D1
C0
Where C0 is the parity check bit which is chosen such that the total no of '1's
in the 7 bit word are even. If the error check code detector in ST2154 is also
configured in this mode, it can detect the error in the transmitted data, but it
cannot tell which bit is in error. It indicates 'the error by switching On of
the Parity Error LED.
c. Odd Parity : This option is selected by placing the A & B switches in the
error check generator block in A = l & B = 0 position. The least significant
bit of the 7 - Bit word is replaced by a single parity bit.
The word format is.
D6 D5
D4
D3
D2
D1
C0
Where C0 is the parity check bit such that the total no of '1's in the 7 bit word
are odd.
If the error check code detector in ST2154 is also included in this mode, it
can detect the error in the transmitted data, but cannot tell which bit is in
error. It indicates the error by switching On of the parity error LED.
d. Hamming Code : This option is selected when the A & B switches in the
Error check code generator on ST2153 are placed in A=1 & B=1 position.
In this case the three check bits replace the three least significant bits of the
7 bit word. The word format is :
D6 D5
D4
D3
C2
C1
C0
Where C2, C1 & C0 are the Hamming check bits. If the Error Check Code
Detector in ST2154 is switched into same .mode, it can detect the error &
even connect the erroneous transmitted data bit (only single). It indicates the
erroneous bit by lighting the corresponding LED in hamming code error
block. Illustration of various check codes are given in steps 22nd to 29th :

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ST2153 & ST2154

22.

23.

24.

25.

26.

27.
28.

29.

Connect the ST2154's CH 0 (TP33) & CH 1 output (TP36) to the two channels
of the oscilloscope. Now introduce the switched fault '2' in the trainer system by
switching On the pole 2 of switched faults Block. This fault forces the D6 bit
(MSB) of the transmitted 7 bit word to be always '1' even when there must have
been a '0'. Notice the distortion in the output in the output sine waves at the
ST2154's CH 0 (TP33) & CH 1 (TP36) outputs.
Switch 'Off' the fault. Introduce even parity error check code option on both the
trainers by switching the A & B switches in the corresponding block to A=0 &
B=1 position.
Observe the two output waveforms at ST2154's CH 0 (TP33) & CH 1 (TP36)
outputs are distortion less & also observe the LEDs in the error check code
detector block are 'Off'.
Switch On fault '2' again.
Observe that the parity error indicator LED in error check code detector glows
i.e. the receiver has detected the error in transmitted data but is not in a position
to locate which bit is in error. Therefore the output at CH 0 & CH 1 on ST2154
still remains distorted.
You can carry on the same experiment by selecting the odd parity option. You
will get the same result as the earlier ones. Note switch 'Off' the fault prior to
selecting the Error check code option.
Switch ''Off'' the fault. Select the hamming code option by placing the A & B
switches in the corresponding block to A = 1 & B = 1 position.
Switch On fault '2'
Observe that the D6 LED marked in error check code detector's hamming code
error bit glows. Since its 3 bit hamming code, it can detect as well as correct one
bit error in a sample. It reveals the erroneous bit in the data format by lighting
the corresponding LED (D6 in the present case). Notice, now that the outputs at
CH 0 & CH 1 on ST2154 are now distortion less. This is because the erroneous
bit has even been corrected by the receiver.
You can induce any switched fault /faults in the ST2153 & ST2154 trainer to
investigate the effect of particular faults on the whole system. This also allows
you the opportunity to practice & test your skills in fault detection trouble shooting. The list of various faults that can be induced in the system is given in
this manual.

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ST2153 & ST2154

Figure 15
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ST2153 & ST2154

Experiment 7
Objective :
Computer Communication using RS232 interface via ST2153 & ST2154
There are two channels provided on ST2153 & ST2154. It utilizes these two channels
to communicate between two computers, thus forming a full duplex link. It will need
the following :
System :
Microsoft Windows 95, 98, or above
Software :
Supplied with the trainer in CD
Procedure :
1.

Keep PCs on either side of the ST2153 & ST2154.

2.

Connect the RS232 cable to the serial port of the computer and the other end to
ST2153 & ST2154 as shown in figure 16.

3.

Make the interconnections between ST2153 & ST2154 as shown in the figure
16. (Before connecting perform the experiment no.6 in mode 3).

4.

Install the Software on both the PCs.

5.

After establishing a connection, select the com port in the "COM Port" window,
and select Baud rate (same on both PCs).

6.

Follow this procedure for both the computers.

7.

Switch On the trainers.

8.

Now type a message in the message window of PC1 and click send, you will see
the message in receiver window of PC2 and in transmit window of PC1.

9.

If you send a message from PC2 you will receive the message in the receiver
window of PC1 and in transmitter window of PC2.

10.

If you disconnect any of the transmitting or receiving wire, you will see that the
data transmission has failed.

11.

You can reduce the baud rate of both PCs and you will observe that the transmit
rate is lower.

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ST2153 & ST2154

Figure 16
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ST2153 & ST2154

Experiment 8
Objective :
Multi point to multipoint communication using RS232 interface via ST2153 &
ST2154
There are two channels provided on ST2153 & ST2154. It utilizes these two links to
communicate from two PCs on one end to two PCs on other end. The two PCs
connected to ST2153 will act as transmitter, and those connected to ST2154 will act
as receiver. This will be a one way communication. It will need the following:
System :
Microsoft Windows 95, 98, or above
Software :
Supplied with the trainer in CD.
Procedure :
1.

Keep the PCs on either sides of the ST2153 & ST2154.

2.

Connect the RS232 cable to the serial port of the computer and the other end to
ST2153 & ST2154 as shown in figure 17.

3.

Make the interconnections between ST2153 & ST2154 as shown in the figure
17 (Before connecting perform the experiment no.6 in mode 3).

4.

Install the software provided with the trainer in all the four PCs.

5.

Run the software in all the PCs and select the respective COM ports and the
same baud rate in all the PCs.

6.

Switch On the trainers.

7.

Now the data transmitted by PC1 and PC2 will be multiplexed, Pulse code
modulated and transmitted via single wire and then, demodulateddemultiplexed and received by PC 3 and PC4 respectively.

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ST2153 & ST2154

Figure 17

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ST2153 & ST2154

Experiment 9
Objective :
Point to multipoint communication using RS232 interface via ST2153 & ST2154
There are two channels provided on ST2153 & ST2154. It utilizes these two links to
communicate from one PC to the two other PC's on the other end. The PC on the
transmitter side will act as master and the PCs on receiver side will act as slaves. This
will also be a one way communication.
System :
Microsoft Windows 95, 98, or above
Software :
Supplied with the trainer in CD
Procedure :
1.

Keep one PC to the left of ST2153 (master) & two PCs to ST2154 (slaves) as
shown in figure 18.

2.

Connect the RS232 cable to the serial port of the computer and the other end to
ST2153 & ST2154 as shown in the figure 18.

3.

Make the interconnections between ST2153 & ST2154 as shown.

4.

Install the software provided with the trainer in all the three PCs. Run the
software and select the respective COM ports and same BAUD rate in all the
PCs.

5.

Switch On the trainers.

6.

Now the data or instructions transmitted by the master will be received by the
two slaves.

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ST2153 & ST2154

Figure 18

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ST2153 & ST2154

Switched Faults
1.

Transmitter Switched Faults :

Following faults can be induced in the ST2153 to study their effects on the system &
to practice fault-diagnosis techniques.
Switched Fault 1 :
Switching ON of this fault causes the A/D Converter's D6 Output to be always '0',
irrespective of the applied analog input. The fault occurs before error check code
generator & hence cannot be detected by the receivers error detection correction
logic. Hence the output of the receiver is not always a true representation of the
applied analog input at the transmitter.
Switched Fault 2 :
The switching On of this fault cause D6 bit of the P.C.M. output of the transmitter to
be always '1' irrespective of the connect D6 bit level. This fault is induced after the
error check code generator block & hence can be detected & in case of hamming code
selected, can be corrected also if the same mode is selected on error detection &
correction logic on receiver trainer also. This fault can be used to study the utility of
the error check codes in case of bit corruption in the P.C.M. data along the
transmission path.
Switched Fault 3 :
This fault causes the error check code generator to treat the A/D converter's D5 output
to be always high irrespective of the actual D5 bit in P.C.M. data transmitted. This
fault has no effect when none of the error check code option is selected the receiver
may wrongly decide that the P.C.M. data has a fault.
In case of hamming code, the receiver may try to correct the wrongly diagnosed 'error'
thus distorting the output in this process.
Switched Fault 4 :
This fault affects the pseudo random sync code generator. It causes the generator to
generator a sequence which is not Pseudo Random in Nature. Hence if the receiver is
relying on pseudo random sync code for synchronization as in connecting Modes 2 &
3, the receiver loses frame synchronization. This distorts the receiver's output.
2.

Receiver Switched Faults

The Following faults can be induced in the ST2154 receiver trainer to study their
effects on the system & to practice fault diagnosis techniques
Switched Fault 1 :
This fault breaks the loop between phase locked loop output & loop filter's input on
ST2154 receiver trainer. Thus induction of this fault cause the malfunctioning of
phase locked loop circuit. Hence the receiver doesn't clock into synchronization in
connecting Mode 3. Remember PLL circuit is used to extract clock information in
connecting Mode 3.
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Switched Fault 2 :
This fault affects the functioning of ST2154's pseudo random sync code detector.
When this fault is induced, the receiver cannot detect the transmitted pseudo random
sync code. Hence in connecting Mode 2 & 3 in which the ST2154 depends on sync
code detection for frame synchronization this fault cause the receiver to continuously
try to resynchronize but to do so every time.
Switched Fault 3 :
This fault affects the ST2154's error detection/correction logic when the hamming
option is selected. It causes an error in C1 to be indicated when the received data and
check bits are correct. If the received data actually contains an incorrect bit, the
receiver may decide that the wrong bit is in error, and if that bit is a data bit, try to
correct it. The effect of this fault is detailed in the table below.
Bit Received
In Error

Indicated
Error

Bit
Corrected

None

C1

None

C0

D3

D3

C1

C1

None

C2

D5

D5

D3

D3

D3

D4

D6

D6

D5

D5

D5

D6

D6

D6

Switched Fault 4 :
This fault open circuits the ST2154's channel 1 sample & hold amplifier. This causes
the receiver's channel 1 output CH 1 (TP36) to drift down to 10V supply.

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ST2153 & ST2154

Setting Up the Receiver's Clock Regeneration Circuit


The receiver's clock regeneration circuit contains a preset labeled VCO frequency
adjusts. The preset adjusts the free-running frequency of the phase-locked loop's
voltage controlled oscillator (VCO). Before connection mode 3 is used, it may be
necessary to trim the frequency of the VCO to ensure that the generated clock signal
remains synchronized to the incoming data, even when the transitions in the data are
only occasional.
The procedure for making this adjustment in ST2154 check regeneration circuit is as
follows:
1.

Set up the system in connection mode 3. See figure 1.

2.

Ensure in ST2154 circuits that :

a.

All switched faults are 'Off'.

b.

The error check code selector switched are in the '00' ('Off') position

c.

FAST Mode is selected.

3.

Switch On the ST2153's pseudo random sync code generator block and the
ST2154's pseudo random sync code detector block.

4.

Ensure 'that the ST2154's pulse generator delay control is in the fully clockwise
position.

5.

Make the following links at the ST2153 :

a.

DC 1 to CH 0 input.

b.

CH 0 input to CH 1 input

6.

Switch on the power to the boards.

7.

Turn the DC 1 preset, on ST2153 fully clock wise.

8.

Turn the VCO frequency adjust preset, on ST2154 until a position it is found
where the sync bit counter LED, in the sync code detector block of ST2154 is
On.

9.

Turn the DC 1 preset fully counter clockwise and check that the sync bit counter
LED is still On If the LED switches to 'Off', retrim the VCO frequency adjust
preset until the LED stays on for both extreme positions of the DC 1 preset.

After following this procedure, the receiver clock regeneration circuit should be able
to synchronize on any transmitted data stream, providing that there are at least
occasional rising transitions at PCM data output.

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Warranty
1.

We guarantee the product against all manufacturing defects for 24 months from
the date of sale by us or through our dealers. Consumables like dry cell etc. are
not covered under warranty.

2.

The guarantee will become void, if


a)

The product is not operated as per the instruction given in the operating
manual.

b)

The agreed payment terms and other conditions of sale are not followed.

c)

The customer resells the instrument to another party.

d)

Any attempt is made to service and modify the instrument.

3.

The non-working of the product is to be communicated to us immediately giving


full details of the complaints and defects noticed specifically mentioning the
type, serial number of the product and date of purchase etc.

4.

The repair work will be carried out, provided the product is dispatched securely
packed and insured. The transportation charges shall be borne by the customer.

List of Accessories
1.

Patch Cord 16" ...........................................................................................4 Nos

2.

Patch Cord 20" ...........................................................................................1 No.

3.

Mains Cord.................................................................................................1 No.

4.

RS232 Cable .............................................................................................2 Nos

5.

e- Manual ..................................................................................................1 No.


Updated 05-08-2008

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