El t

Electronics
i III
- Power Dissipation in CMOS digital circuits
- Optimization of Chain of Inverters

CMOS Power Dissipation

Trade offs
Power Timing Area
CMOS power includes static and dynamic components

P I DD VDD
Ptotal Pstatic Pdynamic

CMOS Dynamic Power Dissipation

Dynamic Switching Currents
1. Dynamic Capacitive charging current
Pavg

v(t ) i(t )dt

dVout

Vout C L
dt
dt
0
T /2

2
2

Vout
C L
Vout
0
DD
V

V DD Vout
|0
|VDD
Pavg

T
2

VDD
2

1
+
2
2
Pavg C LV DD
C LV DD
f clk V DD I D , avg
T
+
PU
C L Vswing
d
dV
PD
Vout
I D , avg C L

C LV DD f clk
dt
t

Pavg

1

T

T /2

VDD

dV out

Vout C L
dt
dt

Iswitch design factors

Reduce CL Vswing VDD fclk

Pull up:
t= 0 T/2
Vout =0 VDD

Vout
+
-

Pull down:
t = T/2 T
Vout = VDD 0

CMOS Dynamic Power Dissipation

Switching Activity Factor
Activity factor
HOWEVER Most gates do not switch (toggle) at each clock edge
2
Pdynamic

C
V
d
i
L DD f 0
0 1

Pdynamic = 01 CL VDD2 fclk

Where 0 1 is the activity factor

CMOS Dynamic Power Dissipation

Switching Activity Factor
Activity factor
= probability that an output transition 0 1 takes place

= p0p1

p0 = probability output = 0
p1 = probability
b bilit output
t t switches
it h tto 1

Determined from to truth table of specific gate

Assuming equal probability for each combination of input
Example: 2 input NOR/NANDgates
A

A+B

A.B

0
0
1
1

0
1
0
1

1
0
0
0

1
1
1
0

NOR2: p0=3/4, p1=1/4, = 3/16

NAND2: p0=1/4,
=1/4 p1=3/4,
=3/4 = 3/16

CMOS Dynamic Power Dissipation

Switching Activity Factor
Activity factor
Assuming equal probability for each input combination
Example: 2 input XOR gate:
p0=0.5,
0 5 p1=0.5
0 5 = 0.25
0 25

Example: 3 input NOR gate:

p0=7/8,
=7/8 p1=1/8 = 7/64

XOR

0
0
1
1

0
1
0
1

0
1
1
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

A+B+C
1
0
0
0
0
0
0
0

3 input NAND gate: p0 = 1/8, p1=7/8 = 7/64

CMOS Dynamic Power Dissipation

Short Circuit (Crowbar)
Short circuit current when at No load
PDN and PUN are both conducting
during HL and LH transitions

Qr I sc , avg t sc , rise
i
Q f I sc , avg t sc , fall
I sc Qt / T

t sc , rise t sc , fall
T

t sc t sc , rise t sc , fall

I sc , avg

Duration depends on input rise and fall

times
tsc = time for VDD-IVtpI > VI > Vtn

t sc
I sc , avg
T
t
Psc I sc .V DD sc I sc , avg .V DD t sc I sc , avg V DD f clk
T
dV
By _ definition I C
I t C V
dt
Assume t sc I sc , avg C scV DD

I sc

2
Psc C scV DD
f clk

Isc

Ar ISC,av
tsc.rise

Af
tsc.fall

where CSC is an equivalent short circuit capacitance

defined for analogy with dynamic power

Isc
t

CMOS Dynamic Power Dissipation

Short Circuit (Crowbar
(Crowbar, Contd..))
2
Psc C scV DD
f clk

C sc sc C L

Another
A h activity
i i ffactor

2
Psc sc C LV DD
f clk
2
2
2
Pdynamic 0
0 1C LV DD f clk sc C LV DD f clk C LV DD f clk

includes activity and short circuit effects

Minimum ISC : Rise and fall edges of input as sharp (minimum
tsc) and as equal as possible.
possible
BUT This requires large currents in previous stage
large transistors large CL large dynamic power
Trade off between dynamic power of previous stage and short
circuit power of next stage

CMOS Dynamic Power Dissipation

Glitches
Glitches
Extra output transitions
E
ii
d
due to
asynchronous arrival of multiple inputs
Leads to p
power consumption
p
Minimized by managing input arrival
time by adjusting
- path delays
- gate delays
- right selection of gate and
logic
g architecture
SPICE:

0.25 m adjust the inputs of a 2 Input

NOR gate until a glitch appears at the
output during a transient analysis. What
are the conditions for the glitch to occur .

CMOS Static Power Dissipation

Static Currents
2. Static Currents
Subthreshold Channel leakage current in "off" devices
Junction

Reverse bias current through pn junctions

y ((DC)) Current through

g normally
y on devices
Standby
(Pseudo-NMOS)

Pstatic I subthreshold I junction I standby VDD

Power - Delay Trade-offs

G l
Goal
Reduce power and delay Minimize Power-delay product (PDP)

PDP = Paverage x tp = Average

A erage po
power
er x a
average
erage dela
delay
Assume: Dominant source of dissipation Paverage = CVDD2f
Propagation delay = 1/2f
PDP = CVDD2f/2f = CVDD2/2
PDP = Energy per switching operation (per toggle)
Energy stored in C after a charging operation
EC ,01

i (t )v
0

out (t ) dt

2
VDD
dvoutt
CVDD
C
vout (t ) dt C vout (t ) dvout
PDP
2
dt
0

Design factors for PDP reduction

Capacitance, Voltage swing, Supply voltage
PDP obscures design optimization parameters

Power - Delay Trade offs

Energy Delay Product
Energy-Delay Product EDP
New metrics that show delay
EDP = average power x (average propagation delay)2.

dV
CV
t
dt
I
CV
CVDD
tp

I sat
K 2 VDD VT 2
I C

EDP

3
C 2VDD

2 K 2 VDD VT 2

EDP
0 VDD,opt 3VT
VDD
(or 3VT / 2 forshortchanneldevices)

Norm
malized v
values

EDP PDP t p
Energy
Energy.delay

Delay

VDD

Delay of CMOS Inverter Chain

VDD

Input (Gate) capacitance

Cin = CG((Wn+Wp) = CG((Wn + 2Wn) = 3 CGWn
Reff = Reqn(Ln/Wn)
1. Intrinsic inverter time constant Tinv
Tinv = Reff Cin= Reqn (Ln/Wn)CG(3 Wn)=3 ReqnCGLn

Vin
Cin

Vout
Cself

Cout

Independent of Wn hence of Sizing W FxWn

Tinv (Reff/F)x(CinxF) = ReffCin

Load capacitance
N lload:
No
d Capacitance
C
it
att Output
O t t=
inverter own drain node capacitances (Cself)
With load: Load capacitance = Cself + Cout where Cout = capacitance due to
a)Fan
)
out = input capacitance off load gates at output
b) wiring capacitance
CL = Cself + Cout

Hodges and Jackson, Chapter 6, Section 6.5.1, 6.5.2

CMOS Inverter Delay

2. Delay time constant Td
Td = Reff CL = Reff[Cout + Cself] = ReffCin [Cout/Cin + Cself/Cin]
= Tinv [Cout/Cin + Cself/Cin]
VDD

= Tinv [ f +in]
f = Cout/Cin = fan out ratio (electrical effort)
in = Cself/Cin = drain/gate capacitance ratio
in depends on the gate layout

Vin
Cin

Vout
Cself

Cout

Sizing Inverter for optimum delay

Required to drive a very large capacitance using inverter (s)
To reduce the delay the effective resistance should be very small
Solution:

1 Use one very big inverter with a very small resistance

1.
resistance. But will have:
- High input capacitance shifting the problem the previous stage

In

Cin high

Cself loading

- High drain capacitance hence high self loading capacitance Cself and

Out
CL

Chain of Inverters
2. Use a chain of inverters to minimize the delay from input to
output Design issue sizing of each inverter
In
C1

Out
1

j-1

j+1

CL

Total delay Td = Tinv [Ci+1/Ci + inv] = Tinv[3CGWi+1/(3CGWi) + inv]

ii=1
1

ii=1
1

Consider delay of two consecutive inverters

Dj = Tinv(Wj/(Wj-1 + inv) + Tinv(Wj+1/Wj + inv)
To obtain the minimum delay derive Dj wrt Wj and equate to zero
dDj/dWj = Tinv (1/Wj-1) Tinv (Wj+1/Wj2) = 0
Wj/Wj-1 = Wj+1/Wj

Wj = VWj+1Wj-1)

Optimimum Chain of Inverters

2. Use a chain of inverters to minimize the delay from input to
output Design issue sizing of each inverter

In
Cin

Out
1

f2

fN-2

fN-1

CL= fN Cin

Wj/Wj-1 = Cj/Cj-1 = Cout/Cin of inverter j = fj = f = constant for all inverters

Each inverter is doing the same electrical effort
CL/Cin = CL/CN x CN/CN-1 x CN-1/CN-2 X..X C2/Cin
= f N = F = Total electric effort of chain
At optimum sizing each gate delay = Tinv(Cj/Cj-1 + in)
Path
P hd
delay
l Td = NTinv(f + in) = NTinv(F1/N + in)

Optimum Chain of Inverters

Example: assume 3 inverters
I
In
C1

O t
Out
f

f2

CL = 8C1

f = 8 =2
Td = NTinv((f + in)
Need to determine N that minimizesTd

F = f N = CL/C1 N =

ln ((CL/C1)
ln f

[ f + in]
Td = NTinv [ (f + in] = Tinv ln(CL/C1) x
ln f

Optimum Chain of Inverters

To get minimum delay derive Td wrt to f
dTd/df = Tinv ln (CL/C1) x

l f 1 in/f
ln

fopt = exp (1 + in/fopt)

If in = 0 ((i.e. Cself = 0))
f=e
N = ln(CL/C1) = ln (CL/C1]
ln f
If in = 1
f = 3.6
N = 0.78 . ln (CL/C1]

(ln f

)2

=0
5
4.5
4

fopt 3.5

fopt = 3.6 4

3
25
2.5
0

0.5

1.5

inv

2.5

(f = 3.6)

( f = e)

Dela
ay

Optimum Chain of Inverters

f
Practicallyy in 1 Curve veryy flat for f 2
Most common used value used f = 4 (magic number)

Optimum Chain of Inverters

Td = N Tinv (in + F1/N ), F = CL/C1, Nopt= ln F/ln(3.6)
F
(in = 1)

N=1
N=2
Unbuffered Td/Tinv= 2(1+F0.5)
Td/Tinv= (1+F)

Opt. Chain
Td/Tinv= Nopt.(1+3.6)

10

11

8.3

8.3

100

101

22

16.5

1,000

1001

65

24.8

10,000

10,001

202

33.1

Very large capacitive loads F Impressive speed-up with

optimized chain of cascaded inverters

Optimum Chain of Inverters

Example of Inverter (Buffer) Staging (Assume in = 1)
1
C1 = 1
1

CL = 64 C1

CL = 64 C1
4

C1 = 1

tp

64

65

18

Optimum

16

C1 = 1

C1 = 1
1

CL = 64 C1

2.8

22.6

CL = 64 C1

15

2.8

15.3

Optimum Chain of Inverters: Energy vs Delay

driver
Cin

fCin

f2Cin

f3Cin

To be driven
CL = f4Cin

Overhead capacitances
During every switching cycle all inverters are switching
Energy drawn from supply = CjV2DD
Delay decreases but area and energy
increases with number of inverters
Trade-off (Compromise)
Give up some delay for less
energy / area
Emin

tp,min