Department of Electrical and Electronics Engineering

Reg. No

MANIPAL INSTITUTE OF TECHNOLOGY, MANIPAL

(A Constituent Institute of Manipal University, Manipal)
III SEMESTER B.TECH DEGREE MAKE UP EXAMINATION

ELE 209: ANALOG ELECTRONIC CIRCUITS

Time: 3 hours
Note

09 JANUARY 2015

Max. Marks: 50

Answer any FIVE full questions.

Missing data, if any, may be suitably assumed.

1A.
1B.
1C.

Assuming Silicon diode, plot the output waveform for the clamper circuit shown in Fig 1A
Plot the output voltage wavefome for the circuit shown in Fig 1B. Assume diodes to be ideal.
Write a note on Junction Diode Capacitances.

2A.

For a full wave rectifier with a capacitor filter, derive the expression for ripple factor. Draw the circuit diagram and
relevant waveforms.
Design a Zener voltage Regulator to maintain the output voltage to be at 5V, while the load current is expected to
vary over 40-150mA. Assume the input voltage is expected to vary between 10 and 20V and Izmin = 25mA.
Determine IB, dc and dc for a transistor with IC=2.5mA and IE=2.55mA.

2B.
2C.
3A.
3B.
3C
4A.
4B.
5A.
5B.

6A.
6B.
6C.

(03)
(03)
(04)

Determine IC and VCE for the voltage divider bias circuit with the following specifications. = 80, VBE= 0.7 V, VCC= 16 V,
RC = 3.9 k, R1=62 k, R2=9.1 k, Rc=3.9 k, RE=680 .
For the fixed bias circuit derive the expression for stability factor S and comment on the stability of this circuit.
MOSFET is a voltage controlled device. Justify this statement with relevant expressions.
Draw the h parameter model of a basic amplifier circuit and derive expressions for Current gain, Voltage gain, Input
and Output Impedances.
For the circuit shown in Fig 4B, develop approximate h parameter model and determine the overall voltage gain.
(Vo/Vs). Given RS=1K ,RB= 40K , Rc=3.3K , hie=1.1K, hfe=50.
Calculate ID and VD and comment on the region of operation for the circuit shown in Fig 5A,when VG=2V,
2
RD=1K,VT=1V, nCoxW/L=1mA/V
2
In the cascaded amplifier shown in Fig 5B, the MOSFETs have VTH = 0.7 V, nCox = 500 A/V , drain currents ID1 = 2
mA, ID2 = 1 mA., i) Draw the small signal model ii) Find the small signal gain from Vsig to VL iii) Determine Rin and
Rout of the amplifier.
Classify the power amplifiers based on their Q point.
For a series fed Class A Power Amplifier, derive an expression for conversion efficiency and hence determine
maximum efficiency.
Design an adjustable voltage regulator using LM317 to obtain an output voltage of 3 to 16V. Assume Maximum
output current to be 150mA,Vref=1.25V and Iadj=100A.

(04)
(03)
(03)
(04)
(03)
(03)
(06)
(04)
(03)

(07)
(03)
(03)
(04)

Fig 1B
Fig 1A

Vcc

VDD

RC

RB

RD

Vo

Rs
Vs

VG

Fig 4B

Fig 5A

Fig 5B

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