IEEE 2nd International Symposium on Next-Generation Electronics (ISNE) - February 25-26 , Kaohsiung , Taiwan

A 12-bit 4-kHz Incremental ADC with Loading-Free

Extended Counting Technique
I-Jen Chao*, Chia-Chun Huang*, Ying-Cheng Wu*, Bin-Da Liu*, Chun-Yueh Huang**, and Jai-Ming Lin*
* National Cheng Kung University, No.1, University Road, Tainan City 701, Taiwan
** National University of Tainan, 33, Sec. 2, Shu-Lin St., Tainan 700, Taiwan
Correspondence to: jjeenn812@gmail.com

AbstractIn this design, a low-power incremental ADC

employing the loading-free architecture for the extended
counting technique is proposed. The proposed topology uses a
multi-bit SAR ADC to complete the extended counting
conversion, but the integrator of the preceding incremental
ADC is not loaded by the DAC array of the SAR ADC, which
means the opamp power can be reduced. This work adopts an
incremental ADC to convert the first 5-bit MSB and a
synchronous SAR ADC to convert the last 7-bit LSB, and thus
totally 12-bit resolution can be obtained without calibration. The
proposed topology is capable of achieving high resolution, and
furthermore holds the power efficient advantage of SAR ADCs.
The proposed ADC is implemented in a 0.18-m 1P6M CMOS
process. Under 4-kHz input signal bandwidth and 23.07-W
power consumption, the peak signal-to-noise and distortion ratio
is 69.38 dB. The active core area including clock generator
occupies of 0.33 mm2.

I.

Fig. 1.

the resolution together with a higher static linearity. In [3], to

improve the issue of low conversion rate in a given resolution,
a second-order incremental ADC is utilized. The cyclic ADC
is replaced by a power efficient successive approximation
register (SAR) ADC, but obviously the DAC array of the
SAR ADC will result an enormous capacitive loading to the
integrator of incremental ADC. Therefore, 11-bit SAR ADC
with the bridge-capacitor-type DAC is adopted in [3], which
can decrease the capacitive loading. However, to consider the
required matching between the binary-scale capacitors and
the bridge capacitor, the minimum unit capacitor is limited.
This situation will lead that the opamp output loading cannot
be mitigated significantly, and hence increase opamp power
consumption.
In this paper, a similar two-step conversion is adopted. A
first-order loading-free incremental ADC is proposed to carry
out the first 5-bit conversion and a 7-bit SAR ADC, whose
DAC array acts the feedback capacitor of incremental ADC
to avoid the extra capacitive loading at the integrator output,
is to count the residual error, so that the design specifications
of the opamp can be relaxed. Moreover, being different to the
previous arts of the extended counting ADC, the proposed
ADC topology overlaps the second-step operation with the
preceding incremental ADC operation to save the whole
conversion time. That is to say, the conversion rate is only
proportional to the period of the first-step operation in this
work. Consequently, under a given conversion rate, the
sampling frequency can be decreased in the design.
This paper is organized as following. Section II reviews the
fundamentals of the extended counting technique. Section III
illustrates the proposed method in detail. Several design
circuit blocks and the simulated results will be discussed in
Section IV and Section V, respectively. Conclusions are
given in Section VI.

INTRODUCTION

Analog-to-digital converters (ADCs) for biomedical

application usually require analog blocks with low offset and
high dynamic range to transfer sensitive analog signals to
corresponding digital codes. Among the numerous types of
ADC, incremental ADCs are the relatively simple means of
performing these biomedical data. The first reason to use
incremental ADCs is that conventional oversampling deltasigma modulators (DSMs) cannot provide low offset without
complicated digital calibration filters. Another reason is that
incremental ADCs can achieve one-to-one mapping between
input analog samples and output digital codes.
Extended counting technique applied in an incremental
ADC has been shown to improve the accuracy and linearity
significantly [1]-[3]. One whole conversion is separated into
two steps. In [1] and [2], an incremental ADC, which
operates as a resettable first-order DSM and inherently
performs an extremely high resolution but a very low
conversion rate, was utilized for the first steps. During the
second step, residual errors remained on the feedback
capacitors are next passed onto the extended ADC where a
cyclic ADC is adopted as the extended ADC. By encoding
output codes from the two steps, this technique can enhance
This work was supported by the National Science Council, Republic of
China, under Grant Number NSC 100-2220-E-006-014 and NSC 101-2220E-006-014

978-1-978-1-4673-3037-4/13/$31.00 2013 IEEE

Block diagram of a resettable first-order incremental ADC with

extended counting.

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IEEE 2nd International Symposium on Next-Generation Electronics (ISNE) - February 25-26 , Kaohsiung , Taiwan
first integrator output V0 is zero, and the first compared
output code D0 is also zero. Assuming that the input signal is
constant during the counting conversion, we denote the
residual error at the end of the first step as Vcount, and the
relative equation after completing the counting conversion
can be derived as
Fig. 2.

Two operating phases of each clock cycle during counting conversion

step.

Vin =

II.

PRINCIPLE OF EXTENDED COUNTING

CS
(Vin Di1Vref ) .
CF

Vref +

Vcount C F
N CS

Vcount = 2 j B jVref + ext

(2)

(3)

j =1

where M is the number of sampling clock period during the

extended conversion. Combining (2) and (3) leads to
M

Vin =

i =1

Vref +

B jVref

j =1

CF ext CF .
+
CS N CS

(4)

The above equation obviously shows that Vin can be

reconstructed by encoding Di of the first step and Bj of the
second step. The error ext is multiplied by the capacitor ratio
of CF to CS where the ratio is a trade-off between the overall
error and the integrator output swing. More importantly, ext
will be divided by the number of N. This equation is the
essence of the extended counting method, so the resolution of
the entire ADC can be enhanced.
III.

THE PROPOSED LOADING-FREE EXTENDED

COUNTING ARCHITECTURE

A loading-free technique has been presented for a

pipelined ADC [4] to reduce opamp power consumption. The
basic concept is that the feedback capacitor of the MDAC
(multiplying DAC) in the present stage can act as the
sampling capacitor of MDAC in the next stage. The idea can
be also applied in the proposed ADC topology, because the
signal stored on the feedback capacitor of the resettable
integrator is equal to the sampled signal for the SAR ADC.
Therefore, the feedback capacitor can also act the DAC
capacitor array of the SAR ADC during the extended
conversion to mitigate the opamp capacitive load during
counting conversion, thereby decreasing the opamp power
requirement. Figure 3 illustrates the proposed loading-free
extended counting topology and corresponding clocks. As
shown in Fig. 3, the clock signal y is the inverted signal of
x. The interval of both two signals include 34 sampling

(1)

The code Di-1 is decided by comparing the output voltage Vi-1

of the previous step. The code Di-1 is +1 if the voltage Vi-1 is
positive whereas -1 if the voltage Vi-1 is negative. Vref is the
feedback DAC reference voltage. Due to the initial reset, the

978-1-978-1-4673-3037-4/13/$31.00 2013 IEEE

i =1

where N is the number of sampling clock period during the

counting conversion. Then, the circuit goes into the second
step, and the SAR ADC is ready to convert the residual error.
After finishing the extended conversion, we assume that Bj is
an approximate result of the digital output code and ext is the
quantization error of the SAR ADC. The relative equation is
expressed as

As mentioned in Section I, a purely incremental ADC takes

very long conversion time growing up with the desired
resolution. Extended counting [1], [2] is an effective method
to reduce the conversion time in the same sampling rate.
Figure 1 is the block diagram of an incremental ADC with
extended counting technique. This architecture comprises a
switched-capacitor integrator which integrates the difference
between the input signal and the DAC output signal, a 1-bit
quantizer, a decimation filter realized by a simple digital
counter, and a SAR ADC for converting the residual error
and extending the resolution. With extended counting
technique, one conversion is separated into two steps [1].
Each step consists of several sampling clock periods. In the
first counting conversion step, the incremental ADC
operates as a resettable first-order DSM to generate the most
significant bits (MSB). After completing the first step, Vcount
shown in Fig. 1 is the residual error voltage which remains on
the feedback capacitor sets across the integrator. In the
second extended conversion step, the extended ADC
directly converts the residual error stored on the feedback
capacitor sets, i.e., the DAC array of the SAR ADC, to obtain
the least significant bits (LSB).
Figure 2 shows two operating phases, the input-sampling
phase 1 and the charge phase 2, during the counting
conversion step. Note that an incremental ADC needs N
sampling clock periods to carry out once MSB conversion
where the number of N is depended on the desired resolution.
This work is a fully differential implementation, and Fig. 2 is
shown in single-ended for the sake of simplicity. During 1,
the input Vin is sampled onto the sampling capacitor CS.
Meanwhile, quantizer compares the previous output voltage
Vi-1, and then returns the output code Di-1 to control reference
voltage. Taking the linearity into account, one bit quantizer
implemented by a conventional comparator is chosen. During
2, the difference between the input signal and the decided
reference signal is integrated to the feedback capacitor CF.
When the output voltage Vi is settled and remained on CF at
the end of the phase 2, the output voltage Vi for the ith step
can be written as
Vi = Vi 1 +

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IEEE 2nd International Symposium on Next-Generation Electronics (ISNE) - February 25-26 , Kaohsiung , Taiwan
clock periods depended on OSR of the first counting step in
this system.

whole conversion time with the proposed method is only

dominated by the period of the counting step because the
conversion time of the synchronous 7-bit SAR ADC is much
less than that of the incremental one.

Fig. 5 Dynamic comparator.

Fig. 3 The proposed loading-free extended counting architecture.

Fig. 6 Placement of the capacitor array.

IV.

A. Operational Amplifier
Figure 4 shows the operational amplifier scheme which is
used in incremental ADC system. Due to the requirement on
the large output swing, we choose class-AB two-stage
amplifier for the integrator. The telescopic amplifier as the
first stage of the opamp provides high open-loop DC-gain. To
increase the unity-gain bandwidth of the opamp with a given
tail current, two p-MOS transistors is used as the differential
pair. In addition to the bandwidth, the class-AB input
differential pair also arise the open-loop gain. The second
stage only uses a simple common-source amplifier to
maximize the usable output swing.

Fig. 4 Two-stage operational amplifier.

During x, the capacitor set Set-X including a binaryweighted capacitor array serves as a feedback capacitor
across opamp. The other one set Set-Y as same arrangement
as Set-X is connected to the comparator of SAR ADC and act
as the DAC capacitor array. After completing the counting
conversion at the falling edge of x, the residual error has
successfully been held on the Set-X. Then at the beginning of
y, the capacitor sets Set-X and Set-Y interchange
immediately. As illustrated in Fig. 3, Set-X as the feedback
capacitor of the incremental ADC is directly flipped to the
comparator input of the SAR ADC as a DAC capacitor array.
Set-X is now in extended step, and Set-Y is in counting step
on the contrary.
On the other hand, these interchange movements can
reduce the conversion time since the counting ADC and the
extended ADC operate in parallel. For example, in Fig. 3, the
incremental ADC is started to convert one input sample after
the RST signal occurs. This input signal accomplishes the
incremental ADC conversion at the end of x, and the
residual error held on Set-X is then flipped for the SAR ADC
conversion at the beginning of y. In the meantime, the next
input signal is processed under the counting mode of y with
the capacitor set Set-Y. Each counting step is not necessary to
start after the extended step but follows the preceding
counting one. This means that the proposed topology saves
the extended conversion time compared with the previous arts
of the incremental ADC with extended counting. Hence, the

978-1-978-1-4673-3037-4/13/$31.00 2013 IEEE

CIRCUIT IMPLEMENTATION

B. Comparator (Quantizer)
The dynamic comparator [5] with a reset clock is shown in
Fig. 5. This comparator is not only used in SAR ADC, but
serves as a quantizer in incremental ADC. When CLK is high,
the comparator outputs Q and Qb are both reset to high. When
CLK is from high to low, the differential pair compares two
input signals, Vcomp+ and Vcomp-. In other words, this
comparator does not consume static current due to the reset
clock.
C. Capacitor Array
Layout floorplan of a feedback capacitor array, i.e., the
DAC array of the SAR ADC, is shown in Fig. 6. The
capacitor array is arranged in a common-centroid way and
this can reduce the variation caused by standard process. All
capacitors in the design are built by a 21-fF unit capacitor.
For example, CF1 consists of 25 unit capacitors, which
capacitance is about 672 fF. We choose metal-insulator-metal
(MIM) capacitor to construct the capacitor array.

31

IEEE 2nd International Symposium on Next-Generation Electronics (ISNE) - February 25-26 , Kaohsiung , Taiwan

DR = 69.38 dB
SND
Clock_Gen

Counter
Incremental SAR
R
ADC
ADC
C

Fig. 9.
Fig. 7.

Baseband output power spectrum afteer reconstruction. (Post-layout

simulation)

Layout of whole ADC.

TABLE I
Spec.
Architecture

Fig. 8.

SUMMARIZE AND
D COMPARISON
*

This Work
Incremental
with SAR
0.18
1.8
3.765
69.38
11.23
23.07
2.55

Proc. (m)
Supply (V)
Rate (KS/s)
SNDR (dB)
ENOB (bit)
Power (W)
FoM (pJ)
Core Area
0.33
(mm2)
Post-layout simulation

[2]
Incremental
with cyclic
0.6
3.3
500
81
13.16
48000
10.49

[3]
2-order
incremental
0.18
1.8
1000
86.3
14.04
38100
2.26

[6]
Incremental
with cyclic
0.18
1.65
1
82.43
13.4
150
13.88

0.7

3.5

0.1

Static nonlinearity of DNL and INL.

VI.
V.

EXPERIMENTAL RESUL
LTS

The proposed circuit is simulated in a 0.18-m 1P6M

CMOS process. From the equation (4), the pparameter N is set
to 33, M is 7, CS is 1344 fF, and CF is 672 fF in this design.
This work adopts an incremental ADC to coonvert the first 5bit MSB and a synchronous SAR ADC to get the last 7-bit
LSB. Whole chip is composed of an increemental and SAR
ADC, along with a clock generator, a simpple counter as the
decimation filter, and output buffer. The llayout of the full
chip is shown in Fig. 7.
DNL and INL are
As shown in Fig. 8, the simulated peak D
0.3 / -0.2 LSB and 0.7 / -0.3 LSB, respecttively. This ADC
system operates at a clock frequency of 128 kHz and an
oversampling ratio of 32 to achieve a 4--KS/s conversion
bandwidth. Figure 9 shows the spectrum resuults of 1024-point
fast Fourier transform analysis with a sinnusoidal input of
close to 200 Hz. The signal-to-noise andd distortion ratio
(SNDR) achieves 69.38 dB in the post-layouut simulation, and
its corresponding effective number of bits (ENOB) is 11.23
bits. The total ADC dissipates 23.07 W,, including clock
generator and output buffer. The performannce of this design
is summarized and compared with similar sttructure in Table I.
Obviously, the proposed topology possess tthe feature of low
power so is suitable for biomedical applicaation. In Table I,
even FoM is not the best one among [2], [3]], and [6], but it is
comparable to the other excellent works.

978-1-978-1-4673-3037-4/13/$31.00 2013 IEEE

32

CONCLU
USION

A loading-free extended coun

nting technique for an
incremental ADC was proposed. This proposed topology
masterly removes the loading at inteegrator output to save the
opamp power consumption when using extended counting
o feedback capacitor sets,
technique. By interchanging the two
the whole conversion time is diminished.
d
In a given
conversion time, the requirement on the opamp power is
further reduced. This work achievees a peak SNDR of 69.38
dB and a power dissipation of 23.0
07 W at a 1.8-V power
supply and an about 4-kHz conversio
on rate.
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