Multiple

p Voltage
g Domains
(with Software Labs)
Material from Vazgen Melikyan, Synopsys
Co-developed for MSE Conference 2009
and Synopsys University Program
Prof. Dejan Markovi
Electrical Engineering Department
University of California, Los Angeles.
1

Low Power Design Flow

RTL Power Constructs

Definition of power domain

Isolation behavior of a particular signal
Retention behavior of particular registers
Power domain simulation
Isolation logic simulation

Logic Synthesis

Create Power Domains

Clock Gating
Apply OpCond on blocks
Special cell Insertion
Retention Cell Synthesis
Compile
MV DFT

Libraries

RTL Simulation

Physical Implementation

Verification

Voltage Area Creation

MTCMOS Insertion
Physical synthesis
Leakage optimization
MCMM
Scan reordering
MV aware CTS
MV aware Routing
RTL vs. Gates matching
Static Low Power Checks
Parasitic Extraction

Signoff

SI, Timing, Power Signoff

Power Network Analysis

UPF

Unified Power Format (UPF)

UPF
UPF provides the ability for electronic systems to be designed
with power as a key consideration early in the process
No existing HDL adequately supports the specification of
power distribution and management
Vendor-specific formats are non-portable and create
opportunities for bugs via inconsistent specifications

UPF: Definition
UPF Definition
Define power distribution architecture
Power domains
Supply rails
Switches

Create power management (operational) scenarios

Power state tables

Set usage of special low power cells

Switches
Isolation
Level shifters
Retention

UPF: Basic Design Flow

Design Specification (XML)
RTL

UPF

Logic Synthesis
Gate Level

UPF

Physical Synthesis
Gate Level
PG Gate Level

UPF

Power Aware
RTL and Gate Level
Functional Verification
Like Simulation Pattern to Verify
Power states from PST
Isolation value
Retention

Formal and Structural

Verification like Correct
Implementation of
Isolation
I l ti
Level shifter
Switches

1 Power Format for Implementation and Verification

6

Library Requirements for UPF (1)

Level shifters
is_level_shifter : true;

Identified in .lib by

Isolation cells
is_isolation_cell : true;

Identified in .lib by

Retention registers

retention_cell : cell_type;

Identified in .lib by

Power switch (MTCMOS) cells

Identified in .lib by

switch_cell_type : coarse_grain;

Library Requirements for UPF (2)

Power / ground (PG) pin
definitions are required for
all cells in a library

Defined as attributes in .lib

lib
Allows accurate definition of
multiple power / ground pin
information

Benefits

Power domain driven

synthesis
Automatic power net
connections
PST-based optimization
Verification of PG netlist vs.
power domains
Power switch verification
CCS Power library accuracy

pg_pin(VDD) {
std_cell_main_rail : true ;
voltage_name : VDD;
pg_type
: primary_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type
: primary_ground;
}

Chip Top Introduction

(Design used in Software Labs)

ChipTop Logic Design Structure

Synthesizable RTL code
Multiplier,
M lti li GPR
GPRs, MemX
M X and
d

Chi T
ChipTop

MemY are shutdown power

domains (PD)

GENPP is an always-on PD
within Multiplier

PwrCtrl

InstDecode

GPRs

1900um2

1197um2

34150um2

Multiplier
46089um2

Single clock
Number of clocked elements:
Combinational area:
Noncombinational area:
Dynamic Power:
Leakege Poower :

719
92.315um2
1650996um2
2.6193mW
1.39 mW

MemX

MemY

GENPP

174304.8um2

174304.8um2

26009um2

10

Power Management: Operating Voltages

ChipTop
(High Volt)

GPRs
(Low Volt, High Volt.
OFF)

MemXHier
(Low Volt, OFF)

MemX

Multiplier
(High Volt, OFF)
GENPP
(High Volt)

MemYHier
(Low Volt, OFF)

MemY

PwrCtrl

11

Power Nets Scheme

VDDI

VDDG

VDD

on/off

InstDecode

GPRs

0.8V

on/off

0.8V

VDDIS

1.0V

VDDGS

1.0V

OFF

OFF

inst_on

VSS

VSS

gprs_on
mult_on

Multiplier

ChipTop
1.0V

on/off

1.0V

GENPP

OFF

1.0V

VDDMS

VSS

12

Retention Registers Scheme

VDDG

VDDI
InstDecode

GPRs

on/off

0.8V

VDDIS

1.0V

OFF
RR

LS

NRESTORE

VDDGS

1.0V

OFF
ISO

on/off

0.8V

ELS

ISO

RR

LS

VSS

ELS

VSS

SAVE

VDD

VDD
on/off

Multiplier
1 0V
1.0V
OFF

GENPP

ISO

1.0V

ChipTop

VDDMS
ISO

1.0V

VSS

13

Low-Power Design Examples

(Software Labs)

14

Low power methodology manual

Laboratory works
Lab 1: Clock gating
Lab 2: Power gating
Lab 3: Multi-voltage design

15

LPMM Lab1: Clock gating DC commands

set_clock_gating_style

sets the clock gating style used for clock gate

insertion and replacement.

insert_clock_gating

performs clock gating on an appropriately

prepared GTECH netlist.

propagate_constraints
-gate_clock

propagates timing constraints from lower levels

of the design hierarchy to the current design.

report_clock_gating <hier> <-ungated>

reports information about clock gating

performed by Power Compiler.

16

LPMM Lab1: Clock Gating DC Script

#Reading design
analyze -library WORK -format verilog {./RTL/top_odyssey.v
./RTL/srff.v ./RTL/power_controller.v}
read_file -format verilog {./RTL/top_odyssey.v}

#Reading UPF
source ./inputs/chiptop+.upf

#Reading constraints
source ./inputs/chiptop+_s0.sdc

#Compiling
compile

-exact_map -gate_clock

#Generating clock gating report

report_clock_gating
p _
_g
g

#Writing out results

change_names -rule verilog hier
write -f verilog
-h -out
./results/compile.v
write -f ddc
-h -out ./results/compile.ddc
save_upf

./results/compile.upf

17

LPMM Lab1: DC and ICC views

18

LPMM Lab1: Results

Clock gating technique (Hw-5: update the numbers)
Total area:
47358.089912 um2
Total
T t l Dynamic
D
i P
Power :
522 6792 mW
522.6792
W
Without Clock gating technique (Hw-5: update)
Total area:
36996.139839 um2
Total Dynamic Power :
672.5113 mW
Area loss: 22%
Power gain: 28.6%

19

LPMM Lab2: Power gating UPF commands

create_power_domain

Creates power domain. Here domain name

and elements from it must be specified.

create_supply_port

Creates supply port for mentioned power

domain

create_supply_net

Creates supply net for power domain

connect_supply
pp y_net

set_domain_supply_net

Connects supply
pp y nets and p
ports
Sets power domains power/ground nets

20

10

LPMM Lab2: Power gating UPF commands

create_power_domain
create power switch
create_power_switch

Creates power domain. Here domain name and elements from it

must be specified.
Creates
C t a power switch
it h att a specified
ifi d power d
domain
i
Defines the UPF isolation strategy for the power domains in the
design

set_isolation
set_isolation_control

Provides additional options needed for creating isolation cells.

This command is needed with most set_isolation commands
Defines the UPF retention strategy for the power domains in the
design

set_retention
set_retention_control
map_retention_cell

Defines the UPF retention control signals for the defined UPF
retention strategy
Defines how to map the unmapped sequential cells to retention
cells for the specified retention strategy of the power domain.

21

LPMM Lab2: Power Gating UPF example (1)

create_power_domain TOP
create_power_domain GPRS

-elements GPRs

create_supply_port
create_supply_net
create_supply_net
connect_supply_net

VDD
VDD
VDD
VDD

-domain TOP
-domain GPRS reuse
-ports VDD

create_supply_port
create_supply_net
create_supply_net
connect_supply_net

VSS
VSS
VSS
VSS

-domain TOP
-domain GPRS -reuse
-ports VSS

create_supply_net

VDDGS

Creating power
domains

Creating supply
nets

-domain GPRS

set_domain_supply_net
t d
i
l
t TOP
\
-primary_power_net VDD \
-primary_ground_net VSS
set_domain_supply_net GPRS \
-primary_power_net VDDGS \
-primary_ground_net VSS

Setting primary
power/ground
nets

22

11

LPMM Lab2: Power Gating UPF example (2)

Creating power
switch

create_power_switch gprs_sw \
-domain GPRS \
-input_supply_port {in VDD} \
-output_supply_port
l
{
{out
VDDGS}
} \
-control_port {gprs_sd PwrCtrl/gprs_sd} \
-on_state {state2002 in {gprs_sd}}
set_isolation gprs_iso_out \
-domain GPRS \
-isolation_power_net VDD \
-isolation_ground_net VSS \
-clamp_value 1 \
-applies_to outputs

Setting Isolation

set_isolation_control gprs_iso_out \
-domain GPRS \
-isolation_signal PwrCtrl/gprs_iso \
-isolation_sense low \
-location parent

Setting Isolation
control options

23

LPMM Lab2: Power Gating UPF example (4)

Setting
Retention

set_retention gprs_ret -domain GPRS \

-retention_power_net VDDGS
\
-retention_ground_net VSS
set_retention_control gprs_ret
-domain
d
i GPRS \
-save_signal {PwrCtrl/gprs_restore low} \
-restore_signal {PwrCtrl/gprs_restore high}

Setting
Retention
control
options

map_retention_cell gprs_ret -domain GPRS -lib_cells RDFFNX1

add_port_state VDD
-state {HV 1.2}
add_port_state gprs_sw/out
-state {HV 1.2}\
-state {OFF off}
create pst chiptop_pst
create_pst
chiptop pst -supplies {VDD VDDGS}
add_pst_state overdrive -pst chiptop_pst -state
add_pst_state function1 -pst chiptop_pst -state
add_pst_state function2 -pst chiptop_pst -state
add_pst_state hibernate -pst chiptop_pst -state
add_pst_state sleep
-pst chiptop_pst -state

Mapping
Retention
cells to
librarys cell
{HV
{HV
{HV
{HV
{HV

HV}
HV}
OFF}
OFF}
OFF}

Port state
definition
Creating Port
State Table

24

12

LPMM Lab2: Power Gating DC Script

#Reading design
analyze -library WORK -format verilog
{./RTL/top_odyssey.v ./RTL/srff.v
./RTL/power_controller.v}
read_file -format verilog {./RTL/top_odyssey.v}
name_format \
-isolation_prefix "ISO_\
-level_shift_prefix "LS_

#Reading constraints
source ./inputs/chiptop+_s0.sdc
#Compiling
compile
#Writing out results
change_names -rule verilog hier
write -f verilog
-h -out
./results/compile.v
write -f ddc
-h -out ./results/compile.ddc
save_upf ./results/compile.upf

#Reading UPF
source ./inputs/chiptop+.upf

#Setting voltages and options

set_voltage 1.2 -obj {VDD VDDGS}
set_voltage 0.000 -obj {VSS}
set auto_insert_level_shifters_on_clocks all
set_dont_touch [get_nets Ovfl]
set_dont_use saed90nm_typ_ht/AODFF*
set_dont_use saed90nm_max/AODFF*
set_dont_use saed90nm_min/AODFF*

25

LPMM Lab2: Design environment & Tool

Chain of Physical Synthesis
Design
Constraints

RTL Code (Verilog /

VHDL)
Designed device

Macro
cells

I/O
cells

Design Library

Gate-level Netlist
(Verilog / VHDL)

Logic Synthesis
(DC)

Standard
cells

Physical Design
(ICC)
UPF

Design
Constraints

UPF

GDS II

26

13

LPMM Lab2: DC and ICC views

27

LPMM Lab2: Results

Power gating technique (not fully debugged)
Total Area:
130134.690886 um2
T t l Dynamic
Total
D
i P
Power:
329 0739 mW
329.0739
W
Without Power gating technique (debugging)
Total area:
88689.9541117 um2
Total Dynamic Power:
192.3634 mW
Area loss: 31.8%
Power gain: 41.6%

28

14

LPMM Lab3: Multi-Voltage UPF commands

create_power_domain

Creates power domain. Here domain name and

elements from it must be specified.

create_supply_port

Creates supply port for mentioned power domain

create_supply_net
connect_supply_net net
name -ports port
name
set_domain_supply_net

set_level_shifter

Creates supply net for power domain

Connects supply nets and ports

Sets power domains power/ground nets

Applies_to outputs -rule low_to_high -location parent
- Create the constraints for Level Shifter cell.

29

LPMM Lab3: Multi-Voltage UPF example (1)

create_power_domain TOP
create_power_domain GPRS

-elements GPRs

create_supply_port
create_supply_net
create_supply_net
connect_supply_net

VDD
VDD
VDD
VDD

-domain TOP
-domain GPRS reuse
-ports VDD

create_supply_port
create_supply_net
create_supply_net
connect_supply_net

VSS
VSS
VSS
VSS

-domain TOP
-domain GPRS -reuse
-ports VSS

create_supply_net

VDDGS

Creating power
domains

Creating supply
nets

-domain GPRS

set_domain_supply_net
t d
i
l
t TOP
\
-primary_power_net VDD \
-primary_ground_net VSS
set_domain_supply_net GPRS \
-primary_power_net VDDGS \
-primary_ground_net VSS

Setting primary
power/ground
nets

30

15

LPMM Lab3: Multi-Voltage UPF example (2)

set_isolation gprs_iso_out \
-domain GPRS \
-isolation_power_net VDD \
-isolation_ground_net VSS \
-clamp
p_value 1 \
-applies_to outputs

Setting Isolation

set_isolation_control gprs_iso_out \
-domain GPRS \
-isolation_signal PwrCtrl/gprs_iso \
-isolation_sense low \
-location parent

Setting Isolation
control options

add_port_state VDD
-state {HV 1.2}
add_port_state VDDGS -state {LV 0.7}

Port state definition

31

LPMM Lab3: Multi-Voltage DC Script

#Reading design
analyze -library WORK -format verilog
{./RTL/top_odyssey.v ./RTL/srff.v
./RTL/power_controller.v}
read_file -format verilog {./RTL/top_odyssey.v}
name_format \
-isolation_prefix "ISO_\
-level_shift_prefix "LS_
#Reading UPF
source ./inputs/chiptop+.upf
#Setting voltages and options
set_voltage 0.7 -obj {VDDGS}
set_voltage 1.2 -obj {VDD }
set voltage 0.000 -obj
set_voltage
obj {VSS}
set uto_insert_level_shifters_on_clocks all
set compile_preserve_subdesign_interfaces trueset
verilogout_show_unconnected_pins true
set_dont_touch [get_nets Ovfl]
set_dont_use saed90nm_typ_ht/AODFF*
set_dont_use saed90nm_max/AODFF*
set_dont_use saed90nm_min/AODFF*

#Reading constraints
source ./inputs/chiptop+_s0.sdc
#Compiling
compile
#Writing out results
change_names -rule verilog hier
write -f verilog
-h -out
./results/compile.v
write -f ddc
-h -out ./results/compile.ddc
save_upf ./results/compile.upf

32

16

LPMM Lab3: DC view

33

LPMM Lab3: Results

With Multi Voltage technique (Hw-5, update)
Total area:
1781481.983087 um2
T t l Dynamic
Total
D
i P
Power:
7 2485 W
7.2485
Without Multi Voltage technique (Hw-5, update)
Total area:
1215683.305258 um2
Total Dynamic Power:
10.0721 W
Area loss: 32%
Power gain: 28%

34

17