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I. INTRODUCTION
HE silicon on insulator (SOI) technology is extremely attractive in terms of performance (high speed, low power
consumption, radiation-hard) and advanced scalability [1]. As
compared to bulk silicon, the architecture of SOI MOSFETs is
more flexible because more parameterssuch as thicknesses of
film and buried oxide, substrate doping, and back gate biascan
be used for optimization and scaling. It is well known that the
short-channel effects are remarkably reduced in ultra-thin SOI
films [1][9]. 50 nm long MOSFETs were already processed on
26 nm SOI films [10]. But what are exactly the meaning and
the limits of an ultra thin film? We will demonstrate in Section II that transistors with a 1nm-thick body can be fabricated
and operated successfully.
A direct application of these extremely thin films is the
double-gate transistor (DG-MOSFET), which makes use of
the volume inversion concept formulated, in 1987, by Balestra
et al. [11]. Recently, these devices have received considerable
attention from the viewpoint of their technological feasibility
and theory. Several approaches for the device architecture have
been explored: gate-all-around (GAA) [7], Delta [12], lateral
epitaxial overgrowth [13], [14], folded-gate [15], Fin-gate [16],
self-alignment [17] etc. Electrostatic and Monte-Carlo sim-
Manuscript received May 1, 2002; revised February 19, 2003. The review of
the paper was arranged by Editor S. Kimura.
T. Ernst, S. Cristoloveanu, G. Ghibaudo, and T. Ouisse are with the Institute of
Microelectronics, Electromagnetism and Photonics (UMR CNRS, INPG UJF)
ENSERG, 38016 Grenoble Cedex 1, France.
S. Horiguchi, Y. Ono, and Y. Takahashi are with the NTT Basic Research
Laboratories, NTT Corporation, Kanagawa 243-0198, Japan.
K. Murase was with the NTT Basic Research Laboratories, NTT Corporation,
Kanagawa 243-0198, Japan. He is now with the NTT Electronics Corporation,
Kanagawa 243-0198, Japan
Digital Object Identifier 10.1109/TED.2003.811371
831
Fig. 1. Drain current versus front gate voltage (in weak and strong inversion),
with the back gate bias as a parameter, in a 1-nm-thick SOI MOSFET (V
50 mV, L = 30 m, W = 100 m).
(a)
(2)
and
(b)
Fig. 2. A 3-nm-thick SOI MOSFET. (a) TEM cross section showing the upper
gate oxide (50 nm), the silicon film, and the bottom buried oxide (62 nm). (b)
Drain current and transconductance versus front gate voltage, with the back gate
bias as a parameter (V = 50 mV, L = 30 m, W = 100 m).
832
Fig. 4.
(V
mV/dec
(5)
where
is the front channel mobility, and
is the mobility
degradation factor.
is available from (6), if the
The effective mobility
is determined independently. A widely
inversion charge
accepted technique in thin-oxide MOSFETs consists of split
measurements [25]. However, the tested devices had
rather thick oxides (i.e., very small capacitance values), so
is still
that the conventional equation
valid. This has been verified by measuring Shubnikov-de-Haas
oscillations [26], which yield direct and accurate values for the
density of charge carriers. It is clear from Fig. 5 that, even with
is pertwo activated gates, the linear relationship
fectly obeyed. (This linearity is no longer satisfied in thin-oxide
method becomes more
MOSFETs, where the split
appropriate.) It follows that equation
can be safely utilized to derive (7). Equation (7) then is used
from which the
to construct the function
mobility is extracted [23].
An acceptable value of the electron mobility (210 cm /Vs)
is found in 3-nm-thick MOSFETs, which implies that the
drastic thinning process has not destroyed the quality of the
Si-film and interface. However, the density of defects (oxidation-induced stacking faults essentially) does increase during
thinning, hence the carrier mobility decreases in the film and
at both interfaces. The front-channel mobility is a monotonic
function of thickness (Fig. 4): 260 cm /Vs in 5-nm-thick and
650 cm /Vs in 45-nm-thick transistors. A mobility degradation in 5 nm and 10 nm thick SOI films was also observed by
Mastrapasqua et al. [27].
We have already seen that the back interface of ultra-thin
films is permanently depleted. An interesting consequence
is the relative insensitiveness of the transconductance shape
and mobility value to back gate bias [i.e., more or less parallel
curves in Fig. 2(b)]. This is totally different from
the case of much thicker films (45 nm), where the back gate
voltage can induce an inverted or an accumulated back channel:
as the vertical field increases significantly from inversion to
accumulation, the transconductance peak is reduced by a factor
of two and the curves are qualitatively modified [1].
was evaluated from the depenThe series resistance
dence of the mobility degradation factor on channel length.
k
m is far below the
The estimated value
833
Fig. 6. Drain current and transconductance versus back gate bias, with the
front gate bias as a parameter (increasing V shifts the curves to the left; V
50 mV; same device as in Fig. 2).
'
834
(a)
but the superposition of the front and back channels, independent from each other. In Section IV, the difference between DG
and SG transistors in terms of current, transconductance, and
mobility is explained based on volume inversion and quantum
arguments.
IV. QUANTUM MODELING
The analysis of the carrier transport mechanisms in ultra-thin
SOI MOSFETs proceeds from the comparison between 1)
physics-based analytical and compact models [20], 2) advanced classical numerical simulations [2], [3], [5], and 3)
quantum simulations [29][38]. Since our devices are long,
the discussion of short-channel effects and scalability issues
is beyond the scope of this work. To clarify the remarkable
DG-transconductance gain (Fig. 7), the profiles of the carrier
mobility, concentration and electric field across the film depth
are calculated by solving self-consistently the 1-D Poisson
and Schrdinger equations. Similar simulations have been
described earlier [30][34], [36], hence we only discuss the
representative case of our 3-nm-thick SG and DG quantum
wells.
A. Potential Profile
The carrier confinement in very narrow potential wells is governed by the wave functions and energy levels of the various subbands. As the film becomes thinner than 10 nm, the energy levels
and their separation increases, making them harder to populate:
the threshold voltage increases (Fig. 4) [39]. The difference between asymmetrical SG and symmetrical DG wells is illustrated
in Fig. 9(a). Two distinct regions of operation are predicted in
3-nm MOSFETs.
1) At low and moderate vertical field (corresponding to
the regions of weak inversion, moderate inversion, and
transconductance peak), the potential well is essentially
thickness-defined. The electrons are confined mainly by
this infinitely-deep rectangular well; little additional
contribution arises from the potential profile, which is
quasiflat. The energy levels and the wave functions are
very similar in SG and DG modes.
2) At high electric field (strong inversion), the triangular
shape of the film potential becomes more pronounced,
primarily in SG-MOSFETs, and induces additional
carrier confinement. The quantization effects are lesser
in DG-MOSFETs than in SG-MOSFETs [Fig. 9(a)]; the
(b)
Fig. 9. (a) DG and SG potential wells and corresponding energy subbands
in strong inversion. (b) Quantum distributions of minority carriers (strong
inversion) in various subbands of a DG-well (- - - classical, nonquantum
profile).
Fig. 10. Inversion charge versus gate voltage in weak and strong inversion, for
DG and SG modes (t = 3 nm).
835
Fig. 11. Quantum profiles of minority carriers and electric field calculated for
a 3 nm thick transistor operated in DG and SG modes. The carrier mobility is
assumed to be severely degraded in the interface areas ( 1 nm, dark grey).
'
(9)
where
as
(10)
nm and
V/cm.
with
) shows
Integration over the whole film depth (i.e.,
that the effective fields in SG and DG modes are identical for
bias, and the DG mobility is just twice as large
constant
as in SG mode. These average values are well approximated by
(11)
for SG mode and
for DG mode. Besides the
with
gain in , this analysis does not reveal any additional advantage
of volume inversion on mobility.
However, if we assume that the inversion charge does not connm (where
), near
tribute to current over a depth
each interface, a clear difference appears between SG and DG
modes (Fig. 12). Since the average field is much lower, the average field-effect mobility is far higher in DG-mode than twice
the value in SG-mode. This is so because, in SG-MOSFETs, the
vertical field is stronger and many carriers flow in the rough
region near the front interface (Fig. 11).
836
Fig. 12. Average values of the electric field and carrier mobility versus gate
voltage, calculated with (9) and (10) for the 3 nm thick transistor of Fig. 2 (DG
and SG modes,
1 nm, t
= 50 nm, t
= 62 nm).
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