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Parity/VRC
BCC/LRC
CRC
Section A 6, Page 1
Generation of a
parity bit
Parity bits
Section A 6, Page 2
Section A 6, Page 3
With even
parity, there is
always an even
number of logic
1 bits in the
(Halsall Fig 3.14c, d)
code word (i.e.
the data with the
parity bit added)
Data Communications, Ed. 2, D. Lauder
Section A 6, Page 4
Block Check
Character
(BCC)
significantly
reduces the
probability of
undetected
errors compared
to parity alone
Section A 6, Page 5
Section A 6, Page 7
This is a
block coder
with k
information
digits going
in and n
digits
coming out
k information digits
n encoded digits
Block coder
Rate, R = k/n
k
n-k
Information
digits
Parity
digits
n digit codeword
Section A 6, Page 6
Section A 6, Page 8
Section A 6, Page 9
Section A 6, Page 10
CRC Generation
Let M(x) be the message to be transmitted,
which is k bits long
An n bit CRC is added such that k>n
Let G(x) be the divisor or generator which
is an (n+1) bit number
Let R(x) be the remainder which is the n bit
CRC. The CRC is appended to the message
before transmission
Section A 6, Page 11
Section A 6, Page 12
CRC example
Section A 6, Page 13
0000 is
appended
to message
(message is
multiplied
by 2n), then
CRC is
calculated
Indicates Bitwise
Exclusive OR operation
Transmitted
frame =
1110 0110 0110
Message CRC
(Halsall Fig 3.17a)
Section A 6, Page 14
Errors are
detected
whether
they are in
the message
bits or CRC
bits
(Halsall Fig 3.17b)
Section A 6, Page 15
Section A 6, Page 16
CRC generation by
hardware
Example shows 8 bit
message with 4 bit
CRC
The FCS shift
register contains all
0 bits initially
The data is sent
serially, followed by
the CRC
(Halsall Fig 3.18a)
Data Communications, Ed. 2, D. Lauder
Section A 6, Page 17
CRC checking by
hardware
The serial data is
received followed by
the CRC
After the data and
CRC have been
received, the FCS
shift register should
contain all 0 bits if
there are no errors
Section A 6, Page 18