Você está na página 1de 20

9.

5 RON 15 V/+12 V/5 V iCMOS


Serially-Controlled Octal SPST Switches
ADG1414

Data Sheet
FEATURES

FUNCTIONAL BLOCK DIAGRAM

SPI interface
Supports daisy-chain mode
9.5 on resistance @ 25C
1.6 on-resistance flatness
Fully specified at 15 V, +12 V, 5 V
3 V logic-compatible inputs
Rail-to-rail operation
24-lead TSSOP and 24-lead 4 mm 4 mm LFCSP

ADG1414
D2

S3

D3

S4

D4

S5

D5

S6

D6

S7

D7

S8

D8
INPUT SHIFT
REGISTER

Automatic test equipment


Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems

SCLK DIN SYNC

SDO

RESET/VL

Figure 1.

GENERAL DESCRIPTION
The ADG1414 is a monolithic complementary metal-oxide
semiconductor (CMOS) device containing eight independently
selectable switches designed on an industrial CMOS (iCMOS)
process. iCMOS is a modular manufacturing process combining
high voltage CMOS and bipolar technologies. iCMOS components
can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduce the
package size.
The ADG1414 is a set of octal SPST (single-pole, single-throw)
switches controlled via a 3-wire serial interface. On resistance is
closely matched between switches and is very flat over the full
signal range. Each switch conducts equally well in both directions and the input signal range extends to the supplies.

Rev. A

D1

S2

08497-001

APPLICATIONS

S1

Data is written to these devices in the form of eight bits; each


bit corresponds to one channel.
The ADG1414 utilizes a versatile 3-wire serial interface that
operates at clock rates of up to 50 MHz and is compatible with
standard SPI, QSPI, MICROWIRE, and DSP interface
standards. The output of the shift register, SDO, enables a
number of these parts to be daisy chained.
On power-up, all switches are in the off condition, and the
internal registers contain all zeros.

PRODUCT HIGHLIGHTS
1.
2.
3.
4.

50 MHz serial interface.


9.5 on resistance.
1.6 on-resistance flatness.
24-lead TSSOP and 4 mm 4 mm LFCSP packages.

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no


responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.


Tel: 781.329.4700 20092013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

ADG1414

Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1

ESD Caution................................................................................ 10

Applications ....................................................................................... 1

Pin Configurations and Function Descriptions ......................... 11

Functional Block Diagram .............................................................. 1

Typical Performance Characteristics ........................................... 13

Product Highlights ........................................................................... 1

Test Circuits..................................................................................... 16

Revision History ............................................................................... 2

Terminology .................................................................................... 18

Specifications..................................................................................... 3

Theory of Operation ...................................................................... 19

15 V Dual Supply ....................................................................... 3

Serial Interface ............................................................................ 19

12 V Single Supply ........................................................................ 4

Input Shift Register .................................................................... 19

5 V Dual Supply ......................................................................... 6

Power-On Reset .......................................................................... 19

Continuous Current per Channel .............................................. 7

Daisy Chaining ........................................................................... 19

Timing Characteristics ................................................................ 8

Outline Dimensions ....................................................................... 20

Absolute Maximum Ratings .......................................................... 10

Ordering Guide .......................................................................... 20

Thermal Resistance .................................................................... 10

REVISION HISTORY
1/13Rev. 0 to Rev. A
Changes to Pin RESET/VL Description ....................................... 11
Changes to Power-On Reset Section ............................................ 19
Updated Outline Dimensions ....................................................... 20
10/09Revision 0: Initial Version

Rev. A | Page 2 of 20

Data Sheet

ADG1414

SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V 10%, VSS = 15 V 10%, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)

On-Resistance Match Between


Channels (RON)
On-Resistance Flatness (RFLAT(ON))

+25C

40C to
+85C

VSS to VDD
9.5
11.5
0.55

14

1
1.6
1.9

1.5

1.7

2.15

2.3

LEAKAGE CURRENTS
Source Off Leakage, IS (Off )

0.05
1

Drain Off Leakage, ID (Off )

0.15
0.05
0.15
0.1
0.3

Channel On Leakage, ID, IS (On)


DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current

40C to
+125C

16

High Impedance Leakage Current

VS = 10 V, VD = 10 V; see Figure 24

VS = VD = 10 V; see Figure 25

nA max
nA typ
nA max
V min
V max
A typ
A max
pF typ

VIN = VGND or VL

4
0.4
0.6
0.001
4

3 dB Bandwidth
Insertion Loss
CD, CS (Off )
CD, CS (On)

256
0.55
8
32

VDD = +13.5 V, VSS = 13.5 V, VS = 10 V, IS =


10 mA
VDD = +16.5 V, VSS = 16.5 V
VS = 10 V, VD = 10 V; see Figure 24

0.001

Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion (THD + N)

tOFF

max
typ
max

VDD = +13.5 V, VSS = 13.5 V, VS = 10 V, IS =


10 mA

nA max
nA typ

2.0
0.8

75
93
25
35
10
73
75
0.05

max
typ

VDD = +13.5 V, VSS = 13.5 V, VS = 10 V, IS =


10 mA; see Figure 23

1
High Impedance Output
Capacitance1
DYNAMIC CHARACTERISTICS1
tON

V
typ

Test Conditions/Comments

nA typ

0.1
Digital Input Capacitance, CIN
LOGIC OUTPUTS (SDO)
Output Low Voltage, VOL 1

Unit

110

120

35

35

V max
V max
A typ
A max
pF typ

ISINK = 3 mA
ISINK = 6 mA

ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ

RL = 100 , CL = 35 pF
VS = 10 V; see Figure 30
RL = 100 , CL = 35 pF
VS = 10 V; see Figure 30
VS = 0 V, RS = 0 , CL = 1 nF; see Figure 31
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27
RL = 110 , 15 V p-p, f = 20 Hz to 20 kHz; see
Figure 29
RL = 50 , CL = 5 pF; see Figure 28
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28
f = 1 MHz
f = 1 MHz

MHz typ
dB typ
pF typ
pF typ

Rev. A | Page 3 of 20

ADG1414

Data Sheet

Parameter
POWER REQUIREMENTS
IDD

40C to
+85C

+25C

40C to
+125C

0.001
1

IL Inactive

0.3

IL Active @ 30 MHz

0.26

IL Active @ 50 MHz

0.3

0.35

0.5

0.55

0.42

ISS

0.001
1
4.5/16.5

VDD/VSS
1

Unit
A typ
A max
A typ
A max
mA typ
mA max
mA typ
mA max
A typ
A max
V min/max

Test Conditions/Comments
VDD = +16.5 V, VSS = 16.5 V
Digital inputs = 0 V or VL
Digital inputs = 0 V or VL
Digital inputs toggle between 0 V and VL
Digital inputs toggle between 0 V and VL
Digital inputs = 0 V or VL

Guaranteed by design, not subject to production test.

12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)

On-Resistance Match Between


Channels (RON)
On-Resistance Flatness (RFLAT(ON))

+25C

40C to
+85C

40C to
+125C
0 to VDD

18
21.5
0.55

26

1.2
5

1.6

6.9

28.5

1.8

7.3

LEAKAGE CURRENTS
Source Off Leakage, IS (Off )

0.02
0.15
0.02

Drain Off Leakage, ID (Off )

0.15
0.05
0.3

Channel On Leakage, ID, IS (On)


DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current

High Impedance Leakage Current


High Impedance Output
Capacitance1

V
typ
max
typ
max
typ

2.0
0.8
0.001
4
0.4
0.6
1
4

Rev. A | Page 4 of 20

Test Conditions/Comments

VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,


IS = 10 mA; see Figure 23
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,
IS = 10 mA
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,
IS = 10 mA

max
nA typ

0.1
Digital Input Capacitance, CIN
LOGIC OUTPUTS (SDO)
VOL, Output Low Voltage 1

Unit

nA max
nA typ

VDD = 10.8 V
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 24
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 24

nA max
nA typ
nA max

VS = VD = 1 V or 10 V; see Figure 25

V min
V max
A typ
A max
pF typ

VIN = VGND or VL

V max
V max
A max
pF typ

ISINK = 3 mA
ISINK = 6 mA

Data Sheet
Parameter
DYNAMIC CHARACTERISTICS1
tON

ADG1414
+25C

40C to
+85C

40C to
+125C

220

240

46

46

Test Conditions/Comments

ns typ
ns max
ns typ
ns max
pC typ

RL = 100 , CL = 35 pF
VS = 8 V; see Figure 30
RL = 100 , CL = 35 pF
VS = 8 V; see Figure 30
VS = 6 V, RS = 0 , CL = 1 nF; see
Figure 31
RL = 50 , CL = 5 pF, f = 1 MHz;
see Figure 26
RL = 50 , CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 50 , CL = 5 pF; see Figure 28
RL = 50 , CL = 5 pF, f = 1 MHz; see
Figure 28
f = 1 MHz
f = 1 MHz
VDD = +13.2 V
Digital inputs = 0 V or VL

Charge Injection

145
185
35
45
8

Off Isolation

70

dB typ

Channel-to-Channel Crosstalk

75

dB typ

3 dB Bandwidth
Insertion Loss

240
1.15

MHz typ
dB typ

12
33

pF typ
pF typ

tOFF

CD, CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD

0.001
1

IL Inactive

0.3
1

IL Active @ 30 MHz

0.26

IL Active @ 50 MHz

0.42

ISS

0.001

0.3

0.5

VDD/VSS
1

Unit

0.35

0.55
1
4.5/16.5

Guaranteed by design, not subject to production test.

Rev. A | Page 5 of 20

A typ
A max
A typ
A max
mA typ
mA max
mA typ
mA max
A typ
A max
V min/max

Digital inputs = 0 V or VL
Digital inputs toggle between 0 V
and VL
Digital inputs toggle between 0V
and VL
Digital inputs = 0 V or VL

ADG1414

Data Sheet

5 V DUAL SUPPLY
VDD = +5 V 10%, VSS = 5 V 10%, VL = 2.7 V to VDD, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)

On-Resistance Match Between


Channels (RON)
On-Resistance Flatness (RFLAT(ON))

+25C

40C to
+85C

VSS to VDD
21
25
0.6

29

1.3
5.2
6.4

1.7

1.9

7.3

7.6

LEAKAGE CURRENTS
Source Off Leakage, IS (Off )

0.02
1

Drain Off Leakage, ID (Off )

0.15
0.02
0.15
0.05
0.3

Channel On Leakage, ID, IS (On)


DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current

40C to
+125C

32

High Impedance Leakage Current


High Impedance Output
Capacitance1
DYNAMIC CHARACTERISTICS1
tON

VS = 4.5 V, VD = 4.5 V; see Figure 24

VS = VD = 4.5 V; see Figure 25

nA max
nA typ
nA max
V min
V max
A typ
A max
pF typ

VIN = VGND or VL

0.4
0.6
1
4

256
1
11
35

VDD = +4.5 V, VSS = 4.5 V, VS = 4.5 V;


IS = 10 mA
VDD = +5.5 V, VSS = 5.5 V
VS = 4.5 V, VD = 4.5 V; see Figure 24

3 dB Bandwidth
Insertion Loss
CD, CS (Off )
CD, CS (On)

max
typ
max

VDD = +4.5 V, VSS = 4.5 V, VS = 4.5V, IS =


10 mA

nA max
nA typ

0.001

Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion, THD + N

tOFF

max
typ

VDD = +4.5 V, VSS = 4.5 V, VS = 4.5 V, IS =


10 mA; see Figure 23

2.0
0.8

190
250
45
60
7
70
75
0.14

V
typ

Test Conditions/Comments

nA typ

0.1
Digital Input Capacitance, CIN
LOGIC OUTPUTS (SDO)
VOL, Output Low Voltage 1

Unit

290

320

65

70

V max
V max
A max
pF typ

ISINK = 3 mA
ISINK = 6 mA

ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ

RL = 100 , CL = 35 pF
VS = 3 V; see Figure 30
RL = 100 , CL = 35 pF
VS = 3 V; see Figure 30
VS = 0 V, RS = 0 , CL = 1 nF; see Figure 31
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27
RL = 110 , 5 V p-p, f = 20 Hz to 20 kHz; see
Figure 29
RL = 50 , CL = 5 pF; see Figure 28
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28
f = 1 MHz
f = 1 MHz

MHz typ
dB typ
pF typ
pF typ

Rev. A | Page 6 of 20

Data Sheet
Parameter
POWER REQUIREMENTS
IDD

ADG1414
+25C

40C to
+85C

40C to
+125C

0.001
1

IL Inactive

0.3

IL Active @ 30 MHz

0.26

IL Active @ 50 MHz
ISS

0.3

0.35

0.5

0.55

0.42
0.001
1
4.5/16.5

VDD/VSS
1

Unit
A typ
A max
A typ
A max
mA typ
mA max
mA typ
mA max
A typ
A max
V min/max

Test Conditions/Comments
VDD = +5.5 V, VSS = 5.5 V
Digital inputs = 0 V or VL
Digital inputs = 0 V or VL
Digital inputs toggle between 0 V and VL
Digital inputs toggle between 0 V and VL
Digital inputs = 0 V or VL

Guaranteed by design, not subject to production test.

CONTINUOUS CURRENT PER CHANNEL


Table 4. Eight Channels On
Parameter
CONTINUOUS CURRENT PER CHANNEL 1
15 V Dual Supply
24-Lead TSSOP (JA = 112.6C/W)
24-Lead LFCSP (JA = 30.4C/W)
12 V Single Supply
24-Lead TSSOP (JA = 112.6C/W)
24-Lead LFCSP (JA = 30.4C/W)
5 V Dual Supply
24-Lead TSSOP (JA = 112.6C/W)
24-Lead LFCSP (JA = 30.4C/W)
1

25C

85C

125C

Unit

67
121

46
75

31
42

mA max
mA max

64
115

44
72

30
41

mA max
mA max

48
86

35
57

22
36

mA max
mA max

25C

85C

125C

Unit

169
295

97
139

48
55

mA max
mA max

161
281

93
135

47
54

mA max
mA max

122
214

76
114

43
51

mA max
mA max

Test Conditions/Comments
VDD = +13.5 V, VSS = 13.5 V

VDD = 10.8 V, VSS = 0 V

VDD = +4.5 V, VSS = 4.5 V

Guaranteed by design, not subject to production test.

Table 5. One Channel On


Parameter
CONTINUOUS CURRENT PER CHANNEL 1
15 V Dual Supply
24-Lead TSSOP (JA = 112.6C/W)
24-Lead LFCSP (JA = 30.4C/W)
12 V Single Supply
24-Lead TSSOP (JA = 112.6C/W)
24-Lead LFCSP (JA = 30.4C/W)
5 V Dual Supply
24-Lead TSSOP (JA = 112.6C/W)
24-Lead LFCSP (JA = 30.4C/W)
1

Test Conditions/Comments
VDD = +13.5 V, VSS = 13.5 V

VDD = 10.8 V, VSS = 0 V

VDD = +4.5 V, VSS = 4.5 V

Guaranteed by design, not subject to production test.

Rev. A | Page 7 of 20

ADG1414

Data Sheet

TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).
VDD = 4.5 V to 16.5 V; VSS = 16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX,
unless otherwise noted. 1
Table 6.
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11 3
t12
1
2
3

Limit at TMIN, TMAX


20
9
9
5
5
5
5
15
5
5
40
15

Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min

Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK active edge setup time
Data setup time
Data hold time
SCLK active edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK active edge ignored
SCLK active edge to SYNC falling edge ignored
SCLK rising edge to SDO valid
Minimum RESET pulse width

Guaranteed by design and characterization, not production tested.


Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = 16.5 V to 0 V, VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V.
Measured with the 1 k pull-up resistor to VL and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode.

Timing Diagrams
t10

t1

t9

SCLK

t8

t2

t3

t7

t4
SYNC

t6
t5
DIN

DB7

DB0

08497-002

RESET

t12

Figure 2. Serial Write Operation

Rev. A | Page 8 of 20

Data Sheet

ADG1414
t1

SCLK

t8

t3

t4

16

t9

t2
t7

SYNC

t5
t6
DIN

DB7

DB0

DB0

DB7

INPUT WORD FOR DEVICE N + 1

INPUT WORD FOR DEVICE N

t11
DB0

DB31

UNDEFINED

INPUT WORD FOR DEVICE N

Figure 3. Daisy-Chain Timing Diagram

Rev. A | Page 9 of 20

08497-003

SDO

ADG1414

Data Sheet

ABSOLUTE MAXIMUM RATINGS


TA = 25C, unless otherwise noted.
Table 7.
Parameter
VDD to VSS
VDD to GND
VSS to GND
VL to GND
Analog Inputs1
Digital Inputs1
Continuous Current, Sx or Dx
Pins
Peak Current, Sx or Dx (Pulsed
at 1 ms, 10% Duty Cycle Max)
TSSOP Package
LFCSP Package
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak
Temperature, Pb free
Time at Peak Temperature
1

Rating
35 V
0.3 V to +25 V
+0.3 V to 25 V
0.3 V to +7 V
VSS 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND 0.3 V to VL + 0.3 V or
30 mA, whichever occurs first
Table 4 specifications + 15%

300 mA
400 mA
40C to +125C
65C to +150C
150C
260C

Stresses above those listed under Absolute Maximum Ratings


may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any one
time.

THERMAL RESISTANCE
Table 8. Thermal Resistance
Package Type
24-Lead TSSOP1
24-Lead LFCSP2
1
2

JA
112.6
30.4

4-layer board.
4-layer board and exposed paddle soldered to VSS.

ESD CAUTION

10 sec to 40 sec

Overvoltages at the analog and digital inputs are clamped by internal


diodes. Limit the current to the maximum ratings given.

Rev. A | Page 10 of 20

JC
50

Unit
C/W
C/W

Data Sheet

ADG1414

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS


SCLK 1

22 SDO

GND 4

21 VSS

D2 8

20 S8

GND
S1
D1
S2
D2
S3

19 D8
18 S7
17 D7

S3 9

16 S6

D3 10

15 D6

S4 11

14 S5

D4 12

13 D5

1
2
3
4
5
6

PIN 1
INDICATOR

ADG1414
TOP VIEW
(Not to Scale)

18
17
16
15
14
13

VSS
S8
D8
S7
D7
S6

NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.

Figure 4. TSSOP Pin Configuration

08497-005

TOP VIEW
(Not to Scale)

7
8
9
10
11
12

S2 7

ADG1414

D3
S4
D4
D5
S5
D6

D1 6

08497-004

S1 5

24
23
22
21
20
19

23 RESET/VL

DIN 3

DIN
VDD
SCLK
SYNC
RESET/VL
SDO

24 SYNC

VDD 2

Figure 5. LFCSP Pin Configuration

Table 9. Pin Function Descriptions


TSSOP
1

Pin No.
LFCSP
22

Mnemonic
SCLK

2
3

23
24

VDD
DIN

4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

GND
S1
D1
S2
D2
S3
D3
S4
D4
D5
S5
D6
S6
D7
S7
D8
S8
VSS

22

19

SDO

23

20

RESET/VL

Description
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates of up to 50 MHz.
Most Positive Power Supply Potential.
Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Ground (0 V) Reference.
Source Terminal 1. This pin can be an input or an output.
Drain Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Drain Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Drain Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Drain Terminal 4. This pin can be an input or an output.
Drain Terminal 5. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Drain Terminal 6. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Drain Terminal 7. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Drain Terminal 8. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, it can be connected to
ground.
Serial Data Output. This pin can be used for daisy-chaining a number of these devices together or
for reading back the data in the shift register for diagnostic purposes. The serial data is transferred
on the rising edge of SCLK and is valid on the falling edge of the clock. Pull this open-drain output
to the supply with an external resistor.
RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V
to 5 V supply. Pull the pin low (<0.8 V) for a short period of time (15 ns is sufficient) to complete a
hardware reset. All switches are opened, and the appropriate registers are cleared to 0. When
using the RESET/VL pin to complete a hardware reset, all other SPI pins (SYNC, SCLK, and DIN)
should be driven low.

Rev. A | Page 11 of 20

ADG1414
TSSOP
24

N/A 1
1

Data Sheet

Pin No.
LFCSP
21

Mnemonic
SYNC

EP

Exposed Pad

Description
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is
transferred in on the falling edges of the following clocks. Taking SYNC high updates the switch
condition.
Exposed Pad. Exposed pad tied to the substrate, VSS.

N/A means not applicable.

Rev. A | Page 12 of 20

Data Sheet

ADG1414

TYPICAL PERFORMANCE CHARACTERISTICS


16

18

VDD = +10V
VSS = 10V

VDD = +13.5V
VSS = 13.5V

14

15
VDD = +12V
VSS = 12V

ON RESISTANCE ()

ON RESISTANCE ()

12
10
8
6

VDD = +16.5V
VSS = 16.5V

VDD = +15V
VSS = 15V

12

TA = +125C
TA = +85C

TA = +25C
6

TA = 40C

3
2

1.5

4.5

1.5

7.5

10.5 13.5 16.5

VS, VD (V)

0
15

08497-006

0
16.5 13.5 10.5 7.5 4.5

Figure 6. On Resistance as a Function of VD (VS), Dual Supply

15

25

ON RESISTANCE ()

VDD = +5.0V
VSS = 5.0V

15
VDD = +5.5V
VSS = 5.5V

10
VDD = +7V
VSS = 7V

TA = +25C
10

TA = 40C

VS, VD (V)

0
5

VS, VD (V)

08497-010

TA = +85C
15

VDD = +5V
VSS = 5V

TA = 25C
IS = 10mA
5

TA = +125C

20

08497-007

Figure 10. On Resistance as a Function of VD (VS), for Different Temperatures,


5 V Dual Supply

Figure 7. On Resistance as a Function of VD (Vs), Dual Supply

25

40
VDD = +5V
VSS = 0V

35
30

20

ON RESISTANCE ()

VDD = +8V
VSS = 0V

25
20
VDD = +10.8V
VSS = 0V

15

VDD = +12V
VSS = 0V

10

TA = +125C
15
TA = +85C
TA = +25C

10

TA = 40C
5

VDD = +15V
VSS = 0V

5
TA = 25C
IS = 10mA
1.5

3.0

VDD = +12V
VSS = 0V
0

4.5

6.0

7.5

9.0

10.5

12.0 13.5

15.0

VS, VD (V)

Figure 8. On Resistance as a Function of VD (VS), Single Supply

08497-008

VDD = +13.2V
VSS = 0V

6
VS, VD (V)

10

12

08497-011

ON RESISTANCE ()

10

Figure 9. On Resistance as a Function of VD (VS), for Different Temperatures,


15 V Dual Supply

VDD = +4.5V
VSS = 4.5V

ON RESISTANCE ()

30

20

VDD = +3.0V
VSS = 3.0V

30

0
7

VS, VD (V)

35

25

10

08497-009

VDD = +15V
VSS = 15V

TA = 25C
IS = 10mA

Figure 11. On Resistance as a Function of VD (VS), for Different Temperatures,


12 V Single Supply

Rev. A | Page 13 of 20

ADG1414

Data Sheet

2.5

500

IDD PER LOGIC INPUT


TA = 25C

VL = 5.5V
ID, IS (ON)

1.5

400

ID (OFF) +
IS (OFF) +

1.0

ID, IS (ON) ++

0.5

IDD (A)

LEAKAGE CURRENT (nA)

VDD = +15V
VSS = 15V
2.0
VBIAS = +10/10V

300

200
0.5
IS (OFF) +

1.0

100
ID (OFF) +

1.5

40

60

80

100

120

TEMPERATURE (C)

0.5

1.0

80

CHARGE INJECTION (pC)

2.0
1.5
ID, IS (ON)
1.0
ID (OFF) +
IS (OFF) +

1.0
20

40

60

80

100

120

TEMPERATURE (C)

4.0

4.5

5.0

TA = 25C

40
20

VDD = +5V
VSS = 5V

VDD = +12V
VSS = 0V

0
20

60
15

VDD = +15V
VSS = 15V

10

10

15

VS (V)

Figure 16. Charge Injection vs. Source Voltage

Figure 13. Leakage Current as a Function of Temperature,


5 V Dual Supply
300

3.0

VDD = 12V
VSS = 0V
2.5 VBIAS = 1V/10V

ID, IS (ON) ++

250

2.0

tON (5V)
200

1.5

TIME (ns)

LEAKAGE CURRENT (nA)

3.5

40

IS (OFF) +
ID (OFF) +
0

3.0

60

08497-014

LEAKAGE CURRENT (nA)

ID, IS (ON) ++

0.5

2.5

Figure 15. IDD vs. Logic Level

3.0

0.5

2.0

LOGIC LEVEL (V)

Figure 12. Leakage Current as a Function of Temperature, 15 V Dual Supply

VDD = +5V
VSS = 5V
2.5 VBIAS = +4.5/4.5V

1.5

08497-017

20

08497-013

08497-016

VL = 2.7V

2.0

ID, IS (ON)
1.0

ID (OFF) +

0.5

IS (OFF) +

tON (+12V)
150

100

tON (15V)

tOFF (5V)
50
ID (OFF) +

1.0
0

20

40

60

80

TEMPERATURE (C)

100

120

Figure 14. Leakage Current as a Function of Temperature, 12 V Single Supply

Rev. A | Page 14 of 20

0
40

tOFF (+12V)

tOFF (15V)
20

20

40

60

80

100

TEMPERATURE (C)

Figure 17. Transition Time vs. Temperature

120

08497-018

IS (OFF) +

08497-015

0.5

Data Sheet
0

0.20

LOAD = 110
0.18 TA = 25C

TA = 25C
VDD = +15V
VSS = 15V

0.16

VDD = +5V, VSS = 5V, VS = +5V p-p

0.14

40

THD + N (%)

OFF ISOLATION (dB)

20

ADG1414

60

0.12
0.10
0.08
VDD = +15V, VSS = 15V, VS = +10V p-p

80

0.06
0.04

100

10k

100k

1M

10M

100M

1G

FREQUENCY (Hz)

08497-019

120
1k

5000

Figure 18. Off Isolation vs. Frequency

15,000

20,000

Figure 21. THD + N vs. Frequency, 15 V Dual Supply

TA = 25C
VDD = +15V
VSS = 15V

0.5

20

TA = 25C
VDD = +15V
VSS = 15V

1.0

40
1.5

ACPSRR (dB)

INSERTION LOSS (dB)

10,000
FREQUENCY (Hz)

08497-023

0.02

2.0
2.5

NO DECOUPLING
CAPACITORS

60
DECOUPLING
CAPACITORS

80
3.0

100

10k

100k

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 19. On Response vs. Frequency


0

TA = 25C
VDD = +15V
VSS = 15V

40

60

80

100

120
10k

100k

1M

10M

100M

FREQUENCY (Hz)

10k

100k

1M

FREQUENCY (Hz)

Figure 22. ACPSRR vs. Frequency

1G

08497-021

CROSSTALK (dB)

20

120
1k

Figure 20. Crosstalk vs. Frequency

Rev. A | Page 15 of 20

10M

08497-025

4.0
1k

08497-012

3.5

ADG1414

Data Sheet

TEST CIRCUITS
IDS

V1

ID (OFF)
A

NC

VD

VS

VDD

0.1F

NETWORK
ANALYZER

0.1F

VDD

50

IN

VS

VS

RL
50

GND

VOUT

VIN

OFF ISOLATION = 20 log

VOUT
VS

INSERTION LOSS = 20 log

Figure 26. Off Isolation

VDD

RL
50

VOUT

VOUT WITH SWITCH


VOUT WITHOUT SWITCH

Figure 28. Insertion Loss

VSS
0.1F

0.1F

VDD

VSS
0.1F

0.1F

VDD

VSS

S1

VDD

D
S2

AUDIO PRECISION

VSS

RS

R
50

S
IN

VS

VS
V p-p
D

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

VIN

VOUT
VS

GND

RL
10k

Figure 29. THD + Noise

Figure 27. Channel-to-Channel Crosstalk

Rev. A | Page 16 of 20

VOUT
08497-035

GND

08497-033

VOUT

RL
50

GND
08497-032

VIN

NETWORK
ANALYZER

NETWORK
ANALYZER

VSS
S

50

50

IN

VD

VSS

0.1F

VSS

08497-034

VDD

ID (ON)

Figure 25. On Leakage

VSS

0.1F

NC = NO CONNECT

Figure 24. Off Leakage

Figure 23. On Resistance

VDD

08497-027

RON = V1/IDS

08497-026

VS

08497-028

IS (OFF)

Data Sheet

ADG1414
VDD

VSS

0.1F

0.1F

VSS

VOUT

VS
INPUT LOGIC

RL
300

CL
35pF

SYNC

50%

50%
90%

90%

VOUT

GND

tON

tOFF

08497-029

VDD

Figure 30. Switching Times

3V
SYNC
RS

VDD

VSS

VDD

VSS

QINJ = CL VOUT

INPUT LOGIC
VOUT

SWITCH OFF

SWITCH ON

Figure 31. Charge Injection

Rev. A | Page 17 of 20

GND

08497-031

VOUT

VOUT
CL
1nF

VS

ADG1414

Data Sheet

TERMINOLOGY
IDD
The positive supply current.

CD, CS (On)
The on switch capacitance, measured with reference to ground.

ISS
The negative supply current.

CIN
The digital input capacitance.

VD (VS)
The analog voltage on Terminal Dx or Terminal Sx.

tON
The delay between applying the digital control input and the
output switching on. See Figure 30.

RON
The ohmic resistance between Terminal Dx and Terminal Sx.
RON
The difference between the RON of any two channels.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.

tOFF
The delay between applying the digital control input and the
output switching off. See Figure 30.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.

ID (Off)
The drain leakage current with the switch off.

Bandwidth
The frequency at which the output is attenuated by 3 dB.

ID, IS (On)
The channel leakage current with the switch on.

On Response
The frequency response of the on switch.

VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.

Insertion Loss
The loss due to the on resistance of the switch.

IINL (IINH)
The input current of the digital input.

THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.

CS (Off)
The off switch source capacitance, measured with reference
to ground.
CD (Off)
The off switch drain capacitance, measured with reference to
ground.

AC Power Supply Rejection Ratio (ACPSRR)


A measure of the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of
signal on the output to the amplitude of the modulation is the
ACPSRR.

Rev. A | Page 18 of 20

Data Sheet

ADG1414

THEORY OF OPERATION
The ADG1414 is a set of serially controlled, octal SPST switches.
Each of the eight bits of the 8-bit write corresponds to one
switch of the device. A Logic 1 in the particular bit position
turns the switch on, whereas a Logic 0 turns the switch off.
Because each switch is independently controlled by an individual
bit, this provides the option of having any, all, or none of the
switches turned on.

SERIAL INTERFACE
The ADG1414 has a 3-wire serial interface (SYNC, SCLK, and
DIN pins) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. This
enables the input shift register. Data from the DIN line is
clocked into the 8-bit input shift register on the falling edge of
SCLK. The serial clock frequency can be as high as 50 MHz,
making the ADG1414 compatible with high speed DSPs.
Data can be written to the shift register in more or less than
eight bits. In each case, the shift register retains the last eight
bits that were written. When all eight bits have been written
into the shift register, the SYNC line is brought high again. The
switches are updated with the new configuration, and the input
shift register is disabled. With SYNC held high, the input shift
register is disabled; therefore, further data or noise on the DIN
line has no effect on the shift register.
Data appears on the SDO pin on the rising edge of SCLK
suitable for daisy chaining or readback, delayed by eight bits.

INPUT SHIFT REGISTER


The input shift register is eight bits wide (see Table 10). Each bit
controls one switch. These data bits are transferred to the switch
register on the rising edge of SYNC.
Table 10. ADG1414 Input Shift Register Bit Map1
MSB
DB7
S8
1

DB6
S7

DB5
S6

DB4
S5

DB3
S4

DB2
S3

Logic 0 = switch off and Logic 1 = switch on.

DB1
S2

LSB
DB0
S1

POWER-ON RESET
The ADG1414 contains a power-on reset circuit. On power-up
of the device, all switches are in the off condition and the internal shift register is filled with zeros and remains so until a valid
write takes place.
The part also has a RESET/VL pin. Under normal operation,
drive the RESET/VL pin with a 2.7 V to 5 V supply and pull the
pin low for short period of time (15 ns is sufficient) to complete
the hardware reset.
When using the RESET/VL pin to do a hardware reset, drive all
other SPI pins (SYNC, SCLK, and DIN) low. This is to prevent
current flow due to ESD protection diodes on the VL pin to the
SPI pins.
When the RESET/VL pin is low, all switches are off and the
appropriate registers are cleared to 0.

DAISY CHAINING
For systems that contain several switches, the SDO pin can be
used to daisy-chain several devices together. The SDO pin can
also be used for diagnostic purposes and provide serial readback,
wherein the user can read back the switch contents.
SDO is an open-drain output that should be pulled to the VL
supply with an external resistor.
The SCLK is continuously applied to the input shift register
when SYNC is low. If more than eight clock pulses are applied,
the data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next device in the chain, a multiswitch interface is
constructed. Each device in the system requires eight clock
pulses; therefore, the total number of clock cycles must equal
8N, where N is the total number of devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This prevents any further data from being clocked
into the input shift register.
The serial clock can be a continuous or a gated clock. A continuous SCLK source can be used only if SYNC can be held low
for the correct number of clock cycles. In gated clock mode, a
burst clock containing the exact number of clock cycles must be
used, and SYNC must be taken high after the final clock to latch
the data. Gated clock mode reduces power consumption by
reducing the active clock time.

Rev. A | Page 19 of 20

ADG1414

Data Sheet

OUTLINE DIMENSIONS
7.90
7.80
7.70

24

13

4.50
4.40
4.30
6.40 BSC
1

12

PIN 1
0.65
BSC

1.20
MAX

0.15
0.05
0.30
0.19

0.75
0.60
0.45

8
0

0.20
0.09

SEATING
PLANE

0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 32. 24-Lead Thin Shrink Small Outline Package [TSSOP]


(RU-24)
Dimensions shown in millimeters

4.10
4.00 SQ
3.90

0.60 MAX
2.50 REF
0.60 MAX

3.75 BSC
SQ

0.50
BSC

2.65
2.50 SQ
2.35

EXPOSED
PAD

13

0.50
0.40
0.30

TOP VIEW

1.00
0.85
0.80
SEATING
PLANE

12 MAX

0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF

0.30
0.23
0.18

12

BOTTOM VIEW

0.25 MIN

FOR PROPER CONNECTION OF


THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8

04-11-2012-A

PIN 1
INDICATOR

PIN 1
INDICATOR

24

19
18

Figure 33. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]


4 mm 4 mm Body, Very Thin Quad
(CP-24-3)
Dimensions shown in millimeters

ORDERING GUIDE
Model1
ADG1414BRUZ
ADG1414BRUZ-REEL7
ADG1414BCPZ-REEL7
1

Temperature Range
40C to +125C
40C to +125C
40C to +125C

Package Description
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Z = RoHS Compliant Part.

20092013 Analog Devices, Inc. All rights reserved. Trademarks and


registered trademarks are the property of their respective owners.
D08497-0-1/13(A)

Rev. A | Page 20 of 20

Package Option
RU-24
RU-24
CP-24-3