Evaluation of Crosstalk Avoidance coding schemes

Haard Mehta
Department of Computer Engineering
Rochester Institute of Technology
Rochester, NY
hkm7419@g.rit.edu

Abstract Network-on-chip (NoC) paradigm is one of the

emerging solution which fulfills the large communication
requirements of Multi-Processor SoCs (MP-SoCs). Commercial
designs in todays world are integrating a large number of
embedded blocks on SoCs with the number more likely to
increase in the coming years. In deep submicron technology,
propagation delay is the biggest issue to be solved for high-speed
designs. Crosstalk between adjacent wires on the bus increases
the delay as the delay of the wire is dependent on the electrical
state of its neighboring wire and transitions of signals. Crosstalk
avoidance codes can be employed to reduce the delay caused by
crosstalk and energy dissipation in NoC data streams. Crosstalk
avoidance codes help in reducing coupling capacitance and
improving the signal integrity. In this paper, three crosstalk
avoidance schemes of Forbidden Overlap Condition (FOC),
Forbidden Pattern Code (FPC) and Forbidden Transition code
(FTC) have been implemented and are evaluated in term area,
energy, timing and power dissipation. Shielding can be used by
providing a grounded wire between each signal wire to reduce
the crosstalk. Another pattern named Forbidden Pattern Free
and Fibonacci Numeral System is proposed which utlilizes less
area and power dissipation is also low. The significant results
suggest that area for FTC generated is highest among all the
schemes. The critical length of FOC and FPC is about 1mm while
for FTC it is about 5mm.

KeywordsCrosstalk, FOC, FPC, FTC, Area, Power, Energy.

I.

coupling capacitance exceeds the loading capacitance on the

wires, the delay caused by the wire may be equal to or twice
the length of a wire adjacent to a steady signal which is
referred to as crosstalk delay. [1,3]
Crosstalk causes timing violations, power consumption
and also limits the clock speed for high speed design.
Techniques have been devised to insert shielding between
wires but such techniques also increase the increase the wiring
area. As a result, coding schemes have been developed to
reduce the crosstalk.
In coding schemes, coding takes place in the form of
mapping information bits or the incoming data words into
code words through encoder-decoder units. In this paper, three
crosstalk avoidance schemes have been implemented termed
as Forbidden Overlap Condition (FOC), Forbidden Pattern
Code (FPC) and Forbidden Transition code (FTC) to reduce
the coupling capacitance thereby enhancing system reliability
and reducing communication energy as it avoids the area of
wires being increased.
II. SOC PHYSICAL DESIGN ISSUES
A. Bus Models-Delay Models
The delay of a wire is dependent on the transitions in the wire
and those adjacent to it. The worse case delay is found to be
(1+4) , where represents the delay of the wire free from
the crosstalk and is the ratio of coupling capacitance to bulk
capacitance.

INTRODUCTION

The Network on chip is considered as an effective solution to

the ever increasing integration of embedded and functional
storage blocks on SoCs. The functional blocks in NoC
communicate each other through links and switches which
dissipates a lot of power. Power consumption in deep
submicron technologies has been on a larger scale and low
power designs are being developed to reduce the power
consumption. As the spacing between the wires is decreasing
rapidly, the mutual capacitance between the wires is
increasing. Due to this, coupling capacitance increases which
shows some negative effects on the delay, power, area and
signal integrity. The Miller effect or the Miller Coupling
factor where the transition takes place in opposite direction
has a more adverse effect on the delay. When the cross

Fig.1 Types of capacitances

Fig.1 shows the different types of capacitances induced
between two conductors. The total capacitance can be
decomposed into three components: 1) Area capacitance 2)
Fringe capacitance 3) Lateral capacitance. The horizontal
spacing between two conductors is termed as S. The parameter

H is the height above the substrate and T is the thickness of the

conductor.
Table 1 Coupling capacitance on Victim [1]

Fig.2 Block Diagram of combining channels in FOC

The block diagram of Forbidden Overlap code shows the
design of 32-bit input, for which eight FOC blocks are
required and thus a 32-bit un-coded wire gets converted into a
40-bit coded wire. In FOC, to avoid the worst case coupling
transitions, the maximum coupling factor can be reduced to
three.

Table 1 shows the difference conditions for victim and

aggressors and computes the capacitance on victim.

III. CROSSTALK AVOIDANCE CODING SCHEME

A) Forbidden Overlap Codes (FOC)
A wire has the worst-case delay of (1 + 4 ), when it executes
falling transition and its neighbors execute rising transition.
For satisfying the condition of Forbidden Overlap code, the
codebook cannot have 010 and 101 appearing centered around
any bit position. One simple way to achieve the Forbidden
Overlap code is to use half shielding where one ground wire
follows two signal wires but it requires extra wiring. Hence
encoding the data links is one preferred way to satisfy the
condition but it is not possible to do encoding for all the code
bits considering the practical limitations of size and
complexity in codec. The links are divided into sub channels
and are encoded using CACs and these channels can be
combined in a way to avoid crosstalk.

Fig. FOC Coding scheme [1]

B. Forbidden Pattern Code

In Forbidden Pattern code, the bit patterns 010 and 101 from
every code word are avoided. However, encoding all bits at
once using this is infeasible for large buses due to the
prohibitive complexity of the codec circuits. Therefore, Partial
coding is employed, in which the bus is broken into sub-buses
of smaller width, which are encoded into small channels.
These sub channels are encoded in such a way so as to avoid
crosstalk delay at their boundaries. For implementing FPC
encoder, eight FPC channels are combined together.

Fig.3 Block Diagram of combining channels in FPC

Fig. FPC Coding scheme [1]

C. Forbidden Transition code (FTC)
The transitions between the successive codes should not cause
the neighboring wires to switch in opposite directions like a
code word cannot switch from 01 to10 bit-pattern and from 10
to 01. The maximum coupling factor found in FTC is 2. In
FTC, shielding is inserted after each shielding line. In the
design of 32-bit input FTC, eleven FTC (3-4) blocks are
needed and a 33-bit wire gets converted into a 44-bit wire.

Fig.4 Block Diagram of FTC

0111
1000
1001
1010
1011
1100
1101
1110
1111

001111
011000
011001
011100
011110
011111
110000
110001
110011

IV. IMPLEMENTATION
The implementation is carried out using Synopsys Design
Vision Tool in 65nm technology node. The Verilog code
written in Design Vision tool and simulations are performed
on the top-level module of the encoder and decoder files for
the different crosstalk avoidance schemes designed. The
results determined from Synopsys Design Vision tool is in
terms of area, power and timing analysis.

Table1 Area and Power dissipation for FOC

Fig. FTC Coding scheme [1]

FOC Module

Power in
watts

Area in
(um) 2

Total
area (um)
2

Encoder

2.48E-04

1098.23

2578.95

Decoder

3.01E-04

1480.95

D. FPF-FNS ( Forbidden Pattern Free-Fibonacci Numeral

System)
A Fibonacci based numeral system (FNS) for crosstalk
avoidance is created along with Forbidden Pattern Free code.
FNS based mapping is constructed for the codec design and
digital binary system is taken into consideration for the one
and only representation possible for a number.
Table shows the 6 bit code-words for 4 bit data-words which
are generated using FNS-FPF codes. The coded busses in the
simulation are 6-bits wide. A 4- to-6-bit encoder and a 6-to-4bit decoder logic were implemented using mapping of data
words to code-words using FPF code-words. The simulation is
carried out using Synopsys Design Vision tool.

Table FPF-FNS data words-code words

4 bit Data words
0000
0001
0010
0011
0100
0101
0110

6 bit code words

000000
000001
000011
000110
000111
001100
001110

Table 2 Area and Power dissipation for FTC

FPC
Module

Power in
watts

Area in (um)
2

Total area
(um) 2

Encoder

3.8E-04

1772.15

4343.02

Decoder

6.9E-04

2570.87

Table 3 Area and Power dissipation for FPC

FTC
Module

Power in
watts

Area in (um)
2

Total area
(um) 2

Encoder

4.65E-04

1853.2799

3356.0789

Decoder

3.92E-04

1502.799

Table 4 Area and power dissipation for FPF-FNS

FPFFNS
Module

Power in
watts

Area in
(um) 2

Encoder

6.75E-04

1842

Decoder

1.38E-07

682.23

Total area
(um) 2
Fig.5 Estimated capacitance in global wires [3]
2524.23
For coded wires, the capacitance per unit length is calculated
using the parallel plate model consisting of inter and intralevel contributions along with a fringe component. The worst
case capacitance per unit length is given by [3]

Table 5 Coupling capacitance

CAC
FOC
FPC
FTC

Coupling capacitance
(pF/mm)
0.163
0.128
0.128

The power and energy for un-coded wires is measured by

P=E*f
For assumption of capacitance, Saraswat et.al [3,4] have
proposed Worst case capacitance per unit length for global
wires in future. The 65nm technology node is used here for the
measurements of all the parameters and the estimated
capacitance for 65nm technology node is about 0.2 pF/mm
which can be estimated from the graph shown below.

Here,
is the wire capacitance per unit length,
is the
dielectric constant assumed to be homogeneously distributed
both between layers and between metal lines within a layer,
is the permittivity of free space, and AR is the aspect ratio of
the wire defined as the thickness to width ratio of the metal.[
3,4]. The estimated capacitance for FOC comes out to be
0.163 pF with a coupling factor of 3, while it is 0.128 for both
FPC and FTC with a coupling factor of 2. The delay for the
wire is calculated again using the graph shown below.

Table 7 FOC Delay for different length

Length
1
2
3
4
5
6
7
8
9
10

Delay (Ps)
17.604
35.208
52.812
70.416
88.02
105.624
123.228
140.832
158.436
174.06

Table 8 FTC Delay for different length

Fig.6 Estimated Delay [3]

The delay is calculated using the estimated resistance and
capacitance through the following formula [3]:
Delay=0.4xRwxCw
The power and energy are calculated for different lengths
varying from 1 to 10 for both coded and un-coded wires.

Table 6 Power for un-coded wires

LENGTH(MM)

POWER(WATT)

ENERGY

0.5E-03

0.2E-12

1E-03

0.4E-12

1.5E-03

0.6E-12

2E-03

0.8E-12

2.5E-03

1E-12

3E-03

1.2E-12

3.5E-03

1.4E-12

4E-03

1.6E-12

4.5E-03

1.7E-12

10

5E-03

1.8E-12

Length
1
2
3
4
5
6
7
8
9
10

Delay (Ps)
13.824
27.648
41.472
55.296
69.12
82.994
96.778
110.59
124.416
138.24

Table 9 FPC Delay for different length

Length
1
2
3
4
5
6
7
8
9
10

Delay (Ps)
14.267
29.682
44.321
59.432
74.145
89.568
104.761
119.310
134.50
149.20

TABLE 10 FOC POWER AND ENERGY

TABLE 12 POWER AND ENERGY FOR FPC

LENGTH

POWER(WATT)

ENERGY

LENGTH

POWER

ENERGY

5.89E-04

1.03E-14

8.87E-04

1.56E-14

6.29E-04

4.42E-14

9.17E-04

6.45E-14

6.69E-04

1.05E-13

9.47E-04

1.5E-13

7.09E-04

1.99E-13

9.77E-04

2.75E-13

7.49E-04

3.29E-13

1.0E-03

4.4E-13

7.89E-04

5.0E-13

1.03E-03

6.52E-13

8.29E-04

7.15E-13

1.06E-03

9.14E-13

8.69E-04

9.79E-13

1.09E-03

1.2E-12

9.29E-04

1.32E-12

1.12E-03

1.59E-12

10

9.69E-04

1.705E-12

10

1.15E-03

2.02E-12

Table 11 FTC Power and Energy calculations

LENGTH

POWER

ENERGY

1.39E-03

1.92E-14

1.71E-03

9.45E-14

0.004

2.03E-03

2.52E-13

0.003

2.35E-03

5.19E-13

2.67E-03

9.22E-13

3E-03

1.49E-12

3.31E-03

2.24E-12

3.63E-03

3.2E-12

3.9E-03

4.3E-12

10

4.27E-03

5.9E-12

0.006
0.005
Power
(Uncoded)
FOC
Power(watts)

0.002
0.001
0
0

10

15

Fig.7 Plot for Critical length in FOC Power

Fig.10 Plot for Un-coded Power

0.006

Table 13 Critical Length calculations

0.005
0.004

CAC scheme
FOC
FPC
FTC

Power
(Uncoded)

0.003

FTC
Power(Watts)

0.002
0.001

Length (mm)
1
5
2

0
0

10

15

CONCLUSION

Fig.8 FTC Critical length graph

0.006
0.005
0.004

Power
(Uncoded)

0.003

Thus, Network on chip is considered as one of the promising

solution for crosstalk avoidance. Crosstalk avoidance is one of
the major issue in deep submicron technology. In this paper,
different crosstalk avoidance schemes have been presented
which try to reduce the crosstalk in wires. Apart from the three
schemes described, some new schemes like Fibonacci based
numeral method are existing, which shows better results in
terms of area, energy and power the crosstalk in wires. Apart
from the three schemes described, some new schemes like
Fibonacci based numeral method is described, which shows
better results in terms of area, energy and power.

FPC
Power(Watts)

0.002
0.001

ACKNOWLEDGMENT

0
0

10

The author would like to thank Dr. Amlan Ganguly for his
valuable advice throughout the project.

15

Fig.9 Plot for FPC Critical length

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[2]

Power (Uncoded)
0.006

[3]
[4]

0.004
Power
(Uncoded)

0.002
0
0

10

15

[5]

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